Run-Time Reverse Engineering to Optimize DRAM Refresh

Transcription

1 Run-Time Reverse Engineering to Optimize DRAM Refresh Deepak M. Mathew, Eder F. Zulian, Matthias Jung, Kira Kraft, Christian Weis, Bruce Jacob, Norbert Wehn

2 Bitline The DRAM Cell 1 Wordline Access Transistor Storage Capacitor 0 Data is stored by capacity Cell is selected with access transistor Charged capacitor represents a 1 Discharged capacitor represents a 0 Memory is volatile Cell is leaky Refresh needed dynamic 2

3 How Refresh is Performed? DRAM controller sends AREF commands every t REFI (eg. 7.8 µs for Temp. < 85 C) AREF AREF AREF Single AREF command refreshes multiple rows in all banks ( eg. 2 rows in all 8 banks for 2Gb DDR3 DRAM) t RFC t REFI t REFI Bank 4 Bank 5 Bank 6 Bank 7 Bank 0 Bank 1 Bank 2 Bank 3 3

4 Impact of Refresh Refresh Performance Impact Refresh Energy Overhead 50% 50% 45% 45% 40% 40% 35% 35% 30% 30% 25% 25% 20% 20% 15% 15% 10% 10% 5% 5% 0% 2 Gb 4 Gb 8 Gb 16 Gb 32 Gb 64 Gb 0% 2 Gb 4 Gb 8 Gb 16 Gb 32 Gb 64 Gb High Temperatures Worsen The Behaviour J. Liu, et al. RAIDR: Retention-Aware Intelligent DRAM Refresh, ISCA 2012 I. Bhati, et al. DRAM Refresh Mechanisms, Trade-offs and Penalties, IEEE Trans

5 Reducing Refresh Overhead Selective Refresh Retention Aware Refresh Approximate DRAM Different rows need to be refreshed at different rates

6 Drawbacks of Auto-Refresh AREF lacks flexibility No access to internal refresh row counter No rows can t be skipped The complete DRAM has to be refreshed in the same rate Selective Refresh Retention Aware Refresh Approximate DRAM 6

7 Row-Granular Refresh (RGR) RGR (B1, R1) = ACT (B1, R1) t RAS t RAS limits the single refresh execution time Violate t RAS?? PRE (B1) Mimics AREF by sending ACT and PRE commands to specific rows Performance and Energy savings by skipping unncessary refreshes Follow strict JEDEC timings for t RAS Proven to be inefficient compared to AREF ** 7 **Ishwar Bhati, et al. Flexible Auto-Refresh, ISCA 2015

8 DRAM Sensing ACT RD PRE Large t RAS timing to compensate for bitline voltage drop t RAS 8 Patent Pending

9 DRAM Sensing: Refresh ACT PRE No voltage drop due to Read/ Write. Therefore t RAS can be reduced for performing RGR But, how much reduction possible? t RAS * Patent Pending

10 Minimum t RAS for Vendor A t RAS, min timer is present for additional saftey Vendor specific implementations Reverse engineering technique performed during DRAM initialization, or during normal operation Command DQS ACT B1,R1 min t RAS t RAS t RAS = 37.5 ns t min RAS = 20.7 ns PRE B1 t RP RD B1 Patent Pending 10

11 Minimum t RAS for Vendor B & C t RCD violation Command ACT B1,R1 PRE B1 ACT B1,R2 RD B1 DQ FFFF XXX min t RAS t RAS t RAS = 37.5 ns t min RAS = 22 ns Patent Pending 11

12 Advanced Refresh Controller DRAM initialization & Calibration Determination of minimum t RAS Perform AREF Apply timings to perform ORGR Intermediate calibration of t RAS Patent Pending

13 RGR vs ORGR (2Gb x16 DDR3) RGR ORGR t RFC = 158 ns Patent Pending 13 t RFC = ns

14 Hardware Measurements Precise control of temperature (heating and cooling) of DRAM SO-DIMMs Measuring currents / power of DRAM SO- DIMMs Can be applied to any DDR3/4 SO-DIMM based platform (FPGA, CPU ) Measuring retention errors 14

15 Effect on Retention Behavior 30 C 90 C

16 Performance and Energy Savings Refresh Technique t RFC Refresh Energy Auto Refresh Measured for 4Gb x16 DDR3 DRAM from Vendor A Refreshing the complete DRAM RGR ORGR

17 Simulation for 16Gb DDR4 DRAM Estimation of Timings and Currents for Future 16Gb DDR4 device Estimation of DRAM Power consumption for ORGR Memory Subsystem Model based on SystemC-TLM2 Performance Evaluation of ORGR

18 Simulation Results Performance Energy Application with Sparse Access Pattern

19 Conclusion Presented an invented technique (ORGR) to optimize Row Granular Refresh using reduced t RAS Reverse engineering techniques to determine the minimum t RAS for major DRAM vendors by reading the internal DRAM counter Hardware proven for DDR3 DRAMs Evaluated benefits for applications with various access patterns DDR4 hardware evaluations in progress

20 Thank You