Risk Factors. Rev. 4/19/11

Transcription

1 Risk Factors Today s presentations contain forward-looking statements. All statements made that are not historical facts are subject to a number of risks and uncertainties, and actual results may differ materially. Please refer to our most recent Earnings Release and our most recent Form 10-Q or 10-K filing for more information on the risk factors that could cause actual results to differ. If we use any non-gaap financial measures during the presentations, you will find on our website, intc.com, the required reconciliation to the most directly comparable GAAP financial measure. Rev. 4/19/11

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3 Today s News The world s first 3-D Tri-Gate transistors on a production technology New 22nm transistors have an unprecedented combination of power savings and performance gains. These benefits will enable new innovations across a broad range of devices from the smallest handheld devices to powerful cloud-based servers. The transition to 3-D transistors continues the pace of technology advancement, fueling Moore s Law for years to come. The world s first demonstration of a 22nm microprocessor -- code-named Ivy Bridge -- that will be the first high-volume chip to use 3-D Tri-Gate transistors.

4 Lower Transistor Leakage Lower Active Power Active Power per Transistor (normalized) Energy-Efficient Performance Built on Moore s Law 1 1x 65nm 45nm 32nm 22nm 0.1x 0.01x > 50% reduction 0.001x Higher Transistor Performance (Switching Speed) Source: Intel 0.1 Constant Performance 65nm Planar 45nm Planar 32nm Planar 22nm Tri-Gate 22 nm Tri-Gate transistors increase the benefit from a new technology generation Source: Intel

5 Transistor Innovations Enable Technology Cadence nm 65 nm 45 nm 32 nm 22 nm Invented SiGe Strained Silicon 2 nd Gen. SiGe Strained Silicon Invented Gate-Last High-k Metal Gate 2 nd Gen. Gate-Last High-k Metal Gate First to Implement Tri-Gate Strained Silicon High k Metal gate Tri-Gate

6 Transistor Innovations Enable Cost Benefits of Moore s Law to Continue 1 200mm 0.1 $ / Transistor (relative to 0.35um) 300mm um.25um.18um.13um 90nm 65nm 45nm 32nm 22nm 14nm 10nm Source: Intel

7 22 nm Manufacturing Fabs D1D -- Oregon D1C -- Oregon Fab Arizona Fab Israel Fab Arizona 22nm upgrades to be completed

8 Tri-Gate Invented Tri-Gate Achievement Results from Long Term Commitment to Research Internal Research Tri-Gate Selected for 22nm node Pathfinding Development CE! transfer Manufacturing Tri-Gate Mfg Single-fin transistor demonstrated Multi-fin transistor demonstrated Tri-gate SRAM cells demonstrated Tri-gate RMG process flow developed Tri-gate optimized for HVM Bringing innovative technologies to HVM is the result of a highly coordinated internal research-development-manufacturing pipeline

9 For years we have seen limits to how small transistors can get, said Gordon E. Moore. This change in the basic structure is a truly revolutionary approach, and one that should allow Moore s Law, and the historic pace of innovation, to continue.

10 22 nm 3-D Tri-Gate Transistor 3-D Tri-Gate transistors form conducting channels on three sides of a vertical fin structure, providing fully depleted operation Transistors have now entered the third dimension! Source: Intel

11 22 nm 3-D Tri-Gate Transistor Source: Intel Gates Fins

12 Source: Intel 32 nm Planar Transistors 22 nm Tri-Gate Transistors

13 Std vs. Fully Depleted Transistors Bulk Transistor Gate Oxide Gate Inversion Layer Source Drain Depletion Region Silicon Substrate Substrate voltage exerts some electrical influence on the inversion layer (where source-drain current flows) The influence of substrate voltage degrades electrical sub-threshold slope (transistor turn-off characteristics) NOT fully depleted Source: Intel

14 Std vs. Fully Depleted Transistors Partially Depleted SOI (PDSOI) Gate Floating Body Source Drain Oxide Silicon Substrate Source: Intel Floating body exerts some electrical influence on inversion layer, degrading sub-threshold slope NOT fully depleted Not used by Intel

15 Std vs. Fully Depleted Transistors Fully Depleted SOI (FDSOI) Gate Source Drain Extremely Thin Silicon Layer Oxide Silicon Substrate Floating body eliminated and sub-threshold slope improved Requires expensive extremely thin SOI wafer, which adds ~10% to total process cost Not used by Intel Source: Intel

16 Std vs. Fully Depleted Transistors Fully Depleted Tri-Gate Transistor Gate electrode controls silicon fin from three sides providing improved sub-threshold slope Inversion layer area increased for higher drive current Process cost adder is only 2-3% Source: Intel

17 Transistor Operation On Current Planar Channel Current (normalized) Threshold Voltage Off Current Gate Voltage (V) Operating Voltage Maximize current in on state (for improved performance) Minimize current in off state (for lower power) Switch very quickly between the two states (for performance) Source: Intel

18 Transistor Operation Planar Channel Current (normalized) Tri-Gate Reduced Leakage Gate Voltage (V) The fully depleted characteristics of Tri-Gate transistors provide a steeper sub-threshold slope that reduces leakage current Source: Intel

19 Transistor Operation Channel Current (normalized) Tri-Gate Tri-Gate Reduced Threshold Voltage Gate Voltage (V) Reduced Operating Voltage The steeper sub-threshold slope can also be used to target a lower threshold voltage, allowing transistors to operate at lower voltage to reduce power and/or improve switching speed Source: Intel

20 Transistor Gate Delay Transistor Gate Delay (normalized) Slower 32 nm Planar Lower Voltage Operating Voltage (V) Transistor gate delay (switching speed) slows down as operating voltage is reduced Source: Intel

21 Transistor Gate Delay Transistor Gate Delay (normalized) 22 nm Planar 32 nm Planar Operating Voltage (V) 22 nm planar transistors could provide some performance improvement, but would still have poor gate delay at low voltage Source: Intel

22 Transistor Gate Delay Transistor Gate Delay (normalized) 37% Faster 32 nm Planar 22 nm Tri-Gate 18% Faster Operating Voltage (V) 22 nm 3-D Tri-Gate transistors provide improved performance at high voltage and an unprecedented performance gain at low voltage Source: Intel

23 Transistor Gate Delay Transistor Gate Delay (normalized) 22 nm Tri-Gate 32 nm Planar -0.2 V Operating Voltage (V) 22 nm 3-D Tri-Gate transistors can operate at lower voltage with good performance, reducing active power by >50% Source: Intel

24 3-D Tri-Gate Transistor Benefits Dramatic performance gain at low operating voltage, better than Bulk, PDSOI or FDSOI 37% performance increase at low voltage >50% power reduction at constant performance Improved switching characteristics (On current vs. Off current) Higher drive current for a given transistor footprint Only 2-3% cost adder (vs. ~10% for FDSOI) 3-D Tri-Gate transistors are an important innovation needed to continue Moore s Law Source: Intel

25 22nm Product Update Dadi Perlmutter Executive Vice President General Manager, Intel Architecture Group

26 22nm Silicon Technology Breakthrough Benefits Broad Range of Intel Architecture Devices New 22nm 3-D transistors deliver unprecedented performance improvement and power reduction for Intel s product portfolio This benefits smallest handhelds to powerful cloud-based servers 37% performance increase at low voltage vs. 32nm planar transistors* Consumes only half the power at the same performance level as 2-D transistors on 32nm planar chips* * Based on Intel Internal Data

27 Intel Architecture Spans The Compute Continuum Servers / Cloud Desktops Laptops Netbooks Tablets Smartphones Smart TVs Embedded

28 IA Processor Cores Built on a Common Architecture with Optimized Micro-Architectures Intel Architecture 45nm 32nm 22nm Optimized Power Performance Microarchitecture Nehalem Westmere Nehalem Microarchitecture Sandy Bridge Ivy Bridge Sandy Bridge Microarchitecture Future Low Power Microarchitecture Bonnell Microarchitecture Saltwell Microarchitecture Future Microarchitecture Source: Intel

29 Newest Manufacturing Technology Delivers Ivy Bridge 45 nm Process Technology 32 nm Process Technology 22 nm Process Technology Penryn Intel Core Microarchitecture Nehalem NEW Intel Microarchitecture Westmere Intel Microarchitecture (Nehalem) Sandy Bridge NEW Intel Microarchitecture Ivy Bridge Intel Microarchitecture (Sandy Bridge) TICK TOCK TICK TOCK TICK Cadence of Innovation Delivers New Microprocessor Efficiency on the 22 nm Process Intel s First 22 nm Processor

30 Ivy Bridge Sandy Bridge Migrated to 22nm Process Technology Client: Efficient performance for thin and light form factors Increased performance vs. today s 2 nd generation Intel Core product family Enhanced media and graphics performance with processor graphics Enhanced security features Server: Increased performance and improved efficiency Integrated Storage Features Further Demonstrating Intel Product and Process Leadership

31 Ivy Bridge Client Roadmap 22nm Delivers Balance of Performance and Power Efficiency! Desktop Extreme / High-End Desktop Waimea Bay Platform Sandy Bridge-E (32nm) Patsburg X (LGA 2011) Desktop Performance / Mainstream Maho Bay Platform Ivy Bridge (22nm) Mobile Extreme / Performance / Mainstream / Ultra Low Voltage Processor Chipset Panther Point (LGA 1155) Chief River Platform Ivy Bridge (22nm) Panther Point (LGA 1155) Future Intel Microarchitecture All products, dates, and figures specified are preliminary based on current expectations, and are subject to change without notice.

32 Data Center Roadmap Transitioning to 22nm Across the Data Center Portfolio 2011 Boxboro-MC Platform Itanium Platforms Intel Itanium 9300 Processor Poulson Processor 22nm Kittson Processor E7 Platforms Boxboro-EX Platform Intel Xeon Processor E7-8800/4800/2800 Product Family Future Platform 22 nm Ivy Bridge Based Processor Efficient Performance Platforms Tylersburg-EP Platform Intel Xeon Processor 5600/5500 Series Romley - EP Platform Sandy Bridge-EP Processor 22 nm Ivy Bridge Based Processor Bromolow Platform E3 Platforms Intel Xeon Processor E Product Family 22 nm Ivy Bridge Based Processor MIC co-processor Knights Ferry SDV 22nm Knights Corner Co-Processor All products, dates, and figures specified are preliminary based on current expectations, and are subject to change without notice.

33 INTEL ARCHITECTURE FOR LOW POWER COMPUTING

34 IA Platforms for Low Power Segments Optimized Performance for Phones, Tablets, and Consumer Electronics 1 st Gen 45 nm 2 nd Gen 45 nm 3 rd Gen 32 nm 4 th Gen 22 nm Consumer Electronics Diamondville Groveland Pine Trail Sodaville Cedar Trail Future Future Tablets / Embedded Menlow Moorestown Oak Trail Tunnel Creek Clover Trail Future Smart Phones Medfield Future All products, dates, and figures specified are preliminary based on current expectations, and are subject to change without notice.

35 Intel Atom Processor Evolution Higher Performance with Faster Media and Graphics in the same power envelope 1 st and 2 nd Gen 45 nm 3 rd Gen 32 nm 4 th Gen 22 nm Architectural Improvements 10X CPU Thermal Power Reduction* 50X Platform Idle Power Reduction* 1.5X CPU Performance per watt* Process Technology Improvements 10X Lower Leakage Transistors* ~2X Lower Active Power Transistors* ~2X Density Improvements* * Compared to previous generation of Atom processors

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37 Legal Notices and Disclaimers INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS. Intel may make changes to specifications and product descriptions at any time, without notice. All products, dates, and figures specified are preliminary based on current expectations, and are subject to change without notice. Intel, processors, chipsets, and desktop boards may contain design defects or errors known as errata, which may cause the product to deviate from published specifications. Current characterized errata are available on request. Any code names featured are used internally within Intel to identify products that are in development and not yet publicly announced for release. Customers, licensees and other third parties are not authorized by Intel to use code names in advertising, promotion or marketing of any product or services and any such use of Intel's internal code names is at the sole risk of the user. Intel product plans in this presentation do not constitute Intel plan of record product roadmaps. Please contact your Intel representative to obtain Intel s current plan of record product roadmaps. Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products. For more information go to Intel, Intel Inside, the Intel logo, Centrino, Centrino Inside, Intel Core, Intel Atom and Pentium are trademarks of Intel Corporation in the United States and other countries. Material in this presentation is intended as product positioning and not approved end user messaging. This document contains information on products in the design phase of development. *Other names and brands may be claimed as the property of others. Copyright 2011 Intel Corporation, All Rights Reserved

38 Risk Factors The above statements and any others in this document that refer to plans and expectations for the second quarter, the year and the future are forward-looking statements that involve a number of risks and uncertainties. Words such as anticipates, expects, intends, plans, believes, seeks, estimates, may, will, should, and their variations identify forward-looking statements. Statements that refer to or are based on projections, uncertain events or assumptions also identify forwardlooking statements. Many factors could affect Intel s actual results, and variances from Intel s current expectations regarding such factors could cause actual results to differ materially from those expressed in these forward-looking statements. Intel presently considers the following to be the important factors that could cause actual results to differ materially from the company s expectations. Demand could be different from Intel's expectations due to factors including changes in business and economic conditions, including supply constraints and other disruptions affecting customers; customer acceptance of Intel s and competitors products; changes in customer order patterns including order cancellations; and changes in the level of inventory at customers. Potential disruptions in the high technology supply chain resulting from the recent disaster in Japan could cause customer demand to be different from Intel s expectations. Intel operates in intensely competitive industries that are characterized by a high percentage of costs that are fixed or difficult to reduce in the short term and product demand that is highly variable and difficult to forecast. Revenue and the gross margin percentage are affected by the timing of Intel product introductions and the demand for and market acceptance of Intel's products; actions taken by Intel's competitors, including product offerings and introductions, marketing programs and pricing pressures and Intel s response to such actions; and Intel s ability to respond quickly to technological developments and to incorporate new features into its products. The gross margin percentage could vary significantly from expectations based on capacity utilization; variations in inventory valuation, including variations related to the timing of qualifying products for sale; changes in revenue levels; product mix and pricing; the timing and execution of the manufacturing ramp and associated costs; start-up costs; excess or obsolete inventory; changes in unit costs; defects or disruptions in the supply of materials or resources; product manufacturing quality/yields; and impairments of long-lived assets, including manufacturing, assembly/test and intangible assets. Expenses, particularly certain marketing and compensation expenses, as well as restructuring and asset impairment charges, vary depending on the level of demand for Intel's products and the level of revenue and profits. The majority of Intel s non-marketable equity investment portfolio balance is concentrated in companies in the flash memory market segment, and declines in this market segment or changes in management s plans with respect to Intel s investments in this market segment could result in significant impairment charges, impacting restructuring charges as well as gains/losses on equity investments and interest and other. Intel's results could be affected by adverse economic, social, political and physical/infrastructure conditions in countries where Intel, its customers or its suppliers operate, including military conflict and other security risks, natural disasters, infrastructure disruptions, health concerns and fluctuations in currency exchange rates. Intel s results could be affected by the timing of closing of acquisitions and divestitures. Intel's results could be affected by adverse effects associated with product defects and errata (deviations from published specifications), and by litigation or regulatory matters involving intellectual property, stockholder, consumer, antitrust and other issues, such as the litigation and regulatory matters described in Intel's SEC reports. An unfavorable ruling could include monetary damages or an injunction prohibiting us from manufacturing or selling one or more products, precluding particular business practices, impacting Intel s ability to design its products, or requiring other remedies such as compulsory licensing of intellectual property. A detailed discussion of these and other factors that could affect Intel s results is included in Intel s SEC filings, including the report on Form 10-K for the fiscal year ended Dec. 25, 2010.