Intel Corporation Silicon Technology Review

Transcription

1 Intel Corporation Silicon Technology Review Ken David Director, Components Research SEMI Strategic Business Conference April 2003

2 Agenda Corporate Mission Leadership in Technology Leadership in Integration How do we continue to succeed? Investments Research and Development Manufacturing Excellence Supplier Expectations Summary 2

3 Entering A New Era Converged Computing and Communications Microprocessors Memory 3

4 Leadership by Technology Desktop Server 4

5 Leadership by Integration Intel PXA800F Processor Intel Mobile Technology Intel OnChip Flash 4MB/512kB GSM/GPRS Power Management Intel MicroSignal Architecture Intel XScale Core & Peripherals SRAM 512kB/64kB 5

6 How do we continue to lead? Commitment through investments Commitment through advanced research and development new technologies Continued, successful implementation of Moore s Law Commitment through manufacturing excellence 6

7 Intel Capital Expenses 25 Capital Ex: Intel v. Competitors (00-03) *Estimate Billions($) Intel Competitor 1 Competitor 2 Competitor 3 Source: Intel 7

8 Intel R&D Investment ($M) $4,000 $3,897 $3,800 $4,000 est. $3,111 $1,808 $2,347 $2,509 $517 $618 $780 $970 $1,111$1, Source: Intel Annual Report 8

9 Worldwide Intel R&D Presence 75+ labs and over 7,000 R&D professionals California USA Washington USA Oregon USA Illinois USA New Mexico, USA Copenhagen, Denmark Stockholm, Glasgow, Sweden Scotland Gdansk, Poland Swindon,, UK Shannon, Ireland Braunschweig, Ulm Nice, France Germany Barcelona, Spain Nizhny Novgorod, Sarov Russia Beijing Shanghai China Arizona USA Haifa, Israel Delhi Bangalore Mumbai India Tsukuba Tokyo Japan Decentralized Approach Fosters Innovation 9

10 Technology Focus: Microprocessor Products Research Groups are de-centralized Multiple sites Central Technology Development groups Logic: Hillsboro, Oregon Memory: Santa Clara, California Packaging: Chandler, Arizona Copy Exactly! from Development into Manufacturing Fastest and Highest Volume Manufacturing Ramp 10

11 Technology Focus: Logic Actual Forecast Process Name P858 Px60 P1262 P1264 P1266 P1268 P st Production Lithography Node nm Gate Length nm Fab Development Research Copy Exactly! Pathfinding 11

12 Leadership through Technology Mission to continue to provide leading edge technology in computing and communications Financial Challenges Technology Challenges Increasing chip complexity aggressive scaling new materials added features (integrated capabilities) New concerns: Power, heat 12

13 Moore s Law... in the beginning 1965 Transistor Projection 1975 Transistor Projection 13

14 Moore s Law Today 1,000,000, ,000,000 10,000,000 1,000, ,000 10,000 1, Itanium Processor Pentium 4 Processor Pentium III Processor Pentium II Processor Pentium Processor 486 DX Processor 386 Processor Million Heading toward 1 billion transistors in

15 Moore s Law Economics (Source: Intel, VLSIR) Wafer size, mm Fab cost, $B Fab capacity, kwpm $B/kwpm ~77 (200mm- equivalent)

16 Evolution of Intel Process Node 0.25µm 0.18 µm 130nm 90nm 65nm 45nm 32nm 22nm Litho DUV 193nm 193/157?? Metal Al Cu? ILD SiO2 SiOF SiOC?? Gate Ox SiO2 High-k???? Gate Electrode Poly Metal??? New Materials New Structures New Processes Extending Moore s Law! 16

17 Success in 90nm development Silicide Layer Silicon Gate Electrode 1.2 nm SiO 2 Gate Oxide Strained Silicon 50nm Low K ILD Low K etch stop Advanced Cu barriers Cu interconnects 17

18 Driving Moore s Law Further 90nm Node nm Node nm Length (IEDM2002) 30nm Prototype (IEDM2000) 45nm Node nm Prototype (VLSI2001) 32nm Node nm 25 nm 22nm Node nm Prototype (IEDM2001) 10nm Prototype (ITJ 2002) 18

19 Working on Advanced Transistor Architecture New Process Need New Materials Gate Drain Source World record breaking NMOS performance demonstrated today! 19

20 Intel Lithography Roadmap 1000 ITRS Nodes 1/2 Pitch (nm) 100 Dual Wavelength Strategy 130nm Node 90nm Node 65nm Node 45nm Node 32nm Node 10 i-line DUV i-line DUV DUV 193nm DUV 193nm 193nm 157nm 193nm EUV 157nm EUV EUV

21 157nm Lithography nm lithography is maturing: Research tools shipping in 2003 Development tools scheduled for 2004 Single layer resists are making rapid progress 21

22 EUV Lithography - Full Field ETS images (using 0.1 NA system) 100 nm Elbows 1:1 80 nm Elbows 1:1 200 mm Wafer 100 nm contacts 1:1 4x5 matrix 24 x 32.5 mm 2 field Printing 80 nm images at 0.1 NA is equivalent to printing 32 nm with 0.25 NA production system 152 mm 2, 4X Reflective Mask 22

23 Leadership By Integration Computing + Communications on One Chip Silicon Level Integration Functions combined on single chip Package Level Integration Stacked discrete chips and packages Functions on Discrete Chips Flash, Applications processors, Cellular chipsets

24 Wireless Internet on a Chip by Flash+Logic Integration Intel PXA800F Processor Flash 0.16µm 2 Flash Cell Intel OnChip Flash 4MB/512kB GSM/GPRS Power Management Intel MicroSignal Architecture Intel XScale Core & Peripherals SRAM 512kB/64kB Logic 90nm 90nm Transistor Gate 24

25 Continued Manufacturing Excellence 0.13 µm m manufacturing leadership Worldwide Presence Intel Manufacturing Philosophy Technology Development and Manufacturing Linked Copy Exact! Transfer of Processes Manufacturing Efficiency 300mm Production Leading Edge Capacity 25

26 Intel s High Volume Manufacturing Sites Washington Systems Mfg. Oregon Dev D1C/D1D Fab 15/20 Board Mfg. California Dev D2 Sub-con Mfg. Arizona Fab12/22 A/T Dev New Mexico Fab 11/11X Colorado Fab 23 Mass. Fab 17 Costa Rica Ireland Fab 14/24 San Jose A/T Brazil Sub-con Mfg. Israel Fab 8/18 Thailand Sub-con Mfg. Malaysia China Pudong A/T Sub-con Mfg. Penang A/T Kulim A/T Kulim Board/Module Mfg. Sub-con Mfg. Taiwan Sub-con Mfg. Philippines Manila A/T Cavite A/T 26

27 0.13µm(130nm) Leadership Breaking Away from the competition F11X 300mm Wafer Starts F20 F17 D2 F22 D1C 200mm Nearest CPU Competitor Q1 Q2 Q3 Q4 Q1 Q Q3 Q4 Q1 Q2 Q3 Q4 Source: Intel 27

28 Logic Development: Linking 300mm Research, Development, and D1D: 300mm 65nm Development Production D1C/F25: D1C: 300mm 300mm 0.13µm 130nm Production Production 90nm Development 90nm Development and Production RP1: 300mm Research RP1: F20: 300mm 200mm 0.13µm Research Production Source: Intel 28

29 Manufacturing Efficiency $ Capital spending per die of output capacity.18um.13um.13um.09um 200 mm 300 mm Source: Intel 29

30 Scale: Leading Edge Capacity F24 90nm 0.13u F11X 300mm WSPW D1C F11X D2 F22 F17 D1C 300mm F20 Q Q+1 Q+2 Q+3 Q+4 Q+5 Q+6 Q+7 (Quarter in Ramp) **Source: Intel Estimates 30

31 Supplier Expectations Manufacturing excellence Timely, cost-efficient support during HVM ramp Quality systems Advanced Development New equipment and capabilities matched with Intel s roadmap Process Development Research Collaborative efforts to foster innovation 31

32 Summary Intel is committed to the future technologies Success starts with the present 90nm technology innovation 90nm ramp in 2H 03...and leads to the future continued extension of Moore s Law Package level integration System on a chip 32

33 For further information on Intel's silicon technology and Moore s Law, please visit the Silicon Showcase at 33