Implementing Double Data Rate I/O Signaling in Stratix & Stratix GX Devices. Introduction. DDR I/O Elements. Input Configuration

Transcription

1 Implementing Double Data Rate I/O Signaling in Stratix & Stratix GX Devices November 2002, ver. 2.0 Application Note 212 Introduction Typical I/O architectures transmit a single data word on each positive clock edge and are limited to the associated clock speed. To achieve a 400-megabits per second (Mbps) transfer rate, a system requires a 400-MHz clock. Many new applications have introduced a double data rate I/O (DDRIO) architecture to enhance single data rate (SDR) architectures, which allows for faster throughput. While SDR architectures capture data on one edge of a clock. The DDR architectures captures data on both edges of the clock, doubling the throughput for a given clock and accelerating performance. For example, a 200-MHz clock can capture a 400-Mbps data stream, enhancing system performance and simplifying board design. Stratix TM and Stratix GX devices feature dedicated DDR I/O circuitry. This circuitry allows you to build applications that use DDR signaling, such as memory interfaces including DDR SDRAM, fast cycle random access memory (FCRAM), and quad data rate static random access memory (QDR) as well as implement high-speed interface standards. This application note describes the DDR I/O capabilities of Stratix and Stratix GX devices, including I/O element (IOE) details and DDR I/O implementation using the Quartus II software. DDR I/O Elements Each IOE contains six registers and one latch. Two registers and a latch are used for input, two registers are used for output, and two registers are used for output enable control. The functionality of these registers is described below for input, output, and bidirectional pin configuration. Input Configuration When the IOE is configured as an input pin, input registers A I, B I, and latch C I implement the input path for DDR I/O. Figure 1 shows an IOE configured for DDR inputs for a Stratix or Stratix GX device. Altera Corporation 1 AN

2 Figure 1. Input DDR I/O Path Configuration D Q dataout_l Data_in INPUT Input Reg A I neg_reg_out D Q LA TCH Latch D Q ENA dataout_h Logic Array Input Reg B I Latch C I inclock On the rising edge of the clock, the positive-edge triggered register (A I ) acquires the first bit of data. On the corresponding falling edge of the clock, the negative-edge triggered register (B I ) acquires the second bit of data. For a successful data transfer to the logic array, the latch (C I ) synchronizes the data from register B I to the positive edge of the clock. Output Configuration The dedicated output registers for Stratix and Stratix GX devices are labeled A O and B O. These positive-edge triggered registers and a multiplexer are used for implementing the output path for DDR I/O. Figure 2 shows the IOE configuration for DDR outputs in Stratix and Stratix GX devices. 2 Altera Corporation

3 Figure 2. Output DDR I/O Path Configuration oe D Q OE Reg A OE (2) OR2 D Q Logic Array OE Reg B OE (1) datain_l D Q Output Reg Ao 0 1 TRI OUTPUT dataout datain_h D Q outclock Output Reg Bo Notes to Figure 2: (1) Register B OE generates the delayed enable signal for DDR SDRAM applications. (2) Register A OE generates the enable signal for general-purpose DDR I/O applications. On the positive edge of the clock, two consecutive data bits are captured in registers Ao and Bo. The outputs of these two registers are fed to the inputs of a 2-to-1 multiplexer, which uses the output register clock as its control signal. A high clock selects the data in register Bo, and a low level of the clock selects the data in register Ao. This process doubles the data rate. Altera Corporation 3

4 Bidirectional Configuration Input and output registers are independent and enable the bidirectional DDR I/O path can be implemented entirely in the I/O element. The bidirectional configuration includes an input path, an output path, and two output enable registers. The bidirectional path consists of two data flow paths: input path active and output path active. When the input path is active, the output enable disables the tri-state buffer, which prevents data from being sent out on the output path. Disabling the tri-state buffer prevents contention at the I/O pin. The input path behaves like the input configuration as shown in Figure 1 on page 2. During output transactions, the output enable register Aoe controls the flow of data from the output registers. During outgoing transactions, the bidirectional configuration behaves like the output configuration as shown in Figure 2. The DDR I/O input registers can be bypassed in the bidirectional dataflow. For example, the output registers may be used while the input pin drives into the logic array, bypassing the input registers. The second output enable register (B OE ) is used for DDR SDRAM interfaces. This negative-edge register extends the high-impedance state of the pin by a half clock cycle. This feature is enabled by using the altddio_bidir megafunction in the Quartus II software. Figure 3 shows the bidirectional DDR I/O configuration for Stratix and Stratix GX devices. f For more information on DDR I/O megafunctions, see the DDR I/O Megafunctions on page 7. 4 Altera Corporation

5 Figure 3. Bidirectional DDR I/O Path Configuration oe D Q OE Reg AOE OR2 D Q OE Reg B OE (1) datain_l D Q Logic Array datain_h D Output Reg Ao Q 0 1 TRI I/O Pin outclock Output Reg Bo dataout_l Q D dataout_h Latch TCH LA Q D ENA Input Reg A I neg_reg_out Q D inclock Latch CI Input Reg B I Note to Figure 3: (1) Register B OE generates the delayed enable signal for DDR SDRAM applications. Altera Corporation 5

6 f DDR I/O Timing For more information about clock signals and output enable signals for Stratix or Stratix GX devices, see the Stratix Device Family Data Sheet or the Stratix GX FPGA Family Data Sheet. Figure 4 shows the functional timing waveform for the input path. The signal names are the port names used in the altddio_in megafunction. The signal data_in is the input from the pin to the DDR circuitry. neg_reg_out is the output of register B I. dataout_h is the output of latch C I and dataout_l is the output of register A I. dataout_h and dataout_l feed the core and illustrate the conversion of the data from a DDR implementation to positive-edge triggered data. Figure 4. DDR I/O Input Timing Waveform inclock data_in XX D0 E0 D1 E1 D2 E2 D3 neg_reg_out XX D0 D1 D2 D3 dataout_h XX D0 D1 D2 dataout_l XX E0 E1 E2 The functional timing waveform for the output path is shown in Figure 5. The output enable oe can be driven from a pin or internal logic. The oe signal feeds the output enable register (Aoe) and output enable register (B OE ). When oe is high, the output is tristated. The data signals datain_l and datain_h are driven from the logic array to output registers Ao and Bo. The signal data_out is the output from the DDR circuitry to the pin. Figure 5. DDR I/O Output Timing Waveform outclock oe mux control signal datain_l XX D0 D1 D2 D3 datain_h XX E0 E1 E2 E3 dataout XX E0 D0 E1 D1 ZZ 6 Altera Corporation

7 DDR I/O Megafunctions You can implement DDR I/O interfaces in the Quartus II software using the altddio_in, altddio_out, and altddio_bidir megafunctions. The megafunction altddio_in is used for the DDR I/O input path, altddio_out is used for the DDR I/O output path, and altddio_bidir is used for the DDR I/O bidirectional path. These megafunctions allow you to customize DDR I/O parameters. altddio_in The altddio_in megafunction configures the Stratix or Stratix GX IOE for DDR inputs. Tables 1, 2, and 3 show the port names and parameters for altddio_in. The options listed in these tables are valid for Stratix and Stratix GX devices. Other ports and parameters are available if you select a different device family. Table 1. altddio_in Input Ports Name Required Description Comments data_in[] Yes DDR input data port. Input port WIDTH wide. The data_in port should be directly fed from an input pin in the top level design. inclock Yes Clock signal to sample the DDR input. inclocken No Clock enable for the data clock. The data_in port is sampled on each clock edge of the inclock signal. aclr No Asynchronous clear input. The aclr port and the aset port cannot be connected at the same time. aset No Asynchronous preset input. The aclr port and the aset port cannot be connected at the same time. Table 2. altddio_in Output Ports Name Required Description dataout_h[] Yes Data sampled from the data_in[] port at the falling edge of the inclock signal. dataout_l[] Yes Data sampled from the data_in[] port at the rising edge of the inclock signal. Altera Corporation 7

8 Table 3. altddio_in Parameters Parameter Type Required Description WIDTH Integer Yes Width of the data_in, dataout_h, and dataout_l ports POWER_UP_HIGH String No When both the aset and aclr ports are unused, the POWER_UP_HIGH parameter can specify the powerup state of the output ports. Values are ON and OFF. The default setting is OFF. INTENDED_DEVICE_FAMILY String No This parameter is used for modeling and behavioral simulation. Create the altddio_in megafunction with the MegaWizard Plug-in Manager to calculate the value for this parameter. altddio_out The altddio_out megafunction configures the Stratix or Stratix GX IOE for DDR outputs. Tables 4, 5, and 6 show the port names and parameters for altddio_out. The options listed in these tables are valid for Stratix and Stratix GX devices. Other ports and parameters can be available if you select a different device family. Table 4. altddio_out Input Ports Name Required Description Comments datain_h[] Yes Input data, which is output on the Input port WIDTH wide. high level of the outclock port. datain_l[] Yes Input data, which is output on the low level of the outclock port. Input port WIDTH wide. outclock Yes Clock signal to register the data output. The dataout port outputs the DDR data on each level of the outclock signal. outclocken No Clock enable for the outclock port. aclr No Asynchronous clear input. The aclr port and the aset port cannot be connected at the same time. aset No Asynchronous set input. The aclr port and the aset port cannot be connected at the same time. oe No Output enable for the dataout port. Active-low signal. 8 Altera Corporation

9 Table 5. altddio_out Output Ports Name Required Description Comments dataout[] Yes DDR output data port. Output port WIDTH wide. The dataout port should directly feed an output pin in the top-level design. Table 6. altddio_out Parameters Parameter Type Required Comments WIDTH Integer Yes This parameter sets the width of the datain_h, datain_l, and dataout ports. POWER_UP_HIGH String No If both the aset and aclr ports are unused, the POWER_UP_HIGH parameter is available to specify the power-up state of the output ports. Values are ON and OFF. The default setting is OFF. INTENDED_DEVICE_FAMILY String No This parameter is used for modeling and behavioral simulation. Create the altddio_out megafunction with the MegaWizard Plug-in Manager to calculate the value for this parameter. OE_REG String No This specifies whether the oe port is registered. Values are REGISTERED, UNREGISTERED, and UNUSED. The default setting is UNUSED. EXTEND_OE_DISABLE String No This specifies whether the second oe register should be used. When the second oe register is used, the output pin is held at high impedance for an extra half clock cycle after the oe port goes high. Values are ON, OFF, and UNUSED. The default setting is UNUSED. This option is used to implement DDR memory interfaces. altddio_bidir The altddio_bidir megafunction configures the Stratix or Stratix GX IOE for bidirectional DDR inputs and outputs. Tables 7, 8, and 9 show the port names and parameters for altddio_bidir. The options listed in these tables are valid when targeting Stratix and Stratix GX devices. Other ports and parameters are available if you select a different device family. Altera Corporation 9

10 Table 7. altddio_bidir Input Ports Name Required Description Comments datain_h[] Yes Input data to be output to the padio port at the falling edge of the outclock port. Input port WIDTH wide. datain_l[] Yes Input data to be output to the padio port at the rising edge of the outclock port. inclock Yes Clock signal to sample the DDR input. inclocken No Clock enable for the inclock port. outclock Yes Clock signal to register the data output. outclocken No Clock enable for the outclock port. Input port WIDTH wide. The padio port is sampled on each clock edge of the inclock signal. The padio port outputs the DDR data on each level of the outclock signal. aclr No Asynchronous clear input. The aclr port and the aset port cannot be connected at the same time. aset No Asynchronous set input. The aclr port and the aset port cannot be connected at the same time. oe No Output enable for the bidirectional padio port. If oe is not selected, then the padio port is an output port. This signal is active low. Table 8. altddio_bidir Output Ports Name Required Description Comments dataout_h[] Yes Data sampled from the padio port at the falling edge of the inclock signal. dataout_l[] Yes Data sampled from the padio port at the rising edge of the inclock signal. combout No Combinatorial data from the padio port to the logic array. padio Yes Bidirectional DDR port that should directly feed a bidirectional pin in the top-level design. The DDR data is transmitted and received on this bidirectional port. 10 Altera Corporation

11 Table 9. altddio_bidir Parameters Name Type Required Comments WIDTH Integer Yes Width of the datain_h, datain_l, dataout_h, dataout_l, and padio ports. POWER_UP_HIGH String No When both the aset and aclr ports are unused, the POWER_UP_HIGH parameter is available to specify the power-up state of the output ports. Values are ON, and OFF. The default setting is OFF. INTENDED_DEVICE_FAMILY String No This parameter is used for modeling and behavioral simulation purposes. Create the altddio_bidir megafunction with the MegaWizard Plug-in Manager to calculate the value for this parameter. OE_REG String No Specifies whether the oe port is registered. Values are REGISTERED, UNREGISTERED, and UNUSED. The default setting is UNUSED. IMPLEMENT_INPUT_IN_LCELL String No Specifies whether the input channels should be implemented using logic cells. Values are ON, OFF, and UNUSED. The default setting is UNUSED. EXTEND_OE_DISABLE String No Specifies whether the second oe register should be used. When the second oe register is used, the output pin is held at high impedance for an extra half clock cycle after the oe port goes high. Values are ON, OFF, and UNUSED. The default setting is UNUSED. This option is used to implement DDR memory interfaces. Using DDR I/O Megafunctions This section describes how to implement DDR I/O megafunctions in a design. Figure 6 shows a simple implementation of the altddio_in and altddio_out megafunctions. Verilog HDL & VHDL DDR I/O Megafunctions Examples Altera provides design files (in Verilog HDL and VHDL) for the sample designs described in this section. You can download the design files from the Altera website at for The files provided with this application note implement the designs shown in Figure 6 and Figure 8 in both Verilog HDL and VHDL. These files show how to instantiate the DDR I/O megafunctions in Verilog HDL and VHDL. Altera Corporation 11

12 Figure 6. Sample Design using the altddio_in & altddio_out Megafunctions DDRIN8_IN[7..0] CLK INPUT VCC INPUT VCC clk ddrin8 datain[7..0] dataout_h[7..0] DDIO inclock Input dataout_i[7..0] Power up Low inst1 DDRIN8_OUT_H[7..0] DDRIN8_OUT_L[7..0] clk numer[7..0] divide8 quotient[7..0] denom[7..0] remain[7..0] Numer is UNSIGNED Denom is UNSIGNED Pipeline length of 3 quotient[7..0] remain[7..0] DDRIN8_OUT_H[7..0] DDRIN8_OUT_L[7..0] quotient[7..0] remain[7..0] datain_h[7..0] datain_i[7..0] ddrout8 DDIO Input dataout[7..0] DDROUT8_OUT[7..0] outclock Power up Low quotient[7..0] remain[7..0] REG_DDROUT8_IN_H[7..0] REG_DDROUT8_IN_L[7..0] In this design, data is received at double the clock rate through pins DDRIN8_IN[7..0] of the DDRIN8 megafunction. The input data is fed to a simple divide circuit. The DDRIN8_OUT_H[7..0] signals are the numerator and the DDRIN8_OUT_L[7..0] signals are the denominator. The equation below describes the function of the sample design in Figure 6. DDRIN8_OUT_H[7..0]/DDRIN8_OUT_L[7..0] = quotient[7..0] R remain[7..0] These sets of signals are passed into the library of parameterized modules (LPM) function divide8 where the quotient and remainder are calculated. The divider calculates the quotient and remainder through a three-stage pipeline. The quotient and remainder are then fed via signals quotient[7..0] and remain[7..0] into the DDRIN8 megafunction. The DDRIN8 megafunction then drives the data out through pins DDROUT8_OUT[7..0] at double the data rate. Figure 7 shows the functional waveform for the sample design. 12 Altera Corporation

13 Figure 7. Timing Results for Sample Design Using altddio_in & altddio_out 1. The numerator (100) and denominator (5) are captured at 200 Mbps through pin DDRIN8_IN. 2. On the rising edge of clk at 7.5 ns, the numerator (100) drives onto the signal DDRIN8_OUT_H and the denominator (5) drives onto the signal DDRIN8_OUT_L. 3. At 27.5 ns, the quotient (20) and the remainder (0) are calculated and driven onto signals REG_DDROUT8_IN_H and REG_DDROUT8_IN_L. 4. The high level of clk, starting at 37.5 ns, selects the quotient (20) to drive the DDROUT8_OUT pin, and the low level of clk selects the remainder (0) to drive the same pin. 5. The waveform contains calculations for two more sets of numbers. The latency (7.5 ns to 37.5 ns) exists because of a three-stage pipeline in the divider. Figure 8 shows a simple implementation of the ddr_bidir8 megafunction. Altera Corporation 13

14 Figure 8. Sample Design Using the altddio_bidir Megafunction clk INPUT VCC DDRBIDIR8_OUT_H[7..0] DDRBIDIR8_OUT_L[7..0] clk inst numer[7..0] divide8 quotient[7..0] denom[7..0] remain[7..0] Numer is UNSIGNED Denom is UNSIGNED Pipeline length of 3 quotient[7..0] remain[7..0] oe datain_h[7..0] datain_i[7..0] oe inclock outclock inst1 ddr_bidir8 ddio bidir Power up Low dataout_h[7..0] DDRBIDIR8_OUT_H[7..0] dataout_i[7..0] DDRBIDIR8_OUT_L[7..0] padio[7..0] BIDIR DDR_BIDIR8[7..0] VCC oe INPUT VCC oe DDRBIDIR8_OUT_H[7..0] DDRBIDIR8_OUT_L[7..0] DDRBIDIR8_OUT_H[7..0] DDRBIDIR8_OUT_L[7..0] quotient[7..0] REG_DDRBIDIR8_IN_H[7..0] remain[7..0] REG_DDRBIDIR8_IN_L[7..0] This design implements the same divider example as shown in Figure 8, but instead the functionality of altddio_in and altddio_out are implemented in a single megafunction altddio_bidir. The bidirectional pins DDR_BIDIR8[7..0] receive data at double the clock rate. The DDRBIDIR8_OUT_H[7..0] signals are the numerator and the DDRBIDIR8_OUT_L[7..0] signals are the denominator. These two sets of signals are passed into divide8 where the quotient and remainder are calculated. The divider calculates the quotient and remainder through a three-stage pipeline. The quotient and remainder are then fed via signals quotient[7..0] and remain[7..0] back into the altddio_bidir megafunction. The altddio_bidir megafunction then drives the data out through pins DDR_BIDIR8[7..0] at double the data rate. Figure 9 shows the functional waveform for the sample design. Figure 9. Timing Results for a Sample Design Using the altddio_bidir Megafunction 14 Altera Corporation

15 In Figure 9, three sets of numerators and denominators are brought in through the bidirectional pin DDR_BIDIR8. After three sets of data are brought in, the oe signal enables the answers to be driven out on the same bidirectional pin DDR_BIDIR8. The flow of the first set of data is as follows: 1. The numerator (100) and denominator (5) are captured at 200 Mbps through pin DDRBIDIR8. 2. On the rising edge of clk at 7.5 ns, the numerator (100) drives onto the signal DDRBIDIR8_OUT_H and the denominator (5) drives onto the signal DDRIN8_OUT_L. 3. At 27.5 ns, the quotient (20) and the remainder (0) are calculated and driven to signals REG_DDRBIDIR8_IN_H and REG_DDRBIDIR8_IN_L. 4. At 30 ns, the oe signal goes low, allowing the calculated quotient and remainder to be driven out on the bidirectional pin. 5. The high level of clk starting at 37.5 ns, selects the quotient (20) to drive out the DDROUT8_OUT pin and the low level of clk selects the remainder (0) to drive out on the same pin. Two more sets of numbers show the flow of the design. To allow the data to be driven out of the bidirectional pin in the simulation, make sure the input signal part of the bidirectional pin is set to a weak unknown, which allows the simulation to overwrite the value at the specific time interval. The Quartus II software creates an additional signal to emulate the output part of the bidirectional pin. This signal is named <pin name>~result. A three-stage pipeline causes latency (7.5 ns to 37.5 ns) in the divider. DDR I/O Applications This section provides information on the following DDR I/O applications: DDR RAM QDR SRAM High-speed interface applications Altera Corporation 15

16 DDR RAM DDR RAM can write and read data at twice the clock rate by capturing data on both the positive and negative edge of a clock. DDR RAM interfaces include DDR SRAM, DDR SDRAM, and FCRAM. DDR SRAM and DDR SDRAM are JEDEC standards and the FCRAM standard is being developed by Fujitsu and Toshiba. FCRAM uses a proprietary pipeline method and precharge to help reduce random access cycle times. These DDR memory interfaces use SSTL-II or LVCMOS as the standard for transferring data. f See the DDR SDRAM Controller White Paper for more information. QDR SRAM The QDR SRAM standard is defined jointly by Cypress, IDT and Micron. QDR SRAMs have separate DDR read and write ports that can pass data concurrently. The combination of concurrent transactions and DDR signaling allow for data to be passed four times faster than conventional SRAMs. The I/O standards used for QDR SRAMs are HSTL class I and II. f For more information on QDR SRAM, see AN 211: QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices. High-Speed Interface Applications High-speed interface applications can use various differential standards such as LVDS, LVPECL, PCML, or Hypertransport as the transfer medium. These standards often use DDR data. Stratix and Stratix GX devices can implement high-speed standards either by using the dedicated differential I/O SERDES blocks or by bypassing SERDES and using the DDR I/O circuitry SERDES bypass mode. DDR I/O megafunctions, PLLs, and shift registers are all used in SERDES functionality. f For more information about the differential I/O capabilities and SERDES bypass, see AN 201: Using Selectable I/O Standards in Stratix Devices and AN 202: Using High Speed Differential I/O Interfaces in Stratix Devices. 16 Altera Corporation

17 Implementing Megafunctions The Quartus II software allows you to easily and quickly instantiate megafunctions using the MegaWizard Plug-In Manager. To implement a megafunction, follow the below steps: 1. Launch the MegaWizard Plug-In Manager by choosing MegaWizard Plug-In Manager (Tools menu) in the Quartus II software. 2. Select Create a new custom megafunction variation and click Next. See Figure 10. Figure 10. Create a New Megafunction Variation 3. Click the + icon next to I/O to expand the I/O megafunction list. 4. Choose a DDR I/O megafunction under I/O. See Figure 11. Altera Corporation 17

18 Figure 11. Select a DDR I/O Megafunction 5. Select an output file type and enter the desired name of the megafunction. You can choose AHDL (.tdf), VHDL (.vhd), or Verilog HDL (.v) as the output file type. Along with these HDL files, the MegaWizard plug-in manager creates an include file (.inc), a VHDL Component Declaration File (.cmp) and a Block Symbol File (.bsf). The following sections describe the options that are available for the DDR I/O megafunction. altddio_in Configuration The altddio_in wizard provides customizable parameters for device family, data bus width, type of reset, and the clock enable option. Figure 12 shows the wizard. 18 Altera Corporation

19 Figure 12. altddio_in Megafunction All Stratix and Stratix GX IOEs have the six registers that are required to implement DDR I/O. Only the number of I/O pins available per Stratix or Stratix GX device limits the data bus width. Stratix and Stratix GX devices support the asynchronous clear (aclr) and asynchronous preset (aset) asynchronous resets. The asynchronous resets are exclusive and cannot be used together. If an asynchronous reset is not implemented, you must specify the state of the registers (high or low) when powering up. You can add a clock enable port can be added to control when data is clocked in. This signal prevents data from being passed through. f For more information regarding the ports for this megafunction see altddio_in on page 7. altddio_out Configuration The altddio_out wizard provides customizable parameters for device family, data bus width, and type of reset. Other available options include a clock enable port, an output enable port with the option to register the port, and extending the tri-state output for a half clock cycle. Figure 13 shows the wizard. Altera Corporation 19

20 Figure 13. altddio_out Megafunction You can add an output enable port to the megafunction. This port prevents data from driving out of the device. The option to register the output enable port uses register Aoe described in the DDR I/O Architecture section. The Delay switch-on by a half clock cycle option is used to interface with DDR memory. This option uses the B OE register. All I/O elements in Stratix and Stratix GX devices have the six registers needed to implement DDR I/O. Only the number of I/O pins available per Stratix or Stratix GX device limits the data bus width. Stratix and Stratix GX devices support the asynchronous clear (aclr) and asynchronous preset (aset) asynchronous resets. The asynchronous resets are exclusive and cannot be used together. If an asynchronous reset is not implemented, you must specify the state of the registers (high or low) when powering up. You can add a clock enable port to control when data is clocked in. This signal prevents data from being passed through. 20 Altera Corporation

21 altddio_bidir Configuration The altddio_bidir megafunction combines altddio_in and altddio_out into a single megafunction, which instantiates bidirectional DDR ports. Figure 14 shows the altddio_bidir wizard. Figure 14. altddio_bidir Megafunction Configuration Panel The options for altddio_bidir are the same as altddio_out with include the following additions: An option for an unregistered data port, comb_out, is included. The comb_out port sends data to the core bypassing the DDR I/O input registers. The input path of the altddio_bidir megafunction can be implemented in logic elements. For more information about the altddio_bidir megafunction, see altddio_bidir on page 9. Altera Corporation 21

22 Conclusion Revision History Modern systems require faster interfaces to memory and other high-speed applications. With faster system and I/O speeds, interfaces have become a bottleneck. DDR I/O architecture helps increase the speed of these interfaces by allowing them to communicate with system logic at a higher data rate. The DDR I/O circuitry in Stratix and Stratix GX devices enables a robust, push-button solution to enhance system performance. The information contained in AN 212: Inplementing Double Data Rate I/O Signaling in Stratix & Stratix GX Devices version 2.0 supersedes information published in previous versions. The following change was made in AN 212: Inplementing Double Data Rate I/O Signaling in Stratix & Stratix GX Devices version 2.0: added Stratix GX devices throughout the document. 101 Innovation Drive San Jose, CA (408) Applications Hotline: (800) 800-EPLD Literature Services: lit_req@altera.com Copyright 2002 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. 22 Altera Corporation