Designing with ESBs in APEX II Devices

Transcription

1 Designing with ESBs in APEX II Devices March 2002, ver. 1.0 Application Note 179 Introduction In APEX TM II devices, enhanced embedded system blocks (ESBs) support memory structures, such as single-port and dual-port RAM. Additionally, in APEX II devices, ESBs support bidirectional dual-port RAM. In this mode, each ESB has two ports that allow two different read or write operations simultaneously. In APEX II devices, the ESB can be split into two separate single-port 2K RAM blocks. This application note explains the basic operation of the APEX II ESB, how to implement different memory configurations in ESBs, some applications using ESBs, and the initialization file in the Altera Quartus II software. This application note also includes a timing diagram for each memory configuration type. ESB Memory Configurations & Features This application note discusses the following ESB memory configurations: single-port RAM dual-port RAM dual-port+ RAM (bidirectional dual-port RAM) ROM FIFO Single-Port RAM Configuration The single-port RAM configuration is shown in Figure 1 and has the following features: Uses one port that supports either one read or one write. Read during write always uses the same address for reading and writing. The ESB only uses the write clock. As a result, the output depends on the ESB synchronous write cycle time, which is slower than the read cycle time. Therefore, the read cycle runs at a slower frequency as compared to the dual-port RAM configuration. Data bus widths definable as 1, 2, 4, 8, or 16 bits for input and output buses. Registered inputs and outputs each have clock, clock enable, and clear ports. Altera Corporation 1 A-AN

2 Figure 1. Single-Port Memory Configuration in an ESB Partitioning the ESB into two separate 2K-bit single-port RAM blocks increases the total number of memory blocks per device. Each 2K RAM block has its own read and write port, but the maximum data-width is 8-bits. The 2K RAM configurations are 256 8, 512 4, and See Figure 2. The 2K RAM divisions must have the same configuration. Figure 2. Single-Port Partitioned RAM in an ESB Dual-Port RAM Configuration The dual-port RAM configuration is shown in Figure 3 and has the following features: The ESB can simultaneously read and write data. The ESB supports variable-width data ports for reading and writing to the RAM. For example, the ESB can be written in 1-bit mode at port A while being read in 16-bit mode from port B. Table 1 lists the supported variable width configurations for an ESB in dual-port mode. The read and write address ports have independent clock, clock enable, and clear ports. Uses both the read and write clock. When performing synchronous read and writes, the read cycle time is faster than the write cycle time. The output depends on the read cycle time, so the performance is higher than for the single-port RAM configuration, which depends on the write cycle time. 2 Altera Corporation

3 Figure 3. Dual-Port RAM Memory Configuration in an ESB Table 1. Variable Width Configuration for Dual-Port RAM Read Port Width Write Port Width 1 bit 2 bits, 4 bits, 8 bits, or 16 bits 2 bits, 4 bits, 8 bits, or 16 bits 1 bit Bidirectional Dual-Port RAM Configuration The bidirectional dual-port RAM configuration is shown in Figure 4 and has the following features: Two independent ports, port A and port B Can simultaneously perform two reads, two writes, or one read and one write Data bus width definable as 1, 2, 4, or 8 bits Independent clock, clock enable, and clear set signals for port A and port B Figure 4. Bidirectional Dual-Port RAM Configuration in an ESB Altera Corporation 3

4 FIFO Buffer Configuration The FIFO buffer configuration is shown in Figures 5 and 6 and has the following features: Data transferred between design subsystems uses FIFO memory buffers. For instance, FIFO buffers hold data that is driven from multiple sources to a shared bus. When the bus is busy, the FIFO buffer stores the data; when the bus is not busy, the FIFO buffer sends the data to the bus. An ESB can implement a single- or dual-clock FIFO to buffer data between systems communicating at the same or different clock frequencies. Figure 5. Single Clock FIFO Figure 6. Dual Clock FIFO 4 Altera Corporation

5 ROM Configuration The ROM configuration is shown in Figure 7 and has the following features: The memory contents are written during configuration before the device enters user mode. Allows registered or bypassed outputs. The read operation is identical to the single-port RAM. Figure 7. ROM Memory Configuration in an ESB Altera Corporation 5

6 ESB Read/Write Combinations An ESB has two separate ports: A and B. Different modes use different combination for these two ports. Table 2 shows read/write and width/depth for different memory modes in the ESB. These events occur within one clock cycle. Table 2. Read/Write & Width/Depth Combinations in an APEX II ESB Mode Port A Port B Size Bidirectional Dual-port RAM (1) read read read write write write read write Dual-port RAM (1) write read read write Single-port RAM read/write Single-port RAM (packed mode) (2) write/read read/write ROM read FIFO read write Note to Table 2: (1) Supports mismatch in input/output data widths. (2) Packed mode is when the ESB is split into two 2K single-port memory blocks. 6 Altera Corporation

7 Using the MegaWizard to Implement Memory Configurations This section describes how to use the MegaWizard in the Quartus II software to implement memory configurations through megafunctions: LPM_RAM_DQ LPM_RAM_DP LPM_RAM_DP+ LPM_FIFO LPM_ROM Selecting a Megafunction to Customize Select and customize a megafunction in a design using the MegaWizard Plug-In Manager. The following are the steps to select an instance of a megafunction using the Quartus II software: 1. Select MegaWizard Plug-In Manager (Tools menu). 2. Turn on the Create a new custom megafunction variation option. See Figure Click Next. Figure 8. MegaWizard Plug-In Manager [page 1] Altera Corporation 7

8 4. Choose a megafunction from the storage folder in the Available Megafunction list. See Figure 9. Figure 9. MegaWizard Plug-In Manager [page 2a] 5. Turn on the type of output file to create: AHDL, VHDL, or Verilog. 6. Type in a file name for the function. 7. Click Next. 8 Altera Corporation

9 LPM_RAM_DQ Megafunction The LPM_RAM_DQ is a single-port RAM function as shown in Figure 10 and has the following features: Implements either synchronous or asynchronous single-port RAM inclock can register ESB data and/or address inputs A separate outclock can register output data LE-based or ESB-based Synchronous write operations into the memory block use the address[] and data[] ports, triggered by the rising edge of inclock while the write enable (we) port is enabled. The outclock port for the read operation is optional. For asynchronous operations, setup and hold times have to be valid with respect to both edges of the write enable signal (we). The data and address lines should not change while we is active. Figure 10. Single-Port RAM Block Diagram Instantiating the LPM_RAM_DQ Megafunction in a Design Use the following steps to create an instance of the lpm_ram_dq function: 1. Follow the instructions in the Selecting a Megafunction to Customize section, choosing lpm_ram_dq from the storage folder in the Available Megafunction list. 2. Choose the data output and address bus widths using the How wide should the q output bus be? and How wide should the address input bus be? lists. See Figure 11. Any change made is automatically reflected in the symbol graphic. Altera Corporation 9

10 3. Turn on the options for the ports to register in the Which ports should be registered? section. If registered, inclock clocks the data and address ports; while outclock clocks the output port. See Figure 11. Figure 11. MegaWizard Plug-In Manager - LPM_RAM_DQ [page 3 of 5] 4. Turn on the Yes, use this file for the memory content data option to initialize the memory block with a hexadecimal (Intel-format) file (.hex) or a memory initialization file (.mif) file. See Figure 12. or Turn on the No, leave it blank option to initialize the memory block to all zero. See Figure Altera Corporation

11 Figure 12. MegaWizard Plug-In Manager - LPM_RAM_DQ [page 4 of 5] 5. Click Finish to complete the procedure. See Figure 13. Figure 13. MegaWizard Plug-In Manager - LPM_RAM_DQ [page 5 of 5] - Summary Altera Corporation 11

12 LPM_RAM_DP Megafunction The LPM_RAM_DP is a dual-port RAM function as shown in Figure 14 and has the following features: Fully parameterized function Allows simultaneous read and write access to memory cells Can register any combination of EAB/ESB inputs LE-based or EAB/ESB-based Four clocking modes Single clock Shared clock Separate clock Asynchronous Clocking Modes The lpm_ram_dp has four modes: single clock, shared clock, separate clock, and asynchronous. Use the clocking method section of the MegaWizard Plug-in Manager interface to select the different modes. Single Clock In single clock mode, the read and write operations are synchronous to the same clock. Shared Clock In shared clock mode, in addition to having the read and write operations synchronous to the same clock, a separate clock is used for the output port, q[]. This is also referred to as having separate input and output clocks. Separate Clock In separate clock mode, there are two independent clocks, rdclock and wrclock, for the read and write operations, respectively (See Figure 14). Asynchronous The asynchronous mode requires no clock. The write operation is dependent on the wren signal. The read operation is dependent on the rden signal. If not present, the rden is V CC by default. 12 Altera Corporation

13 Figure 14. Dual-Port RAM Block Diagram Instantiating the LPM_RAM_DP Megafunction in a Design Use the following steps to create an instance of the lpm_ram_dp function: 1. Follow the instructions in the Selecting a Megafunction to Customize section, choosing lpm_ram_dp from the storage folder in the Available Megafunction list. See Figure Choose the data output and address bus widths using the How wide should the q output bus be? and How wide should the address input bus be? lists. Any change made is automatically reflected in the symbol graphic. 3. Turn on a clocking method in the Which clocking method do you want to use? section. 4. Optionally, turn on the Create a rden read enable signal option. The rden signal is tied to V CC (active), if no signal is created. See Figure 15. Altera Corporation 13

14 Figure 15. MegaWizard Plug-In Manager - Dual-Port RAM [page 3 of 6] 5. Turn on the options for Which ports should be registered?. Click More Options, to register the ports individually. See Figure 16 on page Optionally, turn on Create one clock enable signal for each clock signal. If using dual clocks, there may be two separate clock enable signals. 1 The Create an aclr asynchronous clear for the registered ports is option is unavailable. In order to enable this option use the altdpram function. 7. Click Next. 14 Altera Corporation

15 Figure 16. MegaWizard Plug-In Manager - Dual-Port RAM [page 4 of 6] 8. Turn on the Yes, use this file for the memory content data option to initialize the memory block with a hexadecimal (Intel-format) file (.hex) or a memory initialization file (.mif) file. See Figure 17. or Turn on the No, leave it blank option to initialize the memory block to all zero. 9. Click Next to see a summary of the files that MegaWizard creates. or Click Finish to complete the process. Altera Corporation 15

16 Figure 17. MegaWizard Plug-In Manager - Dual-Port RAM [page 5of 6] LPM_RAM_DP+ (Bidirectional Dual-Port RAM) Megafunction The LPM_RAM_DP+ is the bidirectional dual-port RAM function and has the following features: Fully parameterized function Capable of simultaneous read and write access to memory cells Capable of registering any combination of ESB inputs LE-based or ESB-based Three clocking modes Single clock Separate clock Asynchronous Clocking Modes Use the clocking method section of the MegaWizard Plug-in Manager interface to select one of the three LPM_RAM_DP+ clocking modes. The three clock modes are as follows: Single Clock In the single clock mode, the read and write operations are synchronous to the same clock. 16 Altera Corporation

17 Separate Clock In the separate clock mode, there are two independent clocks, clock_a and clock_b for port A and port B, respectively. Asynchronous The asynchronous mode requires no clock. The write operation is dependent on the wren signal, but the read operation is independent of wren and can be continuous regardless of the write operation. Instantiating a Bidirectional Dual Port RAM in a Design Use the following steps to create an instance of the lpm_ram_dp+ function: 1. Follow the instructions in the Selecting a Megafunction to Customize section, choosing lpm_ram_dp+ from the storage folder in the Available Megafunction list. 2. Select APEX II for the device family from the Create RAM for which device family? list. 3. Turn on the With two read/write ports option in the How will you be using the dual port ram? section. This option is for the bidirectional dual port RAM configuration. 4. Turn on either the memory size option for As a number of words or As a number of bits in the How do you want to specify the memory size? section. See Figure Click Next. Altera Corporation 17

18 Figure 18. MegaWizard Plug-In Manager - Dual-Port [page 1 of 7] 6. Select How many words of memory?. See Figure Select the width for the output port A from the Read/Write Ports section. 8. Click Next. 18 Altera Corporation

19 Figure 19. MegaWizard Plug-In Manager - Dual-Port RAM [page 2 of 7] 9. Turn on the Single clock option as the clocking method in the Which clocking method do you want to use? section. If using asynchronous mode, turn on No Clock. See Figure Click Next. Altera Corporation 19

20 Figure 20. MegaWizard Plug-In Manager - Dual-Port Ram [page 3 of 7] 11. Check Write input ports and Read output ports to be registered. See Figure Click More Options. 13. Turn on all of the required options in the RAM Port Registers dialog box. 20 Altera Corporation

21 Figure 21. MegaWizard Plug-In Manager - Dual-Port RAM [page 5 of 7] 14. Turn on the Yes, use this file for the memory content data option to initialize the memory block with a hexadecimal (Intel-format) file (.hex) or a memory initialization file (.mif) file. See Figure 22. or Turn on the No, leave it blank option to initialize the memory block to all zeros. 15. Click Next to see a summary of the files that MegaWizard creates. or Click Finish to complete the process. Altera Corporation 21

22 Figure 22. MegaWizard Plug-In Manager - Dual-port RAM [page 6 of 7] LPM_FIFO+ Megafunction The LPM_FIFO+ is a single- or dual-clock FIFO megafunction with the following features: Fully parameterized function Single- or dual-clock modes Simultaneous reads and writes Full, empty, and used words output signals Fully optimized for Altera architecture LE-based or EAB/ESB-based The lpm_fifo+ function is a parameterized, single or dual clock FIFO megafunction that can be used to buffer data between systems communicating at the same or different clock frequencies. The lpm_fifo+ function is actually two functions in one a single clock FIFO (lpm_fifo) and a dual clock FIFO (lpm_fifo_dc). Select which FIFO megafunction to create in the MegaWizard PlugIn Manager interface. 22 Altera Corporation

23 Single Clock Mode In single clock mode, the lpm_fifo+ megafunction instantiates the scfifo megafunction for single clock FIFO functions. The megafunction has a single clock port for writing and reading data to and from the FIFO. Simultaneous reads and writes can be done in the same clock cycle. The parameterization of the lpm_fifo+ megafunction can implement any width/depth combination. The function also has customizable output signals, such as empty/full flags and number of used words outputs. It also gives the choice of an asynchronous or a synchronous clear signal. Either ESBs or LEs can implement the megafunction. However, implementing a large FIFO in LEs can dramatically increase overall LE use. Dual Clock Mode In dual clock mode, the lpm_fifo+ megafunction instantiates the dcfifo megafunction for dual-clock FIFO functions. The megafunction has two independent clock ports used for writing and reading data to and from the FIFO buffer. Simultaneous reads and writes can be done in the same clock cycle. The parameterization of the lpm_fifo+ megafunction can implement any width/depth combination. The function also has customizable output signals, such as empty/full flags and number of used words outputs, that can be synchronized to either the read or write clock. 1 The last three words of the dcfifo may not be available for writing because of the synchronization pipelines between the two clock domains. These pipelines are intended to avoid internal metastability. Because of these pipelines, information available to one clock domain regarding when read and write conditions occur may be temporarily unavailable to the other clock. The wrfull and rdfull ports of an lpm_fifo+ megafunction must go high slightly before the dcfifo is completely full, in order to avoid overshooting the top of the FIFO. This process may cause several words at the end of the FIFO to become unavailable. Depending on the write rate to the FIFO, the wrfull and rdfull ports may go high with three words remaining, with two words remaining, or with one word remaining in the FIFO. However, this process is necessary both to accommodate the clock synchronization and to ensure overflow does not take place. To maintain a specific number of words, specify a number for the LPM_NUMWORDS parameter that is up to three words greater than the amount needed. Altera Corporation 23

24 The synchronization and internal logic in dcfifo may delay the information in the wrempty, wrfull, wrusedw[], rdempty, rdfull, and rdusedw[] ports by one clock cycle of latency. Setup and hold violations on synchronization registers during timing analysis can occur if the rdclock and wrclock signals are unrelated. This is normal behavior for multi-clock designs. Figure 23. FIFO in an ESB Common to Both Dual & Single Clock Modes The read-request port of the lpm_fifo+ megafunction has two configuration modes: legacy synchronous FIFO and show-ahead synchronous FIFO. These modes configure the read-request port to act as either a read request or a read acknowledge. In the default read request (legacy) mode, requested data comes out of the FIFO on the first clock cycle after the read request is asserted. In the read acknowledge (show-ahead) mode, the first piece of data written into the FIFO immediately shows up on its output and reads from the FIFO are acknowledged instead of requested (See Figure 23). 24 Altera Corporation

25 Instantiating the LPM_FIFO+ Megafunction in a Design This section list the steps needed to create an instance of the lpm_fifo+ megafunction in single-clock and in dual-clock mode. Single-Clock FIFO Use the following steps to create an instance of the lpm_fifo+ megafunction in single-clock mode: 1. Follow the instructions in the Selecting a Megafunction to Customize section, choosing lpm_fifo+ from the storage folder in the Available Megafunction list. 2. Select the number of bits for How wide should the FIFO be? and the number of words for How deep should the FIFO be?. See Figure Turn on the Yes, synchronize both reading and writing to clock option. 4. Click Next. Figure 24. MegaWizard Plug-In Manager - LPM_FIFO [page 3 of 8] 5. Turn on the desired options in the Which optional output control signals do you want? section. See Figure Click Next. Altera Corporation 25

26 Figure 25. MegaWizard Plug-In Manager - LPM_FIFO [page 4 of 8] 7. Turn on which rdreq signal mode (legacy synchronous or showahead synchronous) to use in the Which kind of read access do you want with the rdreq signal? section. See Figure Click Next. Figure 26. MegaWizard Plug-In Manager - LPM_FIFO [page 6 of 8] 26 Altera Corporation

27 9. Turn on the Quartus II software optimization (default, speed, or area) to use with the megafunction in the Which type of optimization do you want? section. 10. Optionally, turn on Disable overflow checking and/or Disable underflow checking to disable circuitry protection. 11. Optionally, turn on the Implement FIFO function with logic cells only, even if the device contains EABs or ESBs compiler option. The default is to place the FIFO in ESBs. See Figure Click Next to see a summary of the files that MegaWizard creates. or Click Finish to complete the process. Figure 27. MegaWizard Plug-In Manager - LPM_FIFO [page 7of 8] Dual-Clock FIFO Use the following steps to create an instance of the lpm_fifo megafunction in dual-clock mode: 1. Follow the instructions in the Selecting a Megafunction to Customize section, choosing lpm_fifo from the storage folder in the Available Megafunction list. Altera Corporation 27

28 2. Select the number of bits for How wide should the FIFO be? and the number of words for How deep should the FIFO be?. 3. Turn on No, synchronize reading and writing to rdclock and wrclock, respectively. See Figure Turn on the Yes option to add latency or the No option to not add latency in the Do you want the FIFO to pipeline its output flags? section. 5. Click Next. Figure 28. MegaWizard Plug-In Manager - LPM_FIFO [page 3 of 8] 6. Turn on the required read-side and write-side Which optional output control signals do you want? options. Each of the full, empty or usedw[] signals can be synchronized to either the read or write clock. See Figure If required, turn on the Asynchronous clear. See Figure Click Next. 28 Altera Corporation

29 Figure 29. MegaWizard Plug-In Manager - LPM_FIFO [page 5 of 8] 9. Turn on which rdreq signal mode (legacy synchronous or showahead synchronous) to use in the Which kind of read access do you want with the rdreq signal? section. See Figure Click Next. Figure 30. MegaWizard Plug-In Manager - LPM_FIFO [page 6 of 8] Altera Corporation 29

30 11. Turn on the desired optimization type in the Which type of optimization do you want? section. 12. Optionally, turn on whether you want to disable overflow or underflow checking in the Would you like to disable any circuitry protection? section. 13. Optionally, turn on the Implement FIFO function with logic cells only, even if the device contains EABs or ESBs compiler option. The default is to place the FIFO in ESBs. See Figure 31. Figure 31. MegaWizard Plug-In Manager - LPM_FIFO [page 7of 8] 14. Click Next to see a summary of the files that MegaWizard creates. or Click Finish to complete the process. 30 Altera Corporation

31 LPM_ROM Megafunction The LPM_ROM is a ROM function that has the following features: Fully parameterized function Supports synchronous and asynchronous memory modes Allows control of the address input and ROM output with separate clocks Fully optimized for Altera architecture The parameterized lpm_rom function can implement all ROM functions. The ESB implement these functions in APEX II devices. The lpm_rom megafunction supports both synchronous and asynchronous modes of operation. The address[] input port and/or the q[] output port can be registered and are controlled by the inclock and outclock, inputs respectively. Totally asynchronous memory operations occur when both the inclock and outclock ports are unused. Further, the lpm_rom megafunction provides the optional use of a memory enable signal the memenab port. When the memory is not enabled (memenab is low), the q[] output is high-impedance (See Figure 32). 1 lpm_rom must have a memory initialization file (.mif) or hexadecimal (.hex) file with the same name in the project directory that contains the data written to ROM during configuration. For more information on creating these files see Initialization Files on page 55. Figure 32. ROM Block Diagram Altera Corporation 31

32 Instantiating the LPM_ROM Megafunction in a Design Use the following steps to create an instance of the lpm_rom megafunction in single-clock mode: 1. Follow the instructions in the Selecting a Megafunction to Customize section, choosing lpm_rom from the storage folder in the Available Megafunction list. 2. Specify the size of the ROM by selecting the number of bits in the How wide should the q output bus be? section and the number of bits in the How wide should the address input bus be? section. 3. For synchronous ROM implementation, in the Which ports should be registered? section, turn on the address input port option and/or the q output port option. See Figure Click Next. Figure 33. MegaWizard Plug-In Manager - LPM_ROM [page 1 of 3] 5. To initialize the memory block with a hexadecimal (Intel-format) file (.hex) or a memory initialization file (.mif) file, browse to the file location in the What is the name of the file containing the memory initialization data? section. See Figure Altera Corporation

33 6. Click Next to see a summary of the files that MegaWizard creates. or Click Finish to complete the process. Figure 34. MegaWizard Plug-In Manager - LPM_ROM [page 2 of 3] Altera Corporation 33

34 ESB Timing Diagrams Figures show the timing diagram for different ESB modes, such as single-port, dual-port, bidirectional dual-port RAM and ROM. Single-Port RAM Synchronous write operations into the memory block uses the address[] and data[] port, triggered by the rising edge of inclock while the write enable (we) port is enabled. The outclock port for the read operation is optional. The largest usage of dual-port RAMs is in communications, which includes the exchange of data between processors and systems. Figures show the synchronous and asynchronous timing diagrams of a single-port RAM. Figure 35. Synchronous Read/Write Cycle Timing of a Single-Port RAM (Unregistered Output)) Figure 36. Synchronous Read/Write Block Diagram of a Single-Port RAM (Unregistered Output) 34 Altera Corporation

35 Figure 37. Synchronous Read/Write Cycle Timing of a Single-Port RAM (Registered Output) Figure 38. Synchronous Read/Write Block Diagram of a Single-Port RAM (Registered Output) Altera Corporation 35

36 Figure 39. Asynchronous Read/Write Cycle Timing of a Single-Port RAM Note (1) Note to Figure 39: (1) In asynchronous mode, when we (write enable) is asserted, the address cannot change. Figure 40. Asynchronous Read/Write Block Diagram of a Single-Port RAM Dual-Port RAM Figures show the dual-port RAM read/write configurations and timing diagrams. Read/Write The following situations can occur when simultaneously reading and writing to the same address in dual-port RAM: Unregistered output port 1. The read clock's frequency is greater than 2x the write clock's frequency. The write clock has not written the data at this point; therefore, the old data value is read. 36 Altera Corporation

37 2. Dual-port RAM uses the same clock for reading and writing. The newly written data appears at the output after a delay of t ESBDD after the falling edge of the clock. At slower clock frequencies, the old data value can appear shortly after the rising edge of the clock followed by the newly written data, which appears t ESBDD nanoseconds after the falling edge. 1 Check the data sheet for the value of t ESBDD in the timing model section. Registered output port 3. The read clock is very fast (frequency > 1/t EABDD ). The q output reads the old data value. 4. Dual-port RAM uses the same clock for reading and writing. The q output reads the newly written data value. 5. The read and write clocks are unrelated, and the read clock has a frequency less than 1/t EABDD. The q output reads the newly written data value. Figure 41. Dual-Port RAM Read/Write Cycle Timing in Single Clock Mode (Unregistered Output) Note to Figure 41: (1) If the read and write operations are targeting the same memory location, the newly written data will be available on the output port q[] on the falling edge of the clock. Altera Corporation 37

38 1 When a read occurs to the same address location with a write operations in progress (write not completed), there is a possibility for having unknown output from the ESB. To prevent this potential contention, the read operation should not start until the write operation is completed. For this to occur, the read operation should not be activated for a minimum amount of time specified as the maximum write cycle time in the ESB. This parameter is t ESBSRC and is specified in the data sheet in the timing model section for each device. Figure 42. Dual-Port RAM Read/Write Block Diagram in Single Clock Mode (Unregistered Output) 38 Altera Corporation

39 Figure 43. Dual-Port RAM Read/Write Cycle Timing in Single Clock Mode (Registered Output) Figure 44. Dual-Port RAM Read/Write Block Diagram in Single Clock Mode (Registered Output) Altera Corporation 39

40 Figure 45. Dual-Port RAM Read/Write Cycle Timing in Shared Clock Mode (Registered Output) Notes to Figure 45: (1) If both read and write operations are targeting the same memory location, the present read cycle will result in data that was previously written into that memory location. The newly written data is only present in the next read cycle. (2) rden is deasserted so that the newly written data into 0A is valid on the output port q[]. (3) New data at memory location 0A is not driven out on the output port q[] because the next read cycle is retrieving data from the previous memory location 0A. Figure 46. Dual-Port RAM Read/Write Block Diagram in Shared Clock Mode (Registered Output) 40 Altera Corporation

41 Figure 47. Dual-Port RAM Read/Write Cycle Timing in Separate Clock Mode (Registered Output) Note to Figure 47 (1) During this simultaneous read/write operation the new data is written in memory location 0B at the falling edge of wrclock. Since the output port q[] is registered, this newly written data, 2 is available at the output port q[] only during the next rdclock cycle. Figure 48. Dual-Port RAM Read/Write Block Diagram in Separate Clock Mode (Registered Output) Altera Corporation 41

42 Figure 49. Dual-Port RAM Read/Write Cycle Timing in Separate Clock Mode (Unregistered Output) Note to Figure 49: (1) Since the output port q[] is unregistered, the newly written data at memory location 0B is available at the falling edge of wrclock. Figure 50. Dual-Port RAM Read/Write Block Diagram in Separate Clock Mode (Unregistered Output) 42 Altera Corporation

43 Figure 51. Dual-Port RAM Read/Write Cycle Timing in Asynchronous Clock Mode Note (1) Note to Figure 51: (1) In asynchronous mode, when we (write enable) is asserted, the address cannot be changed. Figure 52. Dual-Port RAM Read/Write Block Diagram in Asynchronous Clock Mode Bidirectional Dual-Port RAM Figures show the bidirectional dual-port RAM read and write operations on both ports A and B. Read/ Write In bidirectional dual-port RAM, each port can read and write. As a result, port A and port B can write at the same time, read at the same time, or read and write alternately. It might happen that both ports write to the same address location at the same time, which causes an invalid data. To prevent this potential write contention, make sure that writes do not occur at the same address simultaneously. Single Clock Mode Only one clock is used for the input, output, write, and read signals. The output is available one clock cycle later because the inputs and outputs are registered. Altera Corporation 43

44 Figure 53. Bidirectional Dual-Port RAM Write & Read Cycle TIming in Single Clock Mode (Inputs & Outputs Registered) Figure 54. Bidirectional Dual-Port RAM Write & Read Block Diagram in Single Clock Mode (Inputs & Outputs Registered) 44 Altera Corporation

45 Figure 55. Bidirectional Dual-Port RAM Write & Read Cycle Timing in Single Clock Mode (Only Inputs Registered) Figure 56. Bidirectional Dual-Port RAM Write & Read in Single Clock Mode (Only Inputs Registered) Altera Corporation 45

46 Double Clock Mode Each port can have a separate clock. The same clock performs writes and reads on each port. See Figures Figure 57. Bidirectional Dual-Port Write & Read Cycle Timing RAM Dual Clock Mode (Inputs & Outputs Registered) Figure 58. Bidirectional Dual-Port RAM Write & Read Block Diagram Dual Clock Mode (Inputs & Outputs Registered) 46 Altera Corporation

47 Asynchronous Bidirectional Dual-Port RAM Figures show the asynchronous bidirectional dual-port RAM timing diagram. Figure 59. Asynchronous Bidirectional Dual-Port RAM Cycle Timing with Simultaneous Write & Read on Ports A & B Notes to Figure 59: (1) Data 6, 7, and 0 is written into address 3. (2) Output port B reads out data 6, 7, and 0. (3) Write enable for port A and B should be high to write or read from memory and should stay low during address transition. Figure 60. Asynchronous Bidirectional Dual-Port RAM Block Diagram with Simultaneous Write & Read on Ports A & B Altera Corporation 47

48 FIFO Figures show the read/write cycle of a single or double clock FIFO. Figure 61. Single-Clock FIFO: Write, Empty Flag, & Simultaneous Read/Write Cycle Waveform (Legacy Synchronous FIFO Mode) Figure 62. Single-Clock FIFO Full Flag Waveform (Legacy Synchronous FIFO Mode) 48 Altera Corporation

49 Figure 63. Single-Clock FIFO Full Flag Waveform (Legacy Synchronous FIFO Mode) Figure 64. Single-Clock FIFO: Read Cycle & Empty Flag (Legacy Synchronous FIFO Mode) Note to Figure 64: (1) There are six clock cycles of latency on the rdempty flag. This number can be changed by changing the delay parameters listed earlier. Altera Corporation 49

50 Figure 65. Dual-Clock FIFO Read Cycle Waveform (Legacy Synchronous FIFO Mode) Note to Figure 65: (1) There are six clock cycles from the first rdclock edge after the data is written to when the data is available to be read. This number can be changed by changing the delay parameters. Also, note that the rdempty flag went high after the second read was done (reading 2). This is due to the relationship between the read an write frequencies. Figure 66. Dual-Clock FIFO Full Flag Waveform (Legacy Synchronous FIFO Mode) Note to Figure 66: (1) In this case, the FIFO is 32 words deep. Note that when the 31st word is written into the FIFO, the wfull flag goes high. For an explanation, please see Dual Clock Mode on page Altera Corporation

51 Figure 67. Dual-Clock FIFO Read-Acknowledge Waveform (Show-Ahead Mode) Note to Figure 67: (1) The first piece of data that is written into the FIFO flows through to the output on the next clock edge of rdclock. In this type of FIFO, the read is acknowledged and not requested. Therefore, even though data 3 is on the q[] port after the second read is done, it still has not been read. Altera Corporation 51

52 ROM Figures show the operation of the lpm_rom function in the following modes Asynchronous Synchronous with q[] output registered Synchronous with address[] and q[] ports registered Figure 68. Read Timing During Asynchronous Memory Operation Note: to Figure 68: (1) During this asynchronous memory operation, the data on the q[] output changes after a certain delay following a change in the address[] input. The MIF file used by this ROM function specifies the data in locations FF and 33 to be FFFF and 3333, respectively. Figure 69. Read Timing During Asynchronous Memory Operation 52 Altera Corporation

53 Figure 70. Read Timing With Registered ROM Output q[] Note: to Figure 70: (1) When the q[] output port is registered, the output register is loaded with the contents of the memory location pointed to by address[] at every rising edge of outclock. Figure 71. Read Timing With Registered ROM Output [q] Altera Corporation 53

54 Figure 72. Read Timing With Registered address[] Input & q[] Output Using The Same Clock Note to Figure 72: (1) The memenab port tri-states the q[] output when it has a logic low level. Although, the memenab port does not affect the address[] input from being registered. After memenab is set to a logic high level, the q[] output register captures the data from the ROM location pointed to by the registered address[] input. Figure 73. Read Timing With Registered address[] Input & q[] Output Using The Same Clock 54 Altera Corporation

55 Initialization Files A memory initialization file (MIF) or hexadecimal file (HEX) specifies the initial value for each memory address. Memory Initialization File An ASCII text file with the extension.mif specifies the initial content of a memory block. These initial values for each address in the.mif file are used during project compilation and/or simulation. Use the Memory Editor in the Quartus II software to create.mif files. Each memory block requires a separate.mif file. A MIF must also specify the memory depth and width values. Optionally, a MIF can specify the radixes used to display and interpret addresses and data values. 1 If multiple values are specified for the same address, only the last value is used. Figure 74 shows a sample.mif file. Figure 74. Sample MIF File DEPTH = 32; % Memory depth and width are required. % WIDTH = 14; % Enter a decimal number. % ADDRESS_RADIX = HEX; % Address and value radixes are required. % DATA_RADIX = HEX; % Enter BIN, DEC, HEX, OCT, or UNS unless otherwise % % specified, radixes = HEX. % Specify values for addresses, which can be a single address or range. CONTENT BEGINS [0..F] : 3FFFF; % Range--Every address from 0 to F = 3FFFF. % 6 : F; % Single address. Address 6 = F. % 8 : F E 5; % Range starting from specific address. % % Addr[8] = F, Addr[9] = E, Addr[A] = 5. % END HEX (Intel-Format) File The Quartus II software can use an ASCII text file with the extension.hex in the Intel-format to store configuration data for one or more Altera devices, to store the initial memory values for a memory block implemented in an Altera device, or to build software project executables. Altera Corporation 55

56 A HEX file can be used as an input file for memory initialization in the Compiler and Simulator. Use the Memory Editor to create a HEX File. The Software mode can use a HEX file as an output file. A software application can be built as a HEX File. Creating a MIF or HEX File To create a (.mif) or (.hex): 1. Choose New (File menu). 2. In the New dialog box, click the Other Files tab. 3. To create a MIF, select Memory Initialization File or to create a HEX File, select Hexadecimal File. 4. Click OK. 5. In the Number of Words & Word Size dialog box, type the number of words in the Number of words box. 6. In the Word size box, type the size of the words. 7. Click OK. Figure 75 shows a sample MIF table. 56 Altera Corporation

57 Figure 75. An 8-bit MIF Table Applications of ESB Memory APEX II ESB memory configurations are suitable for a variety of applications. The following paragraphs suggest possible applications of the different memory configurations. RAM Configurations RAM memory can be used for communication between systems. In these applications, RAM can be partitioned into virtual data-storage areas, or buffers, usually storing at least two data packets. The buffers are shared between the communications controller and the intelligent host that assembles the packets and stores them usually a microprocessor. If the system contains only one processor, the data buffers are not shared and the system needs neither a virtual nor a physical dual-port RAM. Single-Port RAM Single-port RAM can be used in applications that require parallel data transfer because the write and read ports are the same width. Dual-Port RAM Configuration Dual-port RAM has applications in the general areas of wide area networks, storage networks, and wireless infrastructures. Some specific applications can be in switches and routes, RAID directors, host bus adapters, and cellular base stations. Dual-port RAM can be used in applications that require parallel data transfer, because the two independent clock ports allow different access rates for read and write operations. Also, the presence of dual-addressing enables simultaneous read and write operations in the same clock cycle. Altera Corporation 57

58 Bus Width Mismatch A simple dual-port RAM can be used in APEX II devices for read and write width mismatch since RAM cells have independent read and write ports. This feature can be used for serialization or deserialization of some high-speed applications that use ESB blocks. Because the speed of some signals to the ESB may be too high to b used for internal logic, they need to be slowed down. Deserializing the serialized incoming signals is the method used to slow down signals. The ESB s dual-port RAM feature can perform deserialization and serialization because it supports a mismatched bus width configuration on its ports. Bidirectional Dual-Port RAM Because bidirectional dual-port RAM can read or write simultaneously at both ports, it can be used in applications that require quick data access, such as in switches and routers. ROM Configuration ROM can be used to implement all functions that only need to perform read operations. FIFO Configuration Using FIFO is a way to increase data throughput to an I/O interface while minimizing central processing unit (CPU) wait states. FIFO buffers transfer data between the host bus and the peripheral systems. Some common applications using FIFO buffers are SCSI and integrated drive electronics (IDE) interfaces, bus-width conversion applications (e.g., 8-bit to 32-bit conversions), and asynchronous transfer mode (ATM) network interface cards. Conclusion With bidirectional dual-port RAM becoming the desired and preferred choice in the market, the ESBs in APEX II devices have been enhanced to accommodate this new memory structure. Bidirectional dual-port RAM can be used in different applications where the ability to access data simultaneously by two different processes is a requirement. In addition, the ESB in APEX II with its enhanced memory structure is able to divide the ESB into two identical 2K single-port RAM blocks for applications that required more memory blocks. 58 Altera Corporation

59 101 Innovation Drive San Jose, CA (408) Applications Hotline: (800) 800-EPLD Literature Services: Copyright 2002 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. 59 Altera Corporation