International Journal of Advanced Research in Computer Science and Software Engineering
|
|
- Clementine Christiana Gilbert
- 5 years ago
- Views:
Transcription
1 Volume 2, Issue 1, October 212 ISSN: X International Journal of Advanced Research in Computer Science and Software Engineering Research Paper Available online at: Special Issue: Recent Trend in Computing Conference Held in SRM University, NCR Campus, India Speed Comparison for Embedded Processors Using Infinite Series Samuel Noah Ramrajkar, SheltonD souza, Rahul J Shetty,Shraddha Joshi Abstract The following paper describes in detail the Embedded CPU benchmarking algorithm that we have developed. The paper gives a brief description about the existing benchmarking methods. It then talks about our algorithm used for benchmarking and finally ends with the results that we found in a tabular and graphic format. Keywords: benchmarking, Synthetic Programs I. INTRODUCTION Processors are ubiquitous in today's world. They interpret and implement software instructions, perform calculations and comparisons, make logical decisions and interact with other devices. Almost any electronic device contains a processor, and their computing power ranges from a few thousand to millions of instruction per second. They come in many sizes and shapes, vary in speed and have different instruction sets, are designed for different use, and so their capabilities vary greatly. Even within a specific area, processors are different enough to make it difficult to compare them. Benchmarks provide a method of comparing the performance of processors and rank them among their peers. The term benchmark was created and used by surveyors. After surveying an area, surveyors chiselled marks in which they placed an angle-iron to bracket (bench) the rod to indicate the exact position from where they took their measurements for future reference. From there, the word benchmark found its way into computer science CPU benchmarking is a type of measurement for computer performance that is applied to the central processing unit, or CPU, of the computer system. These measurements provide a set of standards that allow users to compare the performance of different machines under the same circumstances. In CPU benchmarking, observers often assess the clock rate or other types of processor functions. The benchmark provides the core standard for the design of a CPU, or simply be recorded in quality or production research. II. TYPES OF BENCHMARKING Benchmarks can be roughly divided into 5 groups. Those groups are: 1. Addition Instruction 2. Instruction Mixes 3. Kernels 4. Synthetic Programs 5. Application Benchmarks 1) Addition Instruction Earlier, computers had very few instructions and the addition instruction was the most common instruction so performance was measured by counting how many additions a computer could perform per unit time. 2) Instruction Mixes Measurements based on a single instruction had the disadvantage that they did not take into account that other instructions had different complexities. Hence, instruction mixes was used. The number of times each instruction appears in the mix should ideally reflect the frequency with that the instruction appears in an average program. However, emerging processors continued to increase the number of instructions in the instruction set making it difficult to include all the instructions in the instruction mix. Also, with the introduction of advanced features like pipelining and address translations, execution time of instruction started to depend instructions executed before and after the instruction. 3) Kernels Kernel benchmarks are based on analysis and the knowledge that in most cases 1 percent ofthe code uses 8 percent of the CPU resources. Performance analysts have extracted these codefragments and have used them as benchmarks.the fundamental problems with kernelbenchmarks are that they are usually small, fit in cache, are prone to attack by compilers, andmeasure only CPU performance. The disadvantage of Kernels is that they do not reflect the behaviour of a typical application of issuing system calls and interacting with I/O devices. 212, IJARCSSE All Rights Reserved Page 37
2 Samuel et al., International Journal of Advanced Research in Computer Science and Software Engineering 2 (1), October- 212, pp ) Synthetic Programs Synthetic programs are developed by exercising a mix of computations, system calls and I/O requests. The main advantage of synthetic programs is that they can be quickly developed and do not rely on real data. To assure portability, these programs are written in a high level language. Types of synthetic benchmark are: a. Whetstone The Whetstone benchmark primarily measures the floating point arithmetic performance. It contains ten modules that perform a variety of numerical computations (e.g., arrays, trigonometric functions). The benchmark is small and sensitive to the ordering of library modules and size of caches. The performance metrics are single- and double precision Whetstones per second b. Dhrystone This synthetic benchmark spends significant time on string functions. It was designed to measure the integer performance of small machines with simple architectures. The performance metric is Dhrystones per second. These were the first general purpose industry standard benchmarks. The main drawback of synthetic programs is that they are too small to make statistically relevant memory or disk references. Similar issues arise with page faults, disk cache hits/misses, and the CPU-I/O overlap. 5) Application Benchmarks By far, the most accurate way to get measurements reflecting application program performance is to use applications as benchmarks. a set of 'typical' applications is used to compute an overall performance score. These benchmarks are generally identical to the original applications with the exception of small modifications made to automate the evaluation process. Application benchmarks are also not perfect since they evaluate the whole computer instead of just the processor. Embedded processors are yet another kind of processor. They are typically designed for a specific task. Embedded processors usually run on a lower voltage and frequency, have fewer instructions, and have narrower instruction words. Recently however, embedded processors have become more and more powerful. Nevertheless, embedded processors are different enough to justify their own benchmarks. III. OUR ALGORITHM The benchmarking algorithm is based on the principle of counting the number of terms of a power series e^x. The value of x for the current benchmarking was fixed at an arbitrary value of two. The series is given by e x = 1 + x 1! + x2 2! + x3 3! +. This clearly shows that the computations per term increases exponentially and this can be a real identifier of the speed of the CPU under test Following are the main components of the algorithm. A. Main() This part of the code is the entry function for the code after start-up. It begins by the initialization of the timer (usually of timer ) for the micro-controller so that it can interrupt the processor at duration of 1 sec. This is followed by initialization of the UART module to a predefined baud rate of 192 for displaying the count of terms on the PC screen next section initializes the timer interrupt and only then allows the timer to run. The heart of the algorithm follows this in the while (1) loop. The calculation for the terms starts and goes on till 1 second. The variable terms is the global variable where the value of terms calculated is available any time. Note that the compiler is made aware that it is a shared data variable using volatile modifier.. B. TIMER_ISR() This is the interrupt handler used for timer interrupt that converts the counted terms in to decimal number. It then displays this count on the PC screen. It uses the %1 1 algorithm for this. The ISR then locks up the processor in an infinite loop as the test for the speed is complete. C. send_uart_data This function is a used to send the data to the UART port. The basic idea behind the benchmarking is the fact that more the number of terms calculated more is the speed of the CPU under test. Also it is worth to guess that the calculation of the terms becomes increasingly complex with the 212, IJARCSSE All Rights Reserved Page 38
3 Samuel et al., International Journal of Advanced Research in Computer Science and Software Engineering 2 (1), October- 212, pp increase in the index. This algorithm we believe lies in the segment of Synthetic Programs. The synthesis can easily prove the processing power of an embedded CPU in situations where heavy duty calculations are needed. Such applications could be DSP applications like the digital filter or signal reconstruction algorithms. This may also prove the worth of a CPU for running applications needing the super loop type of execution because the calculation of the terms itself is in a super loop. IV. THE BENCHMARKING CODE void send_uart_data(unsigned char); //function to send data volatile unsigned short int terms; //actual terms calculated void TIMER_Isr() irq unsigned char data[1];//to store the digits of count unsigned short int temp; unsigned char i,j; //disable timer interrupt i=; temp=terms; while(temp!=) data[i]=temp%1; //%1 1 algorithm temp=temp/1; i++; i--; for(j=;j<3;j++) send_uart_data(data[i] x3); i--; while(1); //soft stop the program void main() doubleans; unsignedintvar,index; index=; ans=; var=2; terms=; //set timer to interrupt on 1 sec //enable timer interrupt //enable the UART here //enable timer only now to start counting while(1) unsignedinttemp,i; doublepow; long double fact; temp=index; pow=1; fact=1; for(i=temp;i>;i--) pow=pow*var; for(i=temp;i>;i--) fact=fact*i; ans=ans+(double)(pow/fact); index++; 212, IJARCSSE All Rights Reserved Page 39
4 Number of terms Number of terms Samuel et al., International Journal of Advanced Research in Computer Science and Software Engineering 2 (1), October- 212, pp terms++; V. OBSERVATIONS The following are the tabular and graphical results obtained when the benchmarking algorithm was run on the selected processor. The tables indicate if the results were obtained from simulations, practical hardware or both. A. Cortex M3 (lpc1768) TABLE I OBSERVATIONS FOR CORTEX M3 of operation (in MHz) Terms/sec (simulated) Terms/sec (hardware) y = -.47x x Fig.1 Graph for Cortex M3- Number of terms vs. B. ARM7 (lpc2148) TABLE III OBSERVATIONS FOR ARM7 of Terms/sec operation (in MHz) (simulated) Terms/sec (hardware) y = -.41x x , IJARCSSE All Rights Reserved Page 4
5 Number of Terms Samuel et al., International Journal of Advanced Research in Computer Science and Software Engineering 2 (1), October- 212, pp Fig. 2 Graph for ARM7 Number of terms vs. C. AVR ATMEGA 328 TABLE IIIII OBSERVATIONS FOR AVR of operation (in Terms/sec MHz) (simulated) y = -.516x x D. PIC18 (PIC18F452) Fig. 3 Graph for AVR ATMEGA Number of terms vs. TABLE IVV OBSERVATIONS FOR PIC18 of operation (in Terms/sec MHz) (simulated) y = -.128x x E. 851 (NXP P89V51RD2) Fig. 4. Graph for PIC18 Number of terms vs. TABLE V OBSERVATIONS FOR 851 of operation (in Terms/sec (simulated) MHz) , IJARCSSE All Rights Reserved Page 41
6 Number of terms Samuel et al., International Journal of Advanced Research in Computer Science and Software Engineering 2 (1), October- 212, pp y = -.8x x VI. CONCLUSIONS The benchmarking code was successfully executed in simulation and in hardware. The benchmarking results are selfexplanatory an provide a quick selection guide for an embedded designer to select his processor when core speed is a selection criterion. The algorithm is a better choice as it evaluates the true computing power of the CPU. As the number of terms increases it is worthy to note that the processor is really very powerful as the computing steps increases exponentially with each term. VII.FUTURE SCOPE The benchmarking algorithm is to be extended to RTOS applications with a fixed pair of processor and RTOS can be benched marked with the score of (terms/sec)/process. The work on this will soon commence. REFERENCES [1] Benjamin C Lee. An Architectural Assessment of SPECCPU Benchmark Relevance Internet: ftp://ftp.deas.harvard.edu/techreports/tr-2-6.pdf [2] Christopher Cullian, ChristopherWyant, Timothy Frattesi. Computing Performance Benchmarks among CPU, GPU, and FPGA Internet: [3] Internet: / [4] SHARC Processor Benchmarks Internet:/ [5] Computing Performance Benchmarks among CPU, GPU, and FPGA. Internet: [6] Exponential Function. Internet: 212, IJARCSSE All Rights Reserved Page 42
Q.1 Explain Computer s Basic Elements
Q.1 Explain Computer s Basic Elements Ans. At a top level, a computer consists of processor, memory, and I/O components, with one or more modules of each type. These components are interconnected in some
More informationPower Measurements using performance counters CSL862: Low-Power Computing By Radhika D (2014SIY7530)
Power Measurements using performance counters CSL862: Low-Power Computing By Radhika D (214SIY753) 1 Objective: To observe and note the performance and power consumption of Raspberry PI for various benchmark
More informationReporting Performance Results
Reporting Performance Results The guiding principle of reporting performance measurements should be reproducibility - another experimenter would need to duplicate the results. However: A system s software
More informationMigrating to Cortex-M3 Microcontrollers: an RTOS Perspective
Migrating to Cortex-M3 Microcontrollers: an RTOS Perspective Microcontroller devices based on the ARM Cortex -M3 processor specifically target real-time applications that run several tasks in parallel.
More informationMemory Addressing, Binary, and Hexadecimal Review
C++ By A EXAMPLE Memory Addressing, Binary, and Hexadecimal Review You do not have to understand the concepts in this appendix to become well-versed in C++. You can master C++, however, only if you spend
More informationI/O Systems (3): Clocks and Timers. CSE 2431: Introduction to Operating Systems
I/O Systems (3): Clocks and Timers CSE 2431: Introduction to Operating Systems 1 Outline Clock Hardware Clock Software Soft Timers 2 Two Types of Clocks Simple clock: tied to the 110- or 220-volt power
More informationEmbedded Systems Dr. Santanu Chaudhury Department of Electrical Engineering Indian Institution of Technology, Delhi
Embedded Systems Dr. Santanu Chaudhury Department of Electrical Engineering Indian Institution of Technology, Delhi Lecture - 34 Compilers for Embedded Systems Today, we shall look at the compilers, which
More informationBenchmarking: Classic DSPs vs. Microcontrollers
Benchmarking: Classic DSPs vs. Microcontrollers Thomas STOLZE # ; Klaus-Dietrich KRAMER # ; Wolfgang FENGLER * # Department of Automation and Computer Science, Harz University Wernigerode Wernigerode,
More informationPage 1. Program Performance Metrics. Program Performance Metrics. Amdahl s Law. 1 seq seq 1
Program Performance Metrics The parallel run time (Tpar) is the time from the moment when computation starts to the moment when the last processor finished his execution The speedup (S) is defined as the
More informationIn examining performance Interested in several things Exact times if computable Bounded times if exact not computable Can be measured
System Performance Analysis Introduction Performance Means many things to many people Important in any design Critical in real time systems 1 ns can mean the difference between system Doing job expected
More informationEmbedded Software TI2726 B. 4. Interrupts. Koen Langendoen. Embedded Software Group
Embedded Software 4. Interrupts TI2726 B Koen Langendoen Embedded Software Group What is an Interrupt? Asynchronous signal from hardware Synchronous signal from software Indicates the need for attention
More informationCPE300: Digital System Architecture and Design
CPE300: Digital System Architecture and Design Fall 2011 MW 17:30-18:45 CBC C316 Number Representation 09212011 http://www.egr.unlv.edu/~b1morris/cpe300/ 2 Outline Recap Logic Circuits for Register Transfer
More informationAdvanced Microcontrollers Grzegorz Budzyń Lecture. 1: Introduction
Advanced Microcontrollers Grzegorz Budzyń Lecture 1: Introduction Plan Introduction Course requirements Workplan for thesemester Firstlecture Basic definitions, Microcontroller, Microprocessor Introduction
More informationThe bottom line: Performance. Measuring and Discussing Computer System Performance. Our definition of Performance. How to measure Execution Time?
The bottom line: Performance Car to Bay Area Speed Passengers Throughput (pmph) Ferrari 3.1 hours 160 mph 2 320 Measuring and Discussing Computer System Performance Greyhound 7.7 hours 65 mph 60 3900 or
More informationE85 Lab 8: Assembly Language
E85 Lab 8: Assembly Language E85 Spring 2016 Due: 4/6/16 Overview: This lab is focused on assembly programming. Assembly language serves as a bridge between the machine code we will need to understand
More informationNewbie s Guide to AVR Interrupts
Newbie s Guide to AVR Interrupts Dean Camera March 15, 2015 ********** Text Dean Camera, 2013. All rights reserved. This document may be freely distributed without payment to the author, provided that
More informationComputer Architecture. Minas E. Spetsakis Dept. Of Computer Science and Engineering (Class notes based on Hennessy & Patterson)
Computer Architecture Minas E. Spetsakis Dept. Of Computer Science and Engineering (Class notes based on Hennessy & Patterson) What is Architecture? Instruction Set Design. Old definition from way back
More informationAN4777 Application note
Application note Implications of memory interface configurations on low-power STM32 microcontrollers Introduction The low-power STM32 microcontrollers have a rich variety of configuration options regarding
More informationSeparating Reality from Hype in Processors' DSP Performance. Evaluating DSP Performance
Separating Reality from Hype in Processors' DSP Performance Berkeley Design Technology, Inc. +1 (51) 665-16 info@bdti.com Copyright 21 Berkeley Design Technology, Inc. 1 Evaluating DSP Performance! Essential
More informationLecture 25: Interrupt Handling and Multi-Data Processing. Spring 2018 Jason Tang
Lecture 25: Interrupt Handling and Multi-Data Processing Spring 2018 Jason Tang 1 Topics Interrupt handling Vector processing Multi-data processing 2 I/O Communication Software needs to know when: I/O
More informationDesign of CPU Simulation Software for ARMv7 Instruction Set Architecture
Design of CPU Simulation Software for ARMv7 Instruction Set Architecture Author: Dillon Tellier Advisor: Dr. Christopher Lupo Date: June 2014 1 INTRODUCTION Simulations have long been a part of the engineering
More informationEmbedded Technology for Remote Data Logging, Monitoring and Controlling Using GSM/GPRS
Embedded Technology for Remote Data Logging, Monitoring and Controlling Using GSM/GPRS Sonika Bhagwatrao Jadhav 1, Prof. Ajay S. Wadhawe 2 Research Scholar (M.E.), Dept of ECE, SSIEMS, Parbhani, Maharashtra,
More informationUNIT -3 PROCESS AND OPERATING SYSTEMS 2marks 1. Define Process? Process is a computational unit that processes on a CPU under the control of a scheduling kernel of an OS. It has a process structure, called
More informationEmbedded System Curriculum
Embedded System Curriculum ADVANCED C PROGRAMMING AND DATA STRUCTURE (Duration: 25 hrs) Introduction to 'C' Objectives of C, Applications of C, Relational and logical operators, Bit wise operators, The
More informationInterrupts and Time. Real-Time Systems, Lecture 5. Martina Maggio 28 January Lund University, Department of Automatic Control
Interrupts and Time Real-Time Systems, Lecture 5 Martina Maggio 28 January 2016 Lund University, Department of Automatic Control Content [Real-Time Control System: Chapter 5] 1. Interrupts 2. Clock Interrupts
More informationPerformance. February 12, Howard Huang 1
Performance Today we ll try to answer several questions about performance. Why is performance important? How can you define performance more precisely? How do hardware and software design affect performance?
More informationGUJARAT TECHNOLOGICAL UNIVERSITY
GUJARAT TECHNOLOGICAL UNIVERSITY BRANCH NAME: INSTRUMENTATION & CONTROL ENGINEERING (17) SUBJECT NAME: EMBEDDED SYSTEM DESIGN SUBJECT CODE: 2171711 B.E. 7 th SEMESTER Type of course: Core Engineering Prerequisite:
More informationInput And Output of C++
Input And Output of C++ Input And Output of C++ Seperating Lines of Output New lines in output Recall: "\n" "newline" A second method: object endl Examples: cout
More informationEE251: Tuesday December 4
EE251: Tuesday December 4 Memory Subsystem continued Timing requirements Adding memory beyond 4 Gbyte Time Allowing: Begin Review for Final Exam Homework #9 due Thursday at beginning of class Friday is
More informationInterrupts and Time. Interrupts. Content. Real-Time Systems, Lecture 5. External Communication. Interrupts. Interrupts
Content Interrupts and Time Real-Time Systems, Lecture 5 [Real-Time Control System: Chapter 5] 1. Interrupts 2. Clock Interrupts Martina Maggio 25 January 2017 Lund University, Department of Automatic
More informationCS3350B Computer Architecture CPU Performance and Profiling
CS3350B Computer Architecture CPU Performance and Profiling Marc Moreno Maza http://www.csd.uwo.ca/~moreno/cs3350_moreno/index.html Department of Computer Science University of Western Ontario, Canada
More informationMEASURING COMPUTER TIME. A computer faster than another? Necessity of evaluation computer performance
Necessity of evaluation computer performance MEASURING COMPUTER PERFORMANCE For comparing different computer performances User: Interested in reducing the execution time (response time) of a task. Computer
More informationAdaptive Motion Control of FIREBIRD V Robot
Available Online at www.ijcsmc.com International Journal of Computer Science and Mobile Computing A Monthly Journal of Computer Science and Information Technology ISSN 2320 088X IMPACT FACTOR: 6.017 IJCSMC,
More informationCortex-M3/M4 Software Development
Cortex-M3/M4 Software Development Course Description Cortex-M3/M4 software development is a 3 days ARM official course. The course goes into great depth and provides all necessary know-how to develop software
More informationi960 Microprocessor Performance Brief October 1998 Order Number:
Performance Brief October 1998 Order Number: 272950-003 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
More informationLecture - 4. Measurement. Dr. Soner Onder CS 4431 Michigan Technological University 9/29/2009 1
Lecture - 4 Measurement Dr. Soner Onder CS 4431 Michigan Technological University 9/29/2009 1 Acknowledgements David Patterson Dr. Roger Kieckhafer 9/29/2009 2 Computer Architecture is Design and Analysis
More informationARM Cortex core microcontrollers 3. Cortex-M0, M4, M7
ARM Cortex core microcontrollers 3. Cortex-M0, M4, M7 Scherer Balázs Budapest University of Technology and Economics Department of Measurement and Information Systems BME-MIT 2018 Trends of 32-bit microcontrollers
More informationAli Karimpour Associate Professor Ferdowsi University of Mashhad
AUTOMATIC CONTROL SYSTEMS Ali Karimpour Associate Professor Ferdowsi University of Mashhad Main reference: Christopher T. Kilian, (2001), Modern Control Technology: Components and Systems Publisher: Delmar
More informationComputer Architecture. What is it?
Computer Architecture Venkatesh Akella EEC 270 Winter 2005 What is it? EEC270 Computer Architecture Basically a story of unprecedented improvement $1K buys you a machine that was 1-5 million dollars a
More informationApplication Note One Wire Digital Output. 1 Introduction. 2 Electrical Parameters for One Wire Interface. 3 Start and Data Transmission
Application Note One Wire Digital Output 1 Introduction The pressure transmitter automatically outputs pressure data, and when appropriate temperature data, in a fixed interval. The host simply waits for
More informationFundamentals of Quantitative Design and Analysis
Fundamentals of Quantitative Design and Analysis Dr. Jiang Li Adapted from the slides provided by the authors Computer Technology Performance improvements: Improvements in semiconductor technology Feature
More informationLecture Topics. Principle #1: Exploit Parallelism ECE 486/586. Computer Architecture. Lecture # 5. Key Principles of Computer Architecture
Lecture Topics ECE 486/586 Computer Architecture Lecture # 5 Spring 2015 Portland State University Quantitative Principles of Computer Design Fallacies and Pitfalls Instruction Set Principles Introduction
More informationEmbedded Soc using High Performance Arm Core Processor D.sridhar raja Assistant professor, Dept. of E&I, Bharath university, Chennai
Embedded Soc using High Performance Arm Core Processor D.sridhar raja Assistant professor, Dept. of E&I, Bharath university, Chennai Abstract: ARM is one of the most licensed and thus widespread processor
More informationLecture 05 I/O statements Printf, Scanf Simple statements, Compound statements
Programming, Data Structures and Algorithms Prof. Shankar Balachandran Department of Computer Science and Engineering Indian Institute of Technology, Madras Lecture 05 I/O statements Printf, Scanf Simple
More informationAli Karimpour Associate Professor Ferdowsi University of Mashhad
AUTOMATIC CONTROL SYSTEMS Ali Karimpour Associate Professor Ferdowsi University of Mashhad Main reference: Christopher T. Kilian, (2001), Modern Control Technology: Components and Systems Publisher: Delmar
More informationLRU. Pseudo LRU A B C D E F G H A B C D E F G H H H C. Copyright 2012, Elsevier Inc. All rights reserved.
LRU A list to keep track of the order of access to every block in the set. The least recently used block is replaced (if needed). How many bits we need for that? 27 Pseudo LRU A B C D E F G H A B C D E
More informationEngineer To Engineer Note
Engineer To Engineer Note EE-134 Phone: (800) ANALOG-D, FAX: (781) 461-3010, EMAIL: dsp.support@analog.com, FTP: ftp.analog.com, WEB: www.analog.com/dsp Copyright 2001, Analog Devices, Inc. All rights
More informationARM HOW-TO GUIDE Interfacing GLCD with LPC2148 ARM
ARM HOW-TO GUIDE Interfacing GLCD with LPC2148 ARM Contents at a Glance ARM7 LPC2148 Primer Board... 3 GLCD (Graphical Liquid Crystal Display)... 3 Interfacing GLCD... 4 Interfacing GLCD with LPC2148...
More informationINTERRUPTS in microprocessor systems
INTERRUPTS in microprocessor systems Microcontroller Power Supply clock fx (Central Proccesor Unit) CPU Reset Hardware Interrupts system IRQ Internal address bus Internal data bus Internal control bus
More informationInstructor Information
CS 203A Advanced Computer Architecture Lecture 1 1 Instructor Information Rajiv Gupta Office: Engg.II Room 408 E-mail: gupta@cs.ucr.edu Tel: (951) 827-2558 Office Times: T, Th 1-2 pm 2 1 Course Syllabus
More informationARM HOW-TO GUIDE Interfacing Switch with LPC2148 ARM
ARM HOW-TO GUIDE Interfacing Switch with LPC48 ARM Contents at a Glance ARM7 LPC48 Primer Board... 3 Switch... 3 Interfacing Switch... 4 Interfacing Switch with LPC48... 5 Pin Assignment with LPC48...
More informationFundamentals of Operating Systems (COMP355/L) A Student's Manual for Practice Exercises
Fundamentals of Operating Systems (COMP355/L) A Student's Manual for Practice Exercises Text Book: Operating System Concepts 9 th Edition Silberschatz, Galvin and Gagne 2013 1 Practice Exercises #1 Chapter
More informationWhat is This Course About? CS 356 Unit 0. Today's Digital Environment. Why is System Knowledge Important?
0.1 What is This Course About? 0.2 CS 356 Unit 0 Class Introduction Basic Hardware Organization Introduction to Computer Systems a.k.a. Computer Organization or Architecture Filling in the "systems" details
More informationLab 3a: Scheduling Tasks with uvision and RTX
COE718: Embedded Systems Design Lab 3a: Scheduling Tasks with uvision and RTX 1. Objectives The purpose of this lab is to lab is to introduce students to uvision and ARM Cortex-M3's various RTX based Real-Time
More informationECE 471 Embedded Systems Lecture 2
ECE 471 Embedded Systems Lecture 2 Vince Weaver http://web.eece.maine.edu/~vweaver vincent.weaver@maine.edu 7 September 2018 Announcements Reminder: The class notes are posted to the website. HW#1 will
More informationImplementation of FFT Processor using Urdhva Tiryakbhyam Sutra of Vedic Mathematics
Implementation of FFT Processor using Urdhva Tiryakbhyam Sutra of Vedic Mathematics Yojana Jadhav 1, A.P. Hatkar 2 PG Student [VLSI & Embedded system], Dept. of ECE, S.V.I.T Engineering College, Chincholi,
More informationAdvanced processor designs
Advanced processor designs We ve only scratched the surface of CPU design. Today we ll briefly introduce some of the big ideas and big words behind modern processors by looking at two example CPUs. The
More informationMemory Bandwidth and Low Precision Computation. CS6787 Lecture 9 Fall 2017
Memory Bandwidth and Low Precision Computation CS6787 Lecture 9 Fall 2017 Memory as a Bottleneck So far, we ve just been talking about compute e.g. techniques to decrease the amount of compute by decreasing
More informationAbstract. Testing Parameters. Introduction. Hardware Platform. Native System
Abstract In this paper, we address the latency issue in RT- XEN virtual machines that are available in Xen 4.5. Despite the advantages of applying virtualization to systems, the default credit scheduler
More informationInstruction Set Principles and Examples. Appendix B
Instruction Set Principles and Examples Appendix B Outline What is Instruction Set Architecture? Classifying ISA Elements of ISA Programming Registers Type and Size of Operands Addressing Modes Types of
More informationLab Assignment Each team will independently implement the launch interceptor specification For this assignment, you re writing portable C code
Lab Assignment Each team will independently implement the launch interceptor specification For this assignment, you re writing portable C code We ll worry about I/O later Lab Assignment You are allowed
More information2008 Chapter-8 L1: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill, Inc.
REAL TIME OPERATING SYSTEMS Lesson-1: OPERATING SYSTEM SERVICES GOAL, MODES AND STRUCTURE 1 1. OS Services Goal 2 Goal The OS Service Goal Perfection and correctness during a service 3 OS Services Goal
More informationPractice Exercises 449
Practice Exercises 449 Kernel processes typically require memory to be allocated using pages that are physically contiguous. The buddy system allocates memory to kernel processes in units sized according
More informationChapter 15 ARM Architecture, Programming and Development Tools
Chapter 15 ARM Architecture, Programming and Development Tools Lesson 07 ARM Cortex CPU and Microcontrollers 2 Microcontroller CORTEX M3 Core 32-bit RALU, single cycle MUL, 2-12 divide, ETM interface,
More informationThe Role of Performance
Orange Coast College Business Division Computer Science Department CS 116- Computer Architecture The Role of Performance What is performance? A set of metrics that allow us to compare two different hardware
More informationLast class: Today: Course administration OS definition, some history. Background on Computer Architecture
1 Last class: Course administration OS definition, some history Today: Background on Computer Architecture 2 Canonical System Hardware CPU: Processor to perform computations Memory: Programs and data I/O
More informationCOL862 - Low Power Computing
COL862 - Low Power Computing Power Measurements using performance counters and studying the low power computing techniques in IoT development board (PSoC 4 BLE Pioneer Kit) and Arduino Mega 2560 Submitted
More informationLab 3b: Scheduling Multithreaded Applications with RTX & uvision
COE718: Embedded System Design Lab 3b: Scheduling Multithreaded Applications with RTX & uvision 1. Objectives The purpose of this lab is to introduce students to RTX based multithreaded applications using
More informationCS 110 Computer Architecture
CS 110 Computer Architecture Performance and Floating Point Arithmetic Instructor: Sören Schwertfeger http://shtech.org/courses/ca/ School of Information Science and Technology SIST ShanghaiTech University
More informationELC4438: Embedded System Design Embedded Processor
ELC4438: Embedded System Design Embedded Processor Liang Dong Electrical and Computer Engineering Baylor University 1. Processor Architecture General PC Von Neumann Architecture a.k.a. Princeton Architecture
More informationArchitecture and OS. To do. q Architecture impact on OS q OS impact on architecture q Next time: OS components and structure
Architecture and OS To do q Architecture impact on OS q OS impact on architecture q Next time: OS components and structure Computer architecture and OS OS is intimately tied to the hardware it runs on
More informationIntroduction CHAPTER. Practice Exercises. 1.1 What are the three main purposes of an operating system? Answer: The three main puropses are:
1 CHAPTER Introduction Practice Exercises 1.1 What are the three main purposes of an operating system? Answer: The three main puropses are: To provide an environment for a computer user to execute programs
More informationComputer Architecture A Quantitative Approach, Fifth Edition. Chapter 2. Memory Hierarchy Design. Copyright 2012, Elsevier Inc. All rights reserved.
Computer Architecture A Quantitative Approach, Fifth Edition Chapter 2 Memory Hierarchy Design 1 Introduction Programmers want unlimited amounts of memory with low latency Fast memory technology is more
More informationEmbedded Systems Dr. Santanu Chaudhury Department of Electrical Engineering Indian Institute of Technology, Delhi
Embedded Systems Dr. Santanu Chaudhury Department of Electrical Engineering Indian Institute of Technology, Delhi Lecture - 13 Virtual memory and memory management unit In the last class, we had discussed
More informationMODERN FORTRAN MODERN FORTRAN MODERN FORTRAN PDF FORTRAN - WIKIPEDIA PRODUCTS PAGE THE FORTRAN COMPANY 1 / 5
PDF FORTRAN - WIKIPEDIA PRODUCTS PAGE THE FORTRAN COMPANY 1 / 5 2 / 5 3 / 5 modern fortran pdf Naming. The names of earlier versions of the language through FORTRAN 77 were conventionally spelled in all-capitals
More informationECE2049 E17 Lecture 4 MSP430 Architecture & Intro to Digital I/O
ECE2049-E17 Lecture 4 1 ECE2049 E17 Lecture 4 MSP430 Architecture & Intro to Digital I/O Administrivia Homework 1: Due today by 7pm o Either place in box in ECE office or give to me o Office hours tonight!
More informationLecture 2: Computer Performance. Assist.Prof.Dr. Gürhan Küçük Advanced Computer Architectures CSE 533
Lecture 2: Computer Performance Assist.Prof.Dr. Gürhan Küçük Advanced Computer Architectures CSE 533 Performance and Cost Purchasing perspective given a collection of machines, which has the - best performance?
More informationCSE 410 Computer Systems. Hal Perkins Spring 2010 Lecture 12 More About Caches
CSE 4 Computer Systems Hal Perkins Spring Lecture More About Caches Reading Computer Organization and Design Section 5. Introduction Section 5. Basics of Caches Section 5. Measuring and Improving Cache
More informationAN Entering ISP mode from user code. Document information. ARM ISP, bootloader
Rev. 03 13 September 2006 Application note Document information Info Keywords Abstract Content ARM ISP, bootloader Entering ISP mode is normally done by sampling a pin during reset. This application note
More informationMulticore computer: Combines two or more processors (cores) on a single die. Also called a chip-multiprocessor.
CS 320 Ch. 18 Multicore Computers Multicore computer: Combines two or more processors (cores) on a single die. Also called a chip-multiprocessor. Definitions: Hyper-threading Intel's proprietary simultaneous
More informationLESSON 5 FUNDAMENTAL DATA TYPES. char short int long unsigned char unsigned short unsigned unsigned long
LESSON 5 ARITHMETIC DATA PROCESSING The arithmetic data types are the fundamental data types of the C language. They are called "arithmetic" because operations such as addition and multiplication can be
More informationCS430 Computer Architecture
CS430 Computer Architecture Spring 2015 Spring 2015 CS430 - Computer Architecture 1 Chapter 14 Processor Structure and Function Instruction Cycle from Chapter 3 Spring 2015 CS430 - Computer Architecture
More information1993 Paper 3 Question 6
993 Paper 3 Question 6 Describe the functionality you would expect to find in the file system directory service of a multi-user operating system. [0 marks] Describe two ways in which multiple names for
More informationCpE 442 Introduction to Computer Architecture. The Role of Performance
CpE 442 Introduction to Computer Architecture The Role of Performance Instructor: H. H. Ammar CpE442 Lec2.1 Overview of Today s Lecture: The Role of Performance Review from Last Lecture Definition and
More informationTimed Compiled-Code Functional Simulation of Embedded Software for Performance Analysis of SOC Design
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 22, NO. 1, JANUARY 2003 1 Timed Compiled-Code Functional Simulation of Embedded Software for Performance Analysis of
More informationInternational Journal of Advanced Research in Computer Science and Software Engineering
Volume 2, Issue 9, September 2012 ISSN: 2277 128X International Journal of Advanced Research in Computer Science and Software Engineering Research Paper Available online at: www.ijarcsse.com Case Study
More informationFabric Image Retrieval Using Combined Feature Set and SVM
Available Online at www.ijcsmc.com International Journal of Computer Science and Mobile Computing A Monthly Journal of Computer Science and Information Technology ISSN 2320 088X IMPACT FACTOR: 5.258 IJCSMC,
More informationNAME: Problem Points Score. 7 (bonus) 15. Total
Midterm Exam ECE 741 Advanced Computer Architecture, Spring 2009 Instructor: Onur Mutlu TAs: Michael Papamichael, Theodoros Strigkos, Evangelos Vlachos February 25, 2009 NAME: Problem Points Score 1 40
More informationOperating Systems. Introduction & Overview. Outline for today s lecture. Administrivia. ITS 225: Operating Systems. Lecture 1
ITS 225: Operating Systems Operating Systems Lecture 1 Introduction & Overview Jan 15, 2004 Dr. Matthew Dailey Information Technology Program Sirindhorn International Institute of Technology Thammasat
More informationLPC4088 Timer Interrupts CM0506 Small Embedded Systems
LPC4088 Timer Interrupts CM0506 Small Embedded Systems Dr Alun Moon Seminar 5 Here the module begins to separate from EN0572. The programming structure will make extensive use of interrupts to handle events,
More informationEE251: Thursday November 30
EE251: Thursday November 30 Course Evaluation Forms-fill out Memory Subsystem continued Timing requirements Adding memory beyond 4 Gbyte Time Allowing: Begin Review for Final Exam Homework due next Tuesday,
More informationComputer Organization and Design, 5th Edition: The Hardware/Software Interface
Computer Organization and Design, 5th Edition: The Hardware/Software Interface 1 Computer Abstractions and Technology 1.1 Introduction 1.2 Eight Great Ideas in Computer Architecture 1.3 Below Your Program
More informationUsing a Separation Kernel to Protect against the Remote Exploitation of Unaltered Passenger Vehicles
Safety & Security for the Connected World Using a Separation Kernel to Protect against the Remote Exploitation of Unaltered Passenger Vehicles 16 th June 2015 Mark Pitchford, Technical Manager, EMEA Today
More informationMemory Bandwidth and Low Precision Computation. CS6787 Lecture 10 Fall 2018
Memory Bandwidth and Low Precision Computation CS6787 Lecture 10 Fall 2018 Memory as a Bottleneck So far, we ve just been talking about compute e.g. techniques to decrease the amount of compute by decreasing
More informationARM HOW-TO GUIDE Interfacing Buzzer with LPC2148 ARM
ARM HOW-TO GUIDE Interfacing Buzzer with LPC2148 ARM Contents at a Glance ARM7 LPC2148 Primer Board... 3 Buzzer... 3 Interfacing Buzzer... 4 Interfacing Buzzer with LPC2148... 5 Pin Assignment with LPC2148...
More informationPERFORMANCE MEASUREMENTS OF REAL-TIME COMPUTER SYSTEMS
PERFORMANCE MEASUREMENTS OF REAL-TIME COMPUTER SYSTEMS Item Type text; Proceedings Authors Furht, Borko; Gluch, David; Joseph, David Publisher International Foundation for Telemetering Journal International
More informationArchitectures & instruction sets R_B_T_C_. von Neumann architecture. Computer architecture taxonomy. Assembly language.
Architectures & instruction sets Computer architecture taxonomy. Assembly language. R_B_T_C_ 1. E E C E 2. I E U W 3. I S O O 4. E P O I von Neumann architecture Memory holds data and instructions. Central
More informationVon Neumann architecture. The first computers used a single fixed program (like a numeric calculator).
Microprocessors Von Neumann architecture The first computers used a single fixed program (like a numeric calculator). To change the program, one has to re-wire, re-structure, or re-design the computer.
More informationEfficiency and memory footprint of Xilkernel for the Microblaze soft processor
Efficiency and memory footprint of Xilkernel for the Microblaze soft processor Dariusz Caban, Institute of Informatics, Gliwice, Poland - June 18, 2014 The use of a real-time multitasking kernel simplifies
More informationNew ARMv8-R technology for real-time control in safetyrelated
New ARMv8-R technology for real-time control in safetyrelated applications James Scobie Product manager ARM Technical Symposium China: Automotive, Industrial & Functional Safety October 31 st 2016 November
More information