DDR Testing:Compliance,Verify and Debug( 一 )

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1 DDR Testing:Compliance,Verify and Debug( 一 ) Double data-rate (DDR) memory has ruled the roost as the main system memory in PCs for a long time. Of late, it's seeing more usage in embedded systems as well. Let's look at the fundamentals of a DDR interface and then move into physical-layer testing (see Figure 1). Figure 1: A representative test setup for physical-layer DDR testing A DDR interface entails each DRAM chip transferring data to/from the memory controller by means of several digital data lines. These data streams are accompanied by a strobe signal. Because data can flow both from the controller to the DRAM (write operation) and from the DRAM to the controller (read operation, these digital lines are bidirectional in nature. Common clock, command, and address lines serve all DRAM chips. Because these lines control the interface's operation, they are unidirectional between the controller and the memory ICs. Figure 2 illustrates the "fly-by" topology in use beginning with the DDR3 standard.

2 Figure 2: Common clock, command, and address lines link DRAM chips and controller DDR is "double data rate" memory because of how data transfers are timed: a byte is transmitted on the rising edge of the clock, and another on the falling edge of the clock. The clock runs at half of the DDR data rate and is distributed to all memory chips. The DDR command bus consists of several signals that control the operation of the DDR interface. Command signals are clocked only on the rising edge of the clock. Possible command states vary by DDR speed grade but can include: deselect, no operation, read, write, bank activate, precharge, refresh, and mode register set. The address bus selects which cells of the DRAM are being written to or read from. Like the command bus, the address bus is singleclocked. The bit values on the bus determine the bank, row, and column being written or read. Due to the interface's bi-directional nature, data is transferred between the memory and controller in bursts. To that end, the strobe (DQS) signal is a differential "bursted clock" that only functions during read and write operations. In most DDR generations since its inception, the timing relationship between the strobe and data signals is different for reads and writes (see Figure 3).

3 Figure 3: The timing relationship between the DDR strobe and data signals is different for reads and writes Finally, each DRAM chip has multiple parallel data lines (DQ0, DQ1, and so on) that carry data from the controller to the DRAM for write operations and vice versa for read operations. The data signals are true double data-rate signals that transition at the same rate as the clock/strobe (two transfers per clock cycle). DDR memory interfaces are becoming increasingly common, and present a unique set of challenges to those designing high-speed embedded systems. This article will examine what DDR interface testing is all about, concentrating primarily on the physical layer and solutions to common problems. Physical-layer tests ascertain whether the voltage levels, timing, and signal fidelities are adequate for a system to function correctly. This is distinct from protocol-layer testing, which determines whether the controller and memory chips are communicating properly at the digital level and above. Within the domain of physical-layer test are three subcategories: Compliance: Do the device output signals comply with the JEDEC specification? Validation: Do the devices interact correctly within the system environment? Debug: Why is my device/system not behaving as it should?

4 Compliance test means a raft of specific, mandated tests; these tests are critically important for DRAM and controller vendors. Validation tests, which are less prescriptive but require fuller visibility into system behavior, are critical for system integrators. Debug requires an exhaustive view of system behavior and typically follow from failed compliance tests and/or flawed system behavior. Figure 4: Analyzing the interplay between the high-speed signals and the command bus deepens insight into DDR behavior Which DDR signals are important for such testing? In physical-layer compliance and validation testing, the fastest signals shown in Figure 1 are the most critical: clock (CK), strobe (DQS), and data (DQn). These signals must be analyzed as analog waveforms to fully characterize their signal fidelity. And because there are many data lines in a DDR interface, testing all of them is a time-consuming proposition. Thus, in many instances, board-level simulation reveals the most likely worst-case data lines to isolate them for testing.

5 Figure 5: Shown is an example of a complete DDR analysis system To gain a more complete system-level view, analyzing the interactions between the high-speed CK, DQ, and DQS signals and the slower command bus gives much deeper insight into behavior. In many cases, it is sufficient to acquire the digital state of these signals so long as the acquisition achieves high timing accuracy. What would a complete DDR analysis system look like? Figure 5 provides an example. For acquisition of analog signals, a highbandwidth oscilloscope is paired with low-loading differential probes. Digital signals call for a high-sample-rate digital analyzer and high-bandwidth digital probe. On the oscilloscope, analysis software handles identification of bursts and performs measurements.

6 Figure 6: Shown is a typical BGA package for DDR memory Now let's look into some of the specific challenges one faces in a close examination of these interfaces. The first test challenge is simply accessing the signals of interest. These days, DRAM chips come in ball-grid-array (BGA) packages that are wave-soldered to a matching array of pads on the PCB (Figure 6). How does one get to those pads?

7 Figure 7: Interposers that sit between the DRAM chip and PCB can alleviate difficult signal access Three common approaches to making BGA solder joints accessible include: backside vias, interposers, and DIMM series resistors. If they're included in the PCB layout, backside vias can be the ideal spot at which to probe DDR signals. Typically, good signal fidelity results from the vias' proximity to the termination. However, many devices, such as dual-rank DIMMs and dense embedded systems render this access option untenable. The second option of interposers can also be useful in difficult access situations (Figure 7). As with backside vias, interposers afford reasonably good signal fidelity. However, they impose additional complexity if the socket is to be installed correctly. In addition, the interposer's footprint can be problematic on crowded PCBs.

8 Figure 8: DIMM series resistors are a good alternative for dual-rank DIMMs If dual-rank (or two-sided) DIMMs are involved, the backside vias won't be accessible. This makes DIMM series resistors a good alternate location for signal access (Figure 8). The downside of this approach is that the distance between the probe and the DRAM's terminations can result in problematic reflections from the receiver.