DDR4 SO-DIMM Interposer For use with Keysight Logic Analyzers

Transcription

1 DDR4 SO-DIMM Interposer For use with Keysight Logic Analyzers FS2512 DDR4 SO-DIMM Interposer Key Features Quick and easy connection between the 260 pin DDR4 SODIMM memory bus connector and the U4164A Keysight logic analyzer Complete and accurate MT/s state and timing analysis up to 12.5 GHz Flexible design fits into both RVS and STD connectors Compatible with 260 pin DDR4 SO-DIMM's All signals are probed passively. Does not require U4201A probe cables Registered and Unbuffered SODIMMs are supported. Burst sizes of 2, 4, or 8 are supported. Monitors Writes only, Reads only, or Writes and Reads Quick and easy setup using Keysight Eye Scan with 5 ps resolution Upgrade path from the 256 pin FS2502B available New 260 pin JEDEC DDR4 SO-DIMM support Industries first DDR4 SO-DIMM MT/s Interposer Used with Keysight U4154A/B or U4164A logic analyzer Includes protocol-decode software, probe configuration software, and automatic logic analyzer configuration software Interposer design does not consume a slot Offers full Clock Qualification for U4154A/B or U4164A Powerful, Reliable MT/s Protocol Decode The FS2512 is a 2400MT/s+ Double Data Rate (DDR4) SDRAM bus interposer for Small Outline DIMMs (SO- DIMMs). It provides complete protocol decode of memory transactions using an Keysight logic analyzer as the analysis execution engine. This combination provides powerful triggering, debug and compliance verification measurements. Data is decoded and displayed at any level of detail from the protocol to binary levels. Helping you Design Tomorrow s Computers, Today FuturePlus Systems is the technology leader in protocol analysis tools for the computer design industry. Our analysis probes and software help you monitor and verify complex activities on your advanced technology computer bus design. FuturePlus systems offerings include bus-analysis solutions for most popular computer buses. Visit for more information. Since 1991

2 Accurate State Analysis The FS2512 DDR4 2400MT/s+ SO-DIMM memory bus interposer brings bus signals to the U4164A Keysight logic analyzer via controlled impedance cables for an easy protocol analysis connection while maintaining signal fidelity. No U4201A adapter cables are required. Protocol Analysis State and Timing Analysis The FS2512 protocol-decode software translates acquired signals into easily understood bus transactions, at the full bus speed. The Keysight logic analyzer provides extensive triggering and store qualification features. The FS2512 interposer can be configured to perform State analysis of Reads or Writes, or both Reads and Writes, at 2400 MT/s+. What are the advantages of using an interposer? The DDR protocol decode software executes in the logic analyzer and takes user input on system attributes such as Burst length, CAS and Additive Latency, as well as Chip Selects to decode the key DDR bus signals and present a display that lists the transaction type, address, data and command conditions. The software also supports user-defined symbols that can be easily added to the state listing display. Userselectable post-processing filters allow the acquired data to display different types of transactions indifferent colors. More Powerful No sacrifice of a slot like a VDIMM-SODIMM You can test a fully loaded bus with an interposer! More Flexible Allows the use of any SO-DIMM from any vendor Lower Cost Interposer enables debugging of any SO-DIMM configuration More reliable Less components, no memory chips

3 Signal Integrity Measurements Quickly measure signal integrity with Keysight EyeScan Technology. As timing and voltage margins continue to shrink, confidence in signal integrity becomes an increasingly vital requirement of the design verification process. EyeScan lets you quickly acquire comprehensive signal integrity information on the DDR4 bus in your design, and can provide measurements with 5 ps/5mv of resolution. If a trace exhibits excessive skew or eye closure, the user interface allows you to activate that trace independently to examine it in more detail. The U4154A/B or U4164A Workspace User Input for Protocol Decode Quick EyeScan Full EyeScan by varying both time and voltage

4 FS WRITE EyeScan FS READ EyeScan

5 FS2512 Mechanical Dimensions The FS2512 interposer installed in a system with an SODIMM Ordering Information FS2512 DDR4 SO-DIMM Interposer for use with the U4154A/B or U4164A Keysight Logic Analyzer Software Licenses FS1193 DDR4 Windows License for FS2512, one is included in each FS2512. Software includes: Configuration files for the U4154A/B Keysight logic analyzer Protocol Decoder software, runs on the Keysight logic analyzer Keysight Logic Analyzer Requirements The FS2512 requires - 1 ea M9502A two-slot AXIe chassis - 2 ea U4154A/B or U4164A 136-channel Logic Analyzer Modules for use at bus speeds of <2500MT/s FuturePlus Systems Corporation 15 Constitution Dr Bedford, NH Tel: Fax: Website: Protocol.Decode@FuturePlus.com FuturePlus Systems does not assume any responsibility for use of any circuitry described, and reserves the right to change circuitry and specifications at any time without notice. FuturePlus is a registered trademark of FuturePlus Systems Corporation. 9/17