V6300 Product Brief. Version: 0.5 Release Date: September 15, Specifications are subject to change without notice.

Transcription

1 Version: 0.5 Release Date: September 15, 2016 Specifications are subject to change without notice This document contains information that is proprietary to Unauthorized reproduction of this information in whole or in part is strictly prohibited.

2 General Description The V6300 is a narrowband Power Line Communication (PLC) processor chip. The V6300 integrates one 32-bit MCU, one 32-bit DSP, one embedded Flash memory, two UART interfaces, one SPI Master controller, one SPI Slave interface, one I 2 C Master interface, PLC MAC/PHY layer functions, and Analog Front-End (AFE). Accompanied with Vango s high-current drive line driver chip (V6000), the V6300 forms a complete modem solution to support all known narrowband PLC Standards. Features Supporting multiple narrowband PLC Standards: G3-PLC, IEEE P1901.2, PRIME, ITU-T G.hnem; also supporting single-carrier or multi-carrier PLC with FSK or BPSK/DBPSK modulation schemes With high-linearity and high-current drive line driver (V6000) having integrated receive functions, it offers the lowest BM cost for G3-PLC/PRIME standards. Supporting frequency bands: CENELEC, FCC, and ARIB Supporting modulations: Selectable differential and coherent BPSK, QPSK, 8PSK, and coherent 16QAM Supporting IPv6 networking layer Supporting G3-PLC compliant 6LoWPAN adaptation layer with optimized network formation and mesh routing function Supporting HW AES-128 Two UART interfaces (UART0 and UART1). UART1 is high-speed UART supporting up to 500-Kbps baud rate. It can be used to control wireless transceiver, metering, or other SPI devices. ne SPI Slave interface for alternative data interface with Master processor chip ne I 2 C Master interface to control other I 2 C devices 256-KB embedded Flash memory Supporting In-System Programming (ISP) of Flash memory via UART0 or SPI Slave interface Up to 32 programmable GPIs for maximal flexibility 3.3-V digital. UART pins are 5 V tolerant. Integrated LD (3.3 V to 1.2 V) Packages: V6300P: 80-pin T/LQFP V6300N: 68-pin QFN perating temperature: -40 C ~ +85 C ne SPI Master with two chip select pins

3 System Block Diagram Vango PLC Processor (V6300) Smart Metering Chip UART MCU MAC PHY AFE Vango PLC Line Driver (V6000) Line Coupling Circuit Power Line Figure 1. Example of Leaf Node Application Vango PLC Processor (V6300) Vango PLC Line Driver (V6000) Line Coupling Circuit Host Processor Host Interface: UART/SPI MCU MAC PHY AFE Analog Switch Vango PLC Line Driver (V6000) Line Coupling Circuit 3-Phase Power Line Vango PLC Line Driver (V6000) Line Coupling Circuit Figure 2. Example of Concentrator Application - 2 -

4 Pin Assignments 68L-QFN V6300 Product Brief MSPI_MSI/GPI16 MSPI_MIS/GPI15 MSPI_CS1/GPI18 MSPI_CS0/GPI19 GPI13 GPI12 GPI11 GPI10 TXN TXP NC NC AVDD33 RXP RXN NC LD_CLK LD_SCL LD_SDA UART0_TXD UART0_RXD GPI2 MSPI_CLK/GPI17 GPI9 GPI7 GPI8 I2C_SDA/GPI21 I2C_SCL/GPI20 GPI14 GPI27 GPI28 GPI22 GPI23 GPI24 GPI25 GPI26 RESETN GPI0 GPI1 XTAL_IN XTAL_UT AVDD33 V L-QFN LD_GND 3V3_IN 1V2_UT UART1_RTS UART1_CTS/GPI30 UART1_TXD UART1_RXD GPI31 GPI29 SSPI_CLK SSPI_MSI SSPI_MIS SSPI_FS/GPI30 GPI5 GPI4 17 GPI3 GPI6 NTE: The exposed thermal pad is connected to the ground

5 - 4-80L-T/LQFP V L-T/LQFP TXUTN LD_SDA LD_SCL LD_CLK NC RXINN RXINP TIN TXUTP GPI5 GPI4 GPI9 GPI7 MSPI_SCLK/GPI17 GPI26 GPI25 GPI24 GPI23 GPI22 RESETN XTAL_IN XTAL_UT AVDD33 UART0_RXD UART0_TXD I2C_SCL/GPI20 GPI8 I2C_SDA/GPI21 UART1_TXD UART1_RXD UART1_RTS UART1_CTS/GPI30 SSPI_FS/GPI30 SSPI_MIS SSPI_MSI SSPI_SCLK MSPI_CS1/GPI18 MSPI_CS0/GPI19 MSPI_MIS/GPI15 MSPI_MSI/GPI16 GPI13 GPI12 GPI11 GPI10 1V2_UT 3V3_IN GPI2 TIP AVDD33 GPI0 GPI GPI6 GPI29 AVSS AVSS AVSS GPI GPI27 GPI28 GPI GPI31 LD_GND AVSS33 AVSS33

6 Pin Descriptions V6300 Product Brief 68L-QFN (Pin type: =utput, I = Input, P =Power, G =Ground) 1 TXN DAC differential output (Negative) to line driver chip (V6000) 2 TXP DAC differential output (Positive) to line driver chip (V6000) 3 NC NC. Always keep floating 4 NC NC. Always keep floating 5 AVDD33 P Analog 3.3-V power 6 RXP I ADC differential input (Positive) from line driver chip (V6000) 7 RXN I ADC differential input (Negative) from line driver chip (V6000) 8 NC NC 9 LD_CLK Clock output to line driver chip (V6000) 10 LD_SCL Line driver (V6000) control interface clock output 11 LD_SDA Line driver (V6000) control interface data 12 P Digital 1.2-V power 13 UART0_TXD 14 UART0_RXD I Low-Speed UART port 0: Data output Supporting baud rate from 1200 bps to bps Low-Speed UART port0: Data input Supporting baud rate from 1200 bps to bps 15 P Digital 3.3-V power 16 GPI2 General Purpose 17 GPI3 General Purpose 18 GPI4 General Purpose 19 GPI5 General Purpose 20 P Digital 1.2-V power - 5 -

7 21 SSPI_FS GPI30 I Slave SPI frame sync input General Purpose GPI30 can be used either on pin 21 or pin SSPI_MIS Slave SPI data output 23 SSPI_MSI I Slave SPI data input 24 SSPI_CLK I Slave SPI clock input 25 P Digital 3.3-V power 26 GPI29 General Purpose 27 GPI31 General Purpose 28 UART1_RXD I 29 UART1_TXD High-speed UART port 1: Data input Supporting baud rate from 1200 bps to 500K bps High-speed UART port 1: Data output Supporting baud rate from 1200 bps to 500K bps 30 UART1_CTS GPI30 High-speed UART port 1: Clear to Send General Purpose GPI30 can be used either on pin 21 or pin UART1_RTS I High-speed UART port 1: Request to Send 32 1V2_UT P Internal LD 1.2-V output It must be tied to all the 1.2-V power pin of V V3_IN P Internal LD 3.3-V input 34 LD_GND G Internal LD ground 35 I2C_SCL GPI20 Master I 2 C port serial clock General Purpose 36 I2C_SDA GPI21 Master I 2 C port serial data General Purpose 37 GPI8 General Purpose 38 GPI7 General Purpose 39 GPI6 General Purpose - 6 -

8 40 P Digital 1.2-V power 41 GPI9 General Purpose 42 GPI10 General Purpose 43 GPI11 General Purpose 44 GPI12 General Purpose 45 GPI13 General Purpose 46 P Digital 3.3-V power 47 MSPI_CS0 GPI19 Master SPI select 0 General Purpose 48 MSPI_CS1 GPI18 Master SPI select 1 General Purpose 49 MSPI_MIS GPI15 I Master SPI data input General Purpose 50 MSPI_MSI GPI16 Master SPI data output General Purpose 51 MSPI_CLK GPI17 Master SPI clock output General Purpose 52 GPI14 General Purpose 53 GPI27 General Purpose 54 GPI28 General Purpose 55 P Digital 3.3-V power 56 GPI22 General Purpose 57 GPI23 General Purpose 58 GPI24 General Purpose 59 GPI25 General Purpose 60 GPI26 General Purpose 61 P Digital 1.2-V power 62 G Must be tied to GND - 7 -

9 63 RESETN I Reset input (Active low). It should be pulled low at least 100 ms for reset period. 64 GPI0 General Purpose 65 GPI1 General Purpose 66 XTAL_IN I Input of crystal oscillator driver (24 MHz) 67 XTAL_UT utput of crystal oscillator driver 68 AVDD33 P Analog 3.3-V power 80L-T/LQFP (Pin type: =utput, I = Input, P =Power, G =Ground) 5,7,10,76,80 AVSS P Analog ground 16,24,31,38,48,60,70,72 G Digital ground Note: Signal pins of the 80L-T/LQFP package are the same as 68L-QFN package. Please refer to Pin Descriptions of 68L-QFN package