VertexCom. VC6320 Product Brief. Version: 0.5 Release Date: June 27, Specifications are subject to change without notice.

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1 VC VC6320 Product Brief Version: 0.5 Release Date: June 27, 2018 Specifications are subject to change without notice Vertexcom Technologies, nc. This document contains information that is proprietary to Vertexcom Technologies, nc. Unauthorized reproduction of this information in whole or in part is strictly prohibited.

2 General Description VC6320 is a broadband Power Line Communication (PLC) Processor. t integrates a 32-bit ARM Cortex M4 MCU and 32-bit DSP, embedded Flash memory, 7 UART interfaces, 3 SP interfaces, 2 2 C interfaces, one 10/100M Ethernet MAC, PLC MAC/PHY layer functions, Analog-Front-End and high current Line Driver. VC6320 is a true single chip SoC that supports multiple modern broadband PLC standards for Smart Grid and other ot applications. VC6320 solution is optimized to provide the most robust AM networking connectivity and state-of-the-art communication performance in the noisy electric grid environments. Features Support multiple Broadband PLC Standards: China SGCC Q/GDW 11612, EEE Support Frequency bands: 1.9 MHz - 12 MHz SGCC HPLC 0.7 MHz MHz ntegrated high linearity, high current and power efficient Line Driver to offer the lowest BM cost for Broadband PLC applications. Support modulations: BPSK, QPSK and 16QAM Up to 7 UART interfaces Three SP interfaces: ne SP Master with 4 chip selects. t can be used to control wireless transceiver, metering or other SP devices ne SP Slave interface for alternative data interface with Host Processor 3 rd SP interface which can be configured as Master or Slave -40 ~ +85 C ne Ethernet MAC with RM interface AES-128/192/256 and SM2/SM3/SM4 Crypto Accelerator 2 MB embedded Flash memory 128 KB SRAM Support n-system Programming of Flash memory via UART0 or SP Slave interface Up to 53 programmable GPs for maximal flexibility 3.3V digital ntegrated DC-DC (3.3V to 1.2V) BUCK Converter Chip power consumption TX Normal Mode: TBA mw RX Listen Mode: TBA mw Deep Sleep Mode: TBA mw 88L-QFN (10x10mm) package perating temperature range: Two 2 C interfaces Four 16-bits PWM timers Vertexcom Technologies, nc. Storage temperature range: -40 ~ +125 C - 1 -

3 Functional Block Diagram PLC AFE & Line Driver Analog Blocks XTAL/SC/PR LD/ADC PMU WDT A Analog RST Flash CLK GP B~F SRAM 16KX32 SRAM 16KX32 PLC MAC & PHY APB Bus M4 PMU AHB Bus Matrix SRAM 0 Ethernet MAC SRAM 1 M4 WC CM4 Crypto Engine DMA Bridge M4 DAP Enhanced PWM 2x2C 3xSP APB Bus 4x32b Timer 4x16b PWM 7xUART 2x S7816 R Carrier Vertexcom Technologies, nc

4 System Block Diagram Figure 1. Single-Phase PLC module application example: Smart Meter UART VC6320 Figure 2. 3-Phase PLC module application example: Smart Meter UART VC6320 Line Coupling Circuit Line Coupling Circuit P N A B C N Vertexcom Technologies, nc

VC6320 Product Brief - 4 - Vertexcom Technologies, nc.

73 50 LDUTP AVDD33 ZCN HVN RXNN LDUTP AVDDHV DVDD33 D8 C8 DVDD33 DVDD33 B10/MSP_SCLK DVDD12 D9 A8 A7 A14/UART2_RX B4/UART2_TX RESETN A9 DVDD33 B3/UART1_TX A13/UART1_RX B1 A0/TCK B9/MSP_CS0 C9/MSP_CS1

5 VC6320 Product Brief Vertexcom Technologies, nc. Pin Assignments (88L-QFN) LDUTP AVDD33 ZCN HVN RXNN LDUTP AVDDHV DVDD33 D8 C8 DVDD33 DVDD33 B10/MSP_SCLK DVDD12 D9 A8 A7 A14/UART2_RX B4/UART2_TX RESETN A9 DVDD33 B3/UART1_TX A13/UART1_RX B1 A0/TCK B9/MSP_CS0 C9/MSP_CS1 B11/MSP_MS B12/MSP_MS C11/MSP_CS2 C10/MSP_CS3 B6/PWM1_CK B0/PWM0_CK RXNP AVDD33 B13/PWM2_CK B15 E B14/PWM3_CK A11 A5 C4/2C_SCL HVBUCK_REF AVDDHV AVDDHV A12/UART0_RX B2/UART0_TX AVDDHV XTALUT XTALN LDUTN LDUTN TUTP TUTN AVDD33 REXT TNN TNP B7 C5/2C_SDA VC6320 DVDD12 A6 A15/RM_MD B5/RM_MDC C6/RM_CRSDV C7/RM_RX0 C12/RM_RX1 B8/RM_REFCLK C13/RM_TX0 C14/RM_TX1 C15/RM_TXEN A10 E3 DVDD12 LD12 AVSS33_BUCK BUCK_LX AVDD33_BUCK C1/SSP_SCLK C3/SSP_MS C2/SSP_MS C0/SSP_CS A1/TMS A2/TD A3/TD A4/TRST E4

6 Pin Descriptions (88L-QFN) (Pin type: =utput, = nput, P =Power, G =Ground) No. Mnemonic Type Description 1 HVN High voltage measurement input. 2 ZCN Zero crossing detection input. 3 TNN nput for engineering testing purpose. Keep floating or tie to ground. 4 TNP nput for engineering testing purpose. Keep floating or tie to ground. 5 RXNN Differential input (negative). 6 RXNP Differential input (positive). 7 AVDD33 P Analog 3.3V power. 8 REXT Connected to 60Khm external resistor. 9 AVDD33 P Analog 3.3V power. 10 XTALN nput of Crystal oscillator driver. (25MHz) 11 XTALUT utput of Crystal oscillator driver. 12 TUTP utput for engineering testing purpose. Keep floating. 13 TUTN utput for engineering testing purpose. Keep floating. 14 AVDD33 P Analog 3.3V power. 15 AVDDHV P Analog 7V power. 16 AVDDHV P Analog 7V power. 17 LDUTN Line Driver differential output (negative). 18 LDUTN Line Driver differential output (negative). 19 LDUTP Line Driver differential output (positive). 20 LDUTP Line Driver differential output (positive). 21 AVDDHV P Analog 7V power. 22 AVDDHV P Analog 7V power. 23 A6 General Purpose Vertexcom Technologies, nc.

7 No. Mnemonic Type Description A15 General Purpose. 24 RM_MD MD signal of RM interface UART3_RX Data input of UART port 3. B5 RM_MDC UART3_TX C6 RM_CRSDV C7 RM_RX0 C12 RM_RX1 B8 RM_REFCLK UART6_TX B15 UART6_RX General Purpose. MDC signal of RM interface. Data output of UART port 3. General Purpose. CRSDV signal of RM interface. General Purpose. RX data bit 0 of RM interface. General Purpose. RX data bit 1 of RM interface. General Purpose. 50MHz reference clock input of RM interface. Data output of UART port 6. General Purpose. Data input of UART port DVDD33 P Digital 3.3V power C13 RM_TXD0 C14 RM_TXD1 General Purpose. TX data bit 0 of RM interface. C15 RM_TXEN B0 General Purpose. TX data bit 1 of RM interface. General Purpose. TXEN signal of RM interface. General Purpose. 35 PWM0_CK PWM0 clock output. UART4_RX Data input of UART port 4. Vertexcom Technologies, nc

8 No. Mnemonic Type Description B6 General Purpose. 36 PWM1_CK PWM1 clock output. UART4_TX Data output of UART port DVDD12 P Digital core power. 38 RESETN Reset input (active low). 39 A5 General Purpose A13 UART1_RX B3 UART1_TX B7 UART5_TX B2 UART0_TX A12 UART0_RX General Purpose. Data input of UART port 1. General Purpose. Data output of UART port 1. General Purpose. Data output of UART port 5. General Purpose. Data output of UART port 0. General Purpose. Data input of UART port DVDD33 P Digital 3.3V power. 46 C8 General Purpose. 47 B13 PWM2_CK General Purpose. PWM2 clock output. 48 D8 General Purpose. 49 D9 General Purpose C10 MSP_CS3 C11 MSP_CS2 General Purpose. Master SP chip select output 3. General Purpose. Master SP chip select output C9 MSP_CS1 General Purpose. Master SP chip select output 1. Vertexcom Technologies, nc

9 No. Mnemonic Type Description 53 B9 MSP_CS0 General Purpose. Master SP chip select output 0. B11 General Purpose. 54 MSP_MS Master SP data input. 55 A11 General Purpose. 56 DVDD33 P Digital 3.3V power B12 MSP_MS B10 MSP_SCLK General Purpose. Master SP data output. General Purpose. Master SP clock output. 59 A7 General Purpose. 60 A8 General Purpose. 61 A9 General Purpose. 62 B14 PWM3_CK General Purpose. PWM3 clock output. 63 A10 General Purpose. 64 E3 General Purpose. 65 DVDD12 P Digital core power. 66 LD12 P nternal LD core voltage power, connect 10uF to GND. 67 AVSS33_BUCK G Analog ground of switching regulator. 68 BUCK_LX P Power output of switching regulator. 69 AVDD33_BUCK P Analog 3.3V input of switching regulator B1 UART5_RX C1 SSP_SCLK General Purpose. Data input of UART port 5. General Purpose. Slave SP clock input. 72 C3 SSP_MS General Purpose. Slave SP data input. Vertexcom Technologies, nc

10 No. Mnemonic Type Description 73 C2 SSP_MS General Purpose. Slave SP data output. C0 General Purpose. 74 SSP_CS Slave SP chip select input. 75 DVDD12 P Digital core power. 76 E2 General Purpose A14 UART2_RX B4 UART2_TX General Purpose. Data input of UART port 2. General Purpose. Data output of UART port DVDD33 P Digital 3.3V power C4 2C_SCL C5 2C_SDA General Purpose. 2C host port serial clock. General Purpose. 2C host port serial data. 82 A0 General Purpose. 83 A1 General Purpose. 84 A2 General Purpose. 85 A3 General Purpose. 86 A4 General Purpose. 87 E4 General Purpose. 88 HVBUCK_REF Reference signal to high-voltage power regulator. EPAD G Must be tied to GND. Vertexcom Technologies, nc

VertexCom. VC83X0 Product Brief. Version: 0.4 Release Date: June 28, Specifications are subject to change without notice.

VertexCom. VC83X0 Product Brief. Version: 0.4 Release Date: June 28, Specifications are subject to change without notice. VC VC83X0 Product Brief Version: 0.4 Release Date: June 28, 2018 Specifications are subject to change without notice. 2018 This document contains information that is proprietary to Unauthorized reproduction