RA x33 Character/Graphic LCD Driver Specification. Version 2.1 September 3, RAiO Technology Inc. Copyright RAiO Technology Inc.

Transcription

1 RAiO 128x33 Character/Graphic LCD Driver Specification Version 2.1 September 3, 2005 RAiO Technology nc. Copyright RAiO Technology nc RAiO TECHNOLOGY NC. 1/6

2 1. General Description The is a Dot-Matrix LCD Driver which supports both character and graphic mode. t built-in a 256Kbyte character ROM that consists of Chinese, English and ASC fonts. The embedded 528Byte display RAM supports up to 128x33 dots LCD panel. The also provides a scrolling buffer memory for scrolling functions. t supports up, down, left and right scrolling features, and all of the scrolling are execute by hardware. n character mode, the supports Chinese BG5 code or GB code. The system(mpu) does not need take a lot of time to show the Chinese font in graphic mode. t also provides small ASC(8x8) and big ASC(8x16) font for English character, Japanese, European and Latin. The integrates many powerful hardware that including Contrast adjustment, 4x5 Key-Scan, eight General Purpose /O and EL Backlight signals for EL driver. The is a high integration chip of LCD ler. t reduce a lot of time for system develop, and save much cost for hardware system that due to it provides many features for related LCD display application. 2. Feature Support both Character and Graphic Mode Support 8080/6800 8/4-bit Parallel nterface and 3-wire/4-wire Serial nterface Built-in 256KB Font ROM: Chinese, English, ASC, Japanese, Latin, Latin-ext A, Latin-ext B Support ASC 8x8/8x16 Half Size Font, 16x16 Full Size Chinese Font Support Maximum 128Seg x 33Com LCD Panel. 2 x 8 Chinese Fonts(16x16), or 4 x 16 English Fonts(8x8) Built-in 528 Bytes Display RAM and 354Byte Scrolling Buffer Built-in 256Byte SRAM for Create Font Built-in 2X~3X(Voltage Booster), Voltage Regulator, Voltage Follower Support 1/33 Duty, 1/6~1/4 Bias Panel Eight General Purpose /O Built-in 4x5 Key Scan Circuit Support Horizontal/Vertical Scrolling Functions Provide Signals for EL Driver Provide 32-Steps Contrast Adjust Build-in RC Oscillator Voltage Operation : Chip 2.5~3.6V COG Module 2.7~3.8V Package : Gold Bump Die 3. System Block Diagram MPU LCD Panel GPO EL Back Light Driver 4 x 5 Key Scan RAiO TECHNOLOGY NC. 2/6

3 4. Block Diagram The is consist of Display RAM, 256Kbyte Font ROM, Command Registers, LCD ler, LCD Driver, Voltage Booster, Voltage Regulator, MPU nterface and Key-Scan circuit. DB[0:7] RD(EN) 528bytes Display RAM + Buffer 256bytes CGRAM WR(R/W) CS D/C(RS) C86 BT4 MPU /F Block 256Kx8 Font ROM LCDC Block P/S KST[3..0] KN[4..0] NT Key Scan Block & NT Register Block Cursor Scroll Driver /F Scan O[7..0] EL_CHRG GPO EL_DCHG RA, RB CLK_SEL EXT_CLK RC Oscillator Voltage Voltage Regulator Voltage Follower VREF RST Booster TEST[2..0] FG S[1:0] Test & Power Circuit 128 Segment Drivers 33 Common Drivers C[2:1]P C[2:1]M ~ SEG0~SEG127 COM0~COM31 COMS_A[1:0] COMS_B[1:0] 5. Pin Definition 5-1 MPU nterface Pin Name /O Description DB[7..0] DB0: SCK DB1: SDA/SDO DB2: RS/SD DB3: CS DB[7:6]: SMOD /O Data Bus When the MPU use parallel mode and 8-bit then all of the DB[7:0] are valid. When use 4-bit then only DB[4:0] are valid, and DB[7:4] have to keep floating. When P/ S is 0, then the interface between MPU and is Serial Mode. The pins DB[7:6](SMOD[1:0]) are used to select which serial mode: RAiO TECHNOLOGY NC. 3/6

4 RD EN WR R/ W D/ C RS CS NT C86 BT4 O SMOD : Serial Mode X : 3-Wire, SCK, SDA, CS are used. 1 0 : 4-Wire, SCK, SDA, RS, CS are used. 1 1 : 4-Wire, SCK, SDO, SD, CS are used. n serial mode, all of the related signals are defined by DB[3:0]: SCK(DB0) : Serial Clock. SDA(DB1) : Bi-direction Mode Serial Data. SDO(DB1) : Data Out. RS(DB2) : Memory/Register Cycle Select. SD(DB2) : Serial Data n. CS (DB3) : Chip Select, active low. The unused pin must keep NC for serial mode. Read or Enable When use 8080 series interface, RD is the read signal and active low. When use 6800 series interface, EN is the Enable signal and active high. Write or Read-Write When use 8080 series interface, WR is the write signal and active low. When use 6800 series interface, this pin is R/ W, active high for read cycle and active low for write cycle. Data/Command Select or Register Select) When use 8080 series interface, this is Data or Command signal. When D/ C is 0, means Register Cycle(or Command Cycle). When D/ C is 1, means Data Access Cycle(Data Cycle). When use 6800 series interface, this is the RS signal. When RS is 0, means Register Cycle and 1 means Data Access Cycle. Chip Select This is a chip enable for. nterrupt Signal This is an interrupt output for MPU. Active low MPU Select C86 = 0 The MPU interface is 8080 series. C86 = 1 The MPU interface is 6800 series(default). Data Bit Select BT4 = 0 The parallel mode is use 8-bit data bus. BT4 = 1 The parallel mode is use 4-bit data bus(default). RAiO TECHNOLOGY NC. 4/6

5 Parallel/Serial Select P/ S P/ S = 0 The MPU interface is serial mode(default). See the setting of DB[7:6]. P/ S = 1 The MPU interface is parallel mode. 5-2 LCD Panel nterface Pin Name /O Description SEG0 ~ SEG127 O Segment Signals for Panel COM0 ~ COM31 O Common Signals for Panel COMS_A[1:0] COMS_B[1:0] DUM_L DUM_R O O con Common Signals for Panel Dummy PAD 5-.3 Clock and Power Pin Name /O Description RA, RB Resister nput These are used to connect a resistor for internal oscillator. ~ O Voltage Source of LCD Driver The relationship of the power is > VSS C1P, C1M Capacitor nput These are used to connect a capacitor for internal Booster. C2P, C2M Capacitor nput These are used to connect a capacitor for internal Booster. O Booster Output VREF Reference Voltage nput This is the refeence voltage input when use an external regulator. CLK_SEL EXT_CLK P P P P Voltage Regulator Output When the internal voltage regulator is disable, this pin is connect to and used to generate ~. Clock Select This pin is used to select the clock source. When CLK_SEL 1, the clock is generated by internal oscillator and the external resistor that connect on RA and RB. When CLK_SEL is 0, the system clock is drive by external pin - EXT_CLK. External Clock When CLK_SEL is 0, this pin is the external clock input. When CLK_SEL is 1, this pin do not used and has to connect or. Power Ground RAiO TECHNOLOGY NC. 5/6

6 5-4 Misc. Pin Name /O Description KST[3..0] O Key Strobe Output KN[4..0] Key Data nput O[7..0] /O General Purpose /O EL_CHRG O EL Charge Signal EL_DCHG O EL Discharge Signal RST Reset TEST[2..0] S[1:0], FG Test Pins These pins must keep NC for normal mode. 6. Pad and Package 264 DUM_L 263 SEG0 262 SEG1 261 SEG2 260 SEG3 259 SEG4 258 SEG5 257 SEG6 256 SEG7 255 SEG8 254 SEG9 253 SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG DUM_R COMS_A0 1 COMS_A1 2 COM0 3 COM1 4 COM2 5 COM3 6 COM4 7 COM5 8 COM6 9 COM7 10 COM8 11 COM9 12 COM10 13 COM11 14 COM12 15 COM13 16 COM14 17 COM15 18 Top View (9065 x 1586) Y (0, 0) X Logo P1 P2 134 COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COMS_B0 117 COMS_B C2M 25 C2M 26 C2P 27 C2P 28 C1M 29 C1M 30 C1P 31 C1P 32 P 33 P P VREF 63 VREF RA 70 RB 71 DB7, SMOD1 72 DB6, SMOD0 73 DB5 74 DB4 75 DB3, CS 76 DB2, RS, SD 77 DB1, SDA, SDO 78 DB0, SCL 79 RD, EN 80 WR, R/W 81 D/C, RS 82 CS 83 C86 84 BT4 85 P/S 86 NT 87 EXT_CLK 88 CLK_SEL 89 KST3 90 KST2 91 KST1 92 KST0 93 KN4 94 KN3 95 KN2 96 KN1 97 KN0 98 O7 99 O6 100 O5 101 O4 102 O3 103 O2 104 O1 105 O0 106 EL_CHRG 107 EL_DCHG 108 RST 109 TEST2 110 TEST1 111 TEST S FG S con 128x33 COG FPC #N #1 COG Module RAiO TECHNOLOGY NC. 6/6