ILI9225. a-si TFT LCD Single Chip Driver 176RGBx220 Resolution and 262K color. Datasheet Preliminary

Transcription

1 a-si TFT LC Single Chip river atasheet Preliminary Version: V22 ocument No: S_V22pdf ILI TECHNOLOGY CORP 4F, No 2, Tech 5 th Rd, Hsinchu Science Park, Taiwan 3, ROC Tel ; Fax

2 Table of Contents Section Page Introduction 6 2 Features 6 3 Block iagram 8 4 Pin escriptions 9 5 Pad Arrangement and Coordination 6 Block escription 2 7 System Interface 23 7 Interface Specifications Input Interfaces i8/8-bit System Interface i8/6-bit System Interface i8/9-bit System Interface i8/8-bit System Interface Serial Peripheral Interface (SPI) RGB Input Interface RGB Interface RGB Interface Timing Moving Picture Mode bit RGB Interface bit RGB Interface bit RGB Interface 4 75 Interface Timing 43 8 Register escriptions 44 8 Registers Access Instruction escriptions Index (IR) Status Read (RS) Start Oscillation (Rh) river Output Control (Rh) LC riving Waveform Control (R2h) Entry Mode (R3h) isplay Control (R7h) isplay Control 2 (R8h) Frame Cycle Control (RBh) 6 82 RGB Input Interface Control (RCh) 6 82 Oscillator Control (RFh) Power Control (Rh) Power Control 2 (Rh) 64 Page 2 of Version: 22

3 82 Power Control 3 (R2h) Power Control 4 (Rh) Power Control 5 (Rh) VCI Recycling (R5h) RAM Address Set (R2h, R2h) Write ata to GRAM (R22h) Read ata from GRAM (R22h) Software Reset (R28h) Gate Scan Control (R3h) Vertical Scroll Control (R3h, R32h) Vertical Scroll Control (R33h) Partial Screen riving Position (R34h, R35h) Horizontal and Vertical RAM Address Position (R36h/R37h, R38h/R39h) Gamma Control (R5h ~ R59h) NV Memory ata Programming (R6h) NV Memory Control (R6h) NV Memory Status (R62h) NV memory Protection Key (R63h) I Code (R65h) 76 9 NV Memory Programming Flow 77 GRAM Address Map & Read/Write 78 Window Address Function 82 2 Gamma Correction 83 Application Configuration of Power Supply Circuit 2 isplay ON/OFF Sequence 2 3 Standby and Sleep Mode 4 Power Supply Configuration 4 5 Voltage Generation 5 Electrical Characteristics 6 Absolute Maximum Ratings 6 2 C Characteristics 7 3 Clock Characteristics 7 4 Reset Timing Characteristics 7 5 LC river Output Characteristics 8 6 AC Characteristics 8 6 i8-system Interface Timing Characteristics 8 62 M68-System Interface Timing Characteristics 63 Serial ata Transfer Interface Timing Characteristics 64 RGB Interface Timing Characteristics 2 Page 3 of Version: 22

4 5 Revision History Page 4 of Version: 22

5 Figures FIGURE SYSTEM INTERFACE AN RGB INTERFACE CONNECTION 24 FIGURE2 8-BIT SYSTEM INTERFACE ATA FORMAT 25 FIGURE3 6-BIT SYSTEM INTERFACE ATA FORMAT 26 FIGURE4 9-BIT SYSTEM INTERFACE ATA FORMAT 27 FIGURE5 8-BIT SYSTEM INTERFACE ATA FORMAT 28 FIGURE6 ATA TRANSFER SYNCHRONIZATION IN 8/9-BIT SYSTEM INTERFACE 29 FIGURE7 ATA FORMAT OF SPI INTERFACE 3 FIGURE8 ATA TRANSMISSION THROUGH SERIAL PERIPHERAL INTERFACE (SPI) 32 FIGURE9 ATA TRANSMISSION THROUGH SERIAL PERIPHERAL INTERFACE (SPI), TRI= AN FM= ) 33 FIGURE RGB INTERFACE ATA FORMAT 34 Page 5 of Version: 22

6 Introduction a-si TFT LC Single Chip river is a 262,4-color one-chip SoC driver for a-tft liquid crystal display with resolution of 76RGBx22 dots, comprising a 528-channel source driver, a 22-channel gate driver, 872 bytes RAM for graphic data of 76RGBx22 dots, and power supply circuit has four kinds of system interfaces which are i8/m68-system MPU interface (8-/9-/6-/8-bit bus width), serial data transfer interface (SPI) and RGB 6-/6-/8-bit interface (OTCLK, VSYNC, HSYNC, ENABLE, [7:]) In RGB interface, the combined use of high-speed RAM write function and widow address function enables to display a moving picture at a position specified by a user and still pictures in other areas on the screen simultaneously, which makes it possible to transfer display the refresh data only to minimize data transfers and power consumption can operate with low I/O interface power supply up to 65V, with an incorporated voltage follower circuit to generate voltage levels for driving an LC The also supports a function to display in 8 colors and a standby mode, allowing for precise power control by software These features make the an ideal LC driver for medium or small size portable products such as digital cellular phones or small PA, where long battery life is a major concern 2 Features Single chip solution for a liquid crystal QCIF+ TFT LC display 76RGBx22-dot resolution capable of graphics display in 262,4 color Incorporate 528-channel source driver and 22-channel gate driver Internal 87,2 bytes graphic RAM High-speed RAM burst write function System interfaces i8 system interface with 8-/ 9-/6-/8-bit bus width M68 system interface with 8-/ 9-/6-/8-bit bus width Serial Peripheral Interface (SPI) RGB interface with 8-/6-/8-bit bus width (VSYNC, HSYNC, OTCLK, ENABLE, [7:]) n-line liquid crystal AC drive: invert polarity at an interval of arbitrarily n lines (n: ~ 64) Internal oscillator and hardware reset Reversible source/gate driver shift direction Window address function to specify a rectangular area for internal GRAM access Bit operation function for facilitating graphics data processing Bit-unit write data mask function Pixel-unit logical/conditional write function Abundant functions for color display control γ-correction function enabling display in 262,4 colors Line-unit vertical scrolling function Partial drive function, enabling partially driving an LC panel at positions specified by user Page 6 of Version: 22

7 Incorporate step-up circuits for stepping up a liquid crystal drive voltage level up to 6 times (x6) Power saving functions 8-color mode standby mode sleep mode Low -power consumption architecture Low operating power supplies: IOVcc (V3) = 65 ~ 33 V (interface I/O) Vci = 25 ~ 33 V Low voltage drive: VH (AV) = 45 ~ 55 V Page 7 of Version: 22

8 3 Block iagram a-si TFT LC Single Chip river IOVCC IM[3:] nreset ncs nwr nr RS [7:] SI SO SCL ENABLE HSYNC VSYNC MPU I/F 8-bit 6-bit 9-bit 8-bit SPI I/F RGB I/F 8-bit 6-bit 6-bit 8 8 Index Register (IR) 7 Control Register (CR) Graphics Operation 8 Address Counter (AC) V63 ~ LC Source river S[528:] OTCLK TEST_MOE[2:] TEST_MUX[2:] TEST_CSN[:] VSYNC I/F 8 Read Latch 72 Write Latch 72 Grayscale Reference Voltage VREGOUT VGS VCC V RV GN Regulator Graphics RAM (GRAM) M FLM CL RC-OSC Timing Controller LC Gate river G[22:] VCI VCI GN Charge-pump Power Circuit VCOM Generator VCOM CP CM VH C2P C2M C2P C2M C22P C22M VGH VGL VCL C3P C3M VCOMR VCOMH VCOML Page 8 of Version: 22

9 4 Pin escriptions Pin Name I/O Type escriptions Input Interface Select the MPU system interface mode IM3 IM2 IM IM MPU-Interface Mode Pin in use M68-system 6-bit interface [7:], [8:] M68-system 8-bit interface [7:] IM3, IM2, IM, IM/I I IOVcc i8-system 6-bit interface [7:], [8:] i8-system 8-bit interface [7:] I Serial Peripheral Interface (SPI) SI, SO Setting invalid M68-system 8-bit interface [7:] M68-system 9-bit interface [7:9] i8-system 8-bit interface [7:] i8-system 9-bit interface [7:9] Setting invalid When the serial peripheral interface is selected, IM pin is used for the device code I setting A chip select signal ncs I MPU IOVcc Low: the is selected and accessible High: the is not selected and not accessible Fix to IOVCC level when not in use A register select signal RS I MPU IOVcc Low: select an index or status register High: select a control register Fix to GN level when not in use RW_nWR /SCL I MPU IOVcc In 68-system mode, this is used to select operation, read or write (RW) In 8-system mode, this serves as a write strobe signal (nwr) In SPI mode, it serves as a synchronous clock (SCL) E_nR I MPU IOVcc In 68-system mode, this serves as write/read enable strobe (E) In 8-system mode, this serves as a read strobe signal (nr) Must be fixed to GN level when SPI mode nreset I MPU IOVcc A reset pin Initializes the with a low input Be sure to execute a power-on reset after supplying power 8-bit parallel bi-directional data bus for MPU system interface mode [7:] I/O MPU IOVcc Serves as an input data bus for MPU I/F 8-bit I/F: [7:] is used 9-bit I/F: [7:9] is used 6-bit I/F: [7:] and [8:] is used 8-bit I/F: [7:] is used Page 9 of Version: 22

10 Pin Name I/O Type escriptions Serves as an input data bus for RGB I/F 6-bit interface: [7:2] 6-bit interface: {[7:], [:]} 8-bit interface: [7:] Unused pins must be fixed GN level Serial data input (SI) pin in serial interface operation The data is SI I MPU IOVcc latched on the rising edge of the SCL signal Fix to GN level when not in use Serial data output (SO) pin in serial interface operation The data is SO O MPU IOVcc outputted on the falling edge of the SCL signal When the SPI interface is not used, please let SO as floating A dot clock signal OTCLK I MPU IOVcc PL = : Input data on the rising edge of OTCLK PL = : Input data on the falling edge of OTCLK Fix to GN level when not in use A frame synchronizing signal VSYNC I MPU IOVcc VSPL = : Active low VSPL = : Active high Fix to GN level when not in use A line synchronizing signal HSYNC I MPU IOVcc HSPL = : Active low HSPL = : Active high Fix to GN level when not in use A data ENEABLE signal in RGB interface mode ENABLE I MPU IOVcc Low: Select (access enabled) High: Not select (access inhibited) The EPL bit inverts the polarity of the ENABLE signal Fix to GN level when not in use LC riving signals S528~S O LC Source output voltage signals applied to liquid crystal To change the shift direction of signal outputs, use the SS bit SS =, the data in the RAM address h is output from S SS =, the data in the RAM address h is output from S528 S, S4, S7, display red (R), S2, S5, S8, display green (G), and S3, S6, S9, display blue (B) (SS = ) Page of Version: 22

11 Pin Name I/O Type escriptions G22~G O LC TFT VCOM O common electrode Gate line output signals VGH: the level selecting gate lines VGL: the level not selecting gate lines A supply voltage to the common electrode of TFT panel VCOM is AC voltage alternating signal between the VCOMH and VCOML levels Charge-pump and Regulator Circuit VCOMH O Stabilizing The high level of VCOM AC voltage Connect to a stabilizing capacitor capacitor The low level of VCOM AC voltage Adjust the VCOML level with the VCOML O Stabilizing capacitor Variable VCOMR I resistor or open CP, CM Step-up - C2P, C2M capacitor C2P, C2M Step-up - C22P, C22M capacitor C3P, C3M - Step-up capacitor Stabilizing VH O capacitor, VH Stabilizing VGH O capacitor, VGH Stabilizing VGL O capacitor, VGL VV bits Connect to a stabilizing capacitor To fix the VCOML level to GN and set VCOMG = In this case, capacitor connection is not necessary A reference level to generate the VCOMH level either with an externally connected variable resistor or by setting the register of the When using a variable resistor, halt the internal VCOMH adjusting circuit by setting the register and place the resister between VREGOUT and GN When generating the VCOMH level by setting the register, leave this pin open Connect the charge-pumping capacitor for generating AV level Connect the charge-pumping capacitor for generating VGH, VGL level Connect the charge-pumping capacitor for generating VCL level An output voltage from the step-up circuit, twice the Vci level Place a stabilizing capacitor between GN Place a shottkey diode between Vci and VH See Configurations of Power supply circuit VH = 45 ~ 55V An output voltage from the step-up circuit 2, 4 ~ 6 times the Vci level The step-up rate is set with the BT bits Place a stabilizing capacitor between GN Place a shottkey diode between Vci See Configurations of Power supply circuit VGH = max 65V An output voltage from the step-up circuit 2, -3 ~ -5 times the Vci level The step-up rate is set with the BT bits Place a stabilizing capacitor between GN Place a shottkey diode between Vci See Configurations of Power supply circuit VGL = min 65V VCL O Stabilizing An output voltage from the step-up circuit 2, times the Vci level Page of Version: 22

12 Pin Name I/O Type escriptions capacitor, Connect to a stabilizing capacitor VCLC = ~ 33V VCL A voltage level of VH-GN, generated from the reference level of Stabilizing Vci-GN according to the rate set with the VRH[3:] bits VREGOUT VREGOUT (GV) I/O capacitor or power is () a source driver grayscale reference voltage VH, (2) a VCOMH level reference voltage, and (3) a VCOM amplitude reference voltage supply Connect to a stabilizing capacitor VREGOUT = 3 ~ (VH 5)V VGS I GN or external resistor A reference level for the grayscale voltage generating circuit The VGS level can be changed by connecting to an external resistor VREF I/O Stabilizing capacitor Reference voltage for generating GV voltage Generated power output pin for source driver block AV (VH) P Output voltage of st booster circuit ( =2 x VCI) Input voltage to 2 nd booster circuit This pin needs to connect a capacitor for storage function Power Pads Vci I Power supply A supply voltage to the analog circuit Connect to an external power supply of 25 ~ 33V An internal reference voltage for the step-up circuit Stabilizing The amplitude between Vci and GN is determined by the VC[2:] Vci O capacitor bits Vci Vci must be set so that the output voltages VH, VGH, VGL are generated within the respective setting ranges IOVCC (V3) I Power supply A supply voltage to the interface pins (IOVcc = 65 ~ 33V) AVSS (GN) P - GN for analog circuits VSSC (GN) P - GN for booster circuits VSS (GN) P - GN for logic circuits RV P Stabilizing Capacitor Voltage regulator output for V Connect to V pad for supplying power Connect a capacitor for stabilization Power supply for memory and internal logic circuit V P RV Connect this pin to regulated voltage output RV o not apply any external power to this pin over 8V Test Pads CL O - Output pins used only for test purpose at vendor-side In normal operation, leave this pin open Page 2 of Version: 22

13 Pin Name I/O Type escriptions Tearing effect output pin to synchronize MCU to frame writing, activated by FLM O - S/W command When this pin is not activated, this pin is low If not used, open this pin M O - TEST_MOE[2:] I - Output pins used only for test purpose at vendor-side In normal operation, leave this pin open Input pins used only for test purpose In normal operation, connect this pin to VSS or IOVCC Input pins used only for test purpose TEST_MUX[2] I - This pin is internal pull low In normal operation, please connect this pin to GN or leave this pin as open TEST_MUX[:] I - TEST_A I - Input pins used only for test purpose In normal operation, connect this pin to VSS or IOVCC Input pins used only for test purpose In normal operation, connect this pin to VSS or IOVCC Contact - - Contact resistance measurement pin EXCLK I - EN_EXCLK I - Test pin In normal operation, connect this pin to VSS or IOVCC Test pin In normal operation, connect this pin to VSS or IOVCC Liquid crystal power supply specifications Table No Item escription TFT data lines 528 pins (76 x RGB) 2 TFT gate lines 22 pins 3 TFT display s capacitor structure Cst structure only (Common VCOM) S ~ S528 V ~ V63 grayscales Liquid crystal G ~ G22 VGH - VGL 4 drive output VCOMH - VCOML: Amplitude = electronic volumes VCOM VCOMH=VCOMR: Adjusted with an external resistor 5 Input voltage IOVcc 65V ~ 33V Vci 25V ~ 33V VH Vci x 2 6 Internal step-up circuits VGH Vci x 4, x 5, x 6 VGL Vci x -3, x -4, x -5 VCL Vci x - Page of Version: 22

14 a-si TFT LC Single Chip river 5 Pad Arrangement and Coordination Chip Size: 88um x 7um 5um 5um Chip thickness : 4 um (typ) Pad Location: Pad Center Coordinate Origin: Chip Center Au bump height: um 5um Alignment Mark-Left 5um 5um 25um 5um (-68525, 2575) 25um 25um 5um Alignment Mark-Right 5um 25um 5um 5um (68525, 2575) 25um 5um 25um 5um 5um 25um 25um 25um 5um 5um 25um 25um 25um 5um Face Up (Bump View) UMMY UMMY2 VCOM VCOM VCOM VCOM UMMY3 VGH VGH VGH VGH VGH UMMY4 VGL VGL VGL VGL VGL UMMY5 C22P C22P C22P C22M C22M C22M C2P C2P C2P C2M C2M C2M UMMY6 UMMY7 VSSC VSSC VSSC VSSC VSSC VSSC VSSC VSSC VSSC VSSC VCI VCI VCI VCI VCI VCI CP CP CP CP CP CP CP CP CM CM CM CM CM CM CM CM C2P C2P C2P C2P C2P C2P C2M C2M C2M C2M C2M C2M C3P C3P C3P C3P C3P C3M C3M C3M C3M C3M AV AV AV AV AV AV AV AV VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCL VCL VCL VCL VCL UMMY8 RS CSB VSYNC HSYNC OTCLK ENABLE RESETB SI E_R RW_WRB [7] [6] [5] [] [] [2] [] [] [9] [8] [7] [6] [5] [4] [3] [2] [] [] IM[3] IM[2] IM[] IM[] SO M FLM CL TEST_MOE[2] TEST_MOE[] TEST_MOE[] TEST_MUX[2] TEST_MUX[] TEST_MUX[] TEST_A EN_EXCLK EXCLK AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VGS VGS RV RV RV RV RV RV V V V V V V V3 V3 V3 V3 V3 V3 UMMY9 VREF GVO GVO GVO GVO VCOMH VCOMH VCOML VCOML VCOMR CONTACT CONTACT UMMY VCOM VCOM VCOM VCOM UMMY UMMY2 Chip Center X Y 6um UMMY37 UMMY36 UMMY35 UMMY34 G G3 G5 G7 G9 G G27 G29 G2 G2 G25 G27 G29 UMMY33 UMMY32 UMMY3 UMMY3 UMMY29 UMMY28 UMMY27 UMMY26 S S2 S3 S4 S5 S6 S7 S8 S9 S253 S254 S255 S256 S257 S258 S259 S26 S26 S262 S263 S264 S265 S266 S267 S268 S269 S27 S27 S272 S273 S274 S275 S276 S52 S52 S522 S523 S524 S525 S526 S527 S528 UMMY25 UMMY24 UMMY23 UMMY22 UMMY2 UMMY2 UMMY9 UMMY8 UMMY7 G22 G28 G26 G2 G G2 G G8 G6 G4 G2 UMMY6 UMMY5 UMMY UMMY Page of Version: 22

15 No Name X Y No Name X Y No Name X Y No Name X Y No Name X Y UMMY CP VCI TEST_MUX<2> GVO UMMY CP VCI TEST_MUX<> VCOMH VCOM CP VCI TEST_MUX<> VCOMH VCOM CP VCI TEST_A VCOML VCOM CP VCI EN_EXCLK VCOML VCOM CP VCL EXCLK VCOMR UMMY CP VCL AVSS CONTACT VGH CM VCL AVSS CONTACT VGH CM VCL AVSS UMMY VGH CM VCL AVSS VCOM VGH CM UMMY AVSS VCOM VGH CM RS AVSS VCOM UMMY CM CSB AVSS VCOM VGL CM VSYNC AVSS UMMY VGL CM HSYNC AVSS UMMY VGL C2P OTCLK VSS UMMY VGL C2P ENABLE VSS UMMY VGL C2P RESETB VSS UMMY UMMY C2P SI VSS UMMY C22P C2P E_R VSS G<2> C22P C2P RW_WRB VSS G<4> C22P C2M <7> VSS G<6> C22M C2M <6> VSS G<8> C22M C2M <5> VSS G<> C22M C2M <> VSS G<2> C2P C2M <> VGS G<> C2P C2M <2> VGS G<6> C2P C3P <> RV G<8> C2M C3P <> RV G<2> C2M C3P <9> RV G<22> C2M C3P <8> RV G<24> UMMY C3P <7> RV G<26> UMMY C3M <6> RV G<28> VSSC C3M <5> V G<3> VSSC C3M <4> V G<32> VSSC C3M <3> V G<34> VSSC C3M <2> V G<36> VSSC AV <> V G<38> VSSC AV <> V G<4> VSSC AV IM<3> V G<42> VSSC AV IM<2> V G<44> VSSC AV IM<> V G<46> VSSC AV IM<> V G<48> VCI AV SO V G<5> VCI AV M V G<52> VCI VCI FLM UMMY G<54> VCI VCI CL VREF G<56> VCI VCI TEST_MOE<2> GVO G<58> VCI VCI TEST_MOE<> GVO G<6> CP VCI TEST_MOE<> GVO G<62> Page 5 of Version: 22

16 No Name X Y No Name X Y No Name X Y No Name X Y No Name X Y 25 G<64> G<64> S<56> S<466> S<46> G<66> G<66> S<55> S<465> S<45> G<68> G<68> S<5> S<464> S<4> G<7> G<7> S<5> S<463> S<4> G<72> G<72> S<52> S<462> S<42> G<74> G<74> S<5> S<46> S<4> G<76> G<76> S<5> S<46> S<4> G<78> G<78> S<59> S<459> S<49> G<8> G<8> S<58> S<458> S<48> G<82> G<82> S<57> S<457> S<47> G<84> G<84> S<56> S<456> S<46> G<86> G<86> S<55> S<455> S<45> G<88> G<88> S<54> S<454> S<44> G<9> G<9> S<53> S<453> S<43> G<92> G<92> S<52> S<452> S<42> G<94> G<94> S<5> S<45> S<4> G<96> G<96> S<5> S<45> S<4> G<98> G<98> S<499> S<449> S<399> G<> G<2> S<498> S<448> S<398> G<2> G<22> S<497> S<447> S<397> G<4> G<24> S<496> S<446> S<396> G<6> G<26> S<495> S<445> S<395> G<8> G<28> S<494> S<444> S<394> G<> G<2> S<493> S<443> S<393> G<2> G<22> S<492> S<442> S<392> G<> G<2> S<49> S<44> S<39> G<6> G<26> S<49> S<44> S<39> G<8> G<28> S<489> S<439> S<389> G<2> G<22> S<488> S<438> S<388> G<22> UMMY S<487> S<437> S<387> G<24> UMMY S<486> S<436> S<386> G<26> UMMY S<485> S<435> S<385> G<28> UMMY S<484> S<434> S<384> G<> UMMY S<483> S<433> S<383> G<2> UMMY S<482> S<432> S<382> G<4> UMMY S<48> S<43> S<38> G<6> UMMY S<48> S<43> S<38> G<8> UMMY S<479> S<429> S<379> G<> S<528> S<478> S<428> S<378> G<2> S<527> S<477> S<427> S<377> G<4> S<526> S<476> S<426> S<376> G<6> S<525> S<475> S<425> S<375> G<8> S<524> S<474> S<424> S<374> G<5> S<523> S<473> S<423> S<373> G<52> S<522> S<472> S<422> S<372> G<54> S<52> S<47> S<42> S<37> G<56> S<52> S<47> S<42> S<37> G<58> S<59> S<469> S<49> S<369> G<6> S<58> S<468> S<48> S<368> G<62> S<57> S<467> S<47> S<367> Page 6 of Version: 22

17 No Name X Y No Name X Y No Name X Y No Name X Y No Name X Y 5 S<366> S<36> S<266> S<26> S<66> S<365> S<35> S<265> S<25> S<65> S<364> S<3> S<264> S<2> S<64> S<363> S<3> S<263> S<2> S<63> S<362> S<32> S<262> S<22> S<62> S<36> S<3> S<26> S<2> S<6> S<36> S<3> S<26> S<2> S<6> S<359> S<39> S<259> S<29> S<59> S<358> S<38> S<258> S<28> S<58> S<357> S<37> S<257> S<27> S<57> S<356> S<36> S<256> S<26> S<56> S<355> S<35> S<255> S<25> S<55> S<354> S<34> S<254> S<24> S<54> S<353> S<33> S<253> S<23> S<53> S<352> S<32> S<252> S<22> S<52> S<35> S<3> S<25> S<2> S<5> S<35> S<3> S<25> S<2> S<5> S<349> S<299> S<249> S<99> S<9> S<348> S<298> S<248> S<98> S<8> S<347> S<297> S<247> S<97> S<7> S<346> S<296> S<246> S<96> S<6> S<345> S<295> S<245> S<95> S<5> S<344> S<294> S<244> S<94> S<4> S<343> S<293> S<243> S<93> S<3> S<342> S<292> S<242> S<92> S<2> S<34> S<29> S<24> S<9> S<> S<34> S<29> S<24> S<9> S<> S<339> S<289> S<239> S<89> S<9> S<338> S<288> S<238> S<88> S<8> S<337> S<287> S<237> S<87> S<7> S<336> S<286> S<236> S<86> S<6> S<335> S<285> S<235> S<85> S<5> S<334> S<284> S<234> S<84> S<4> S<333> S<283> S<233> S<83> S<3> S<332> S<282> S<232> S<82> S<2> S<33> S<28> S<23> S<8> S<> S<33> S<28> S<23> S<8> S<> S<329> S<279> S<229> S<79> S<29> S<328> S<278> S<228> S<78> S<28> S<327> S<277> S<227> S<77> S<27> S<326> S<276> S<226> S<76> S<26> S<325> S<275> S<225> S<75> S<25> S<324> S<274> S<224> S<74> S<24> S<323> S<273> S<223> S<73> S<23> S<322> S<272> S<222> S<72> S<22> S<32> S<27> S<22> S<7> S<2> S<32> S<27> S<22> S<7> S<2> S<39> S<269> S<29> S<69> S<9> S<38> S<268> S<28> S<68> S<8> S<37> S<267> S<27> S<67> S<7> Page 7 of Version: 22

18 No Name X Y No Name X Y No Name X Y No Name X Y No Name X Y 75 S<6> S<66> S<6> G<67> G<67> S<5> S<65> S<5> G<65> G<65> S<> S<64> S<> G<63> G<63> S<> S<63> S<> G<6> G<6> S<2> S<62> S<2> G<59> G<59> S<> S<6> S<> G<57> G<57> S<> S<6> S<> G<55> G<55> S<9> S<59> S<9> G<53> G<53> S<8> S<58> S<8> G<5> G<5> S<7> S<57> S<7> G<9> G<49> S<6> S<56> S<6> G<7> G<47> S<5> S<55> S<5> G<5> G<45> S<4> S<54> S<4> G<3> G<43> S<> S<53> S<3> G<> G<4> S<2> S<52> S<2> G<9> G<39> S<> S<5> S<> G<7> G<37> S<> S<5> UMMY G<5> G<35> S<99> S<49> UMMY G<3> G<33> S<98> S<48> UMMY G<> G<3> S<97> S<47> UMMY G<29> G<29> S<96> S<46> UMMY G<27> G<27> S<95> S<45> UMMY G<25> G<25> S<94> S<44> UMMY G<23> G<23> S<93> S<43> UMMY G<2> G<2> S<92> S<42> G<29> G<9> G<9> S<9> S<4> G<27> G<7> G<7> S<9> S<4> G<25> G<5> G<5> S<89> S<39> G<2> G<> G<> S<88> S<38> G<2> G<> G<> S<87> S<37> G<29> G<9> G<9> S<86> S<36> G<27> G<7> G<7> S<85> S<35> G<25> G<5> G<5> S<84> S<34> G<23> G<> G<3> S<83> S<33> G<2> G<> G<> S<82> S<32> G<99> G<99> UMMY S<8> S<3> G<97> G<97> UMMY S<8> S<3> G<95> G<95> UMMY S<79> S<29> G<93> G<93> UMMY S<78> S<28> G<9> G<9> Alignment Mark Left S<77> S<27> G<89> G<89> Alignment Mark Right S<76> S<26> G<87> G<87> S<75> S<25> G<85> G<85> S<74> S<24> G<83> G<83> S<73> S<23> G<8> G<8> S<72> S<22> G<79> G<79> S<7> S<2> G<77> G<77> S<7> S<2> G<75> G<75> S<69> S<9> G<73> G<73> S<68> S<8> G<7> G<7> S<67> S<7> G<69> G<69> Page 8 of Version: 22

19 6 6 S ~ S528 G ~ G22 (pin 26 ~ 988) Unit: um 4 4 I/O Pads (pin ~ 25) Pad Pump Pad Pump 56 6/85 Page 9 of Version: 22

20 6 Block escription MPU System Interface supports three system high-speed interfaces: i8/m68-system high-speed interfaces to 8-, 9-, 6-, 8-bit parallel ports and serial peripheral interface (SPI) The interface mode is selected by setting the IM[3:] pins has a 6-bit index register (IR), an 8-bit write-data register (R), and an 8-bit read-data register (RR) The IR is the register to store index information from control registers and the internal GRAM The R is the register to temporarily store data to be written to control registers and the internal GRAM The RR is the register to temporarily store data read from the GRAM ata from the MPU to be written to the internal GRAM are first written to the R and then automatically written to the internal GRAM in internal operation ata are read via the RR from the internal GRAM Therefore, invalid data are read out to the data bus when the read the first data from the internal GRAM Valid data are read out after the performs the second read operation Registers are written consecutively as the register execution time except starting oscillator takes clock cycle Registers selection by system interface (8-/9-/6-/8-bit bus width) I8 M68 Function RS nwr nr E RW Write an index to IR register Read an internal status Write to control registers or the internal GRAM by R register Read from the internal GRAM by RR register Registers selection by the SPI system interface Function R/W RS Write an index to IR register Read an internal status Write to control registers or the internal GRAM by R register Read from the internal GRAM by RR register Parallel RGB Interface supports the RGB interface as the external interface for displaying a moving picture When the RGB interface is selected, display operations are synchronized with externally supplied signals, VSYNC, HSYNC, and OTCLK In RGB interface mode, data (7-) are written in synchronization with these signals according to the polarity of enable signal (ENABLE) to prevent flicker on display while updating display data In VSYNC interface mode, the display operation is synchronized with the internal clock except frame synchronization, where the operation is synchronized with the VSYNC signal isplay data are written to the internal GRAM via the system interface In this case, there are constraints in speed and method in writing data to the internal RAM For details, see the External isplay Interface section The allows for switching between the external display interface and the system interface by instruction so that the optimum interface is Page 2 of Version: 22

21 selected for the kind of picture to be displayed on the screen (still and/or moving picture(s)) The RGB interface, by writing all display data to the internal RAM, allows for transferring data only when updating the frames of a moving picture, contributing to low power requirement for moving picture display Bit Operation The supports a write data mask function for selectively writing data to the internal RAM in units of bits and a logical/compare operation to write data to the GRAM only when a condition is met as a result of comparing the data and the compare register bits For details, see Graphics Operation Functions Address Counter (AC) The address counter (AC) gives an address to the internal GRAM When the index of the register for setting a RAM address in the AC is written to the IR, the address information is sent from the IR to the AC As writing data to the internal GRAM, the address in the AC is automatically updated plus or minus The window address function enables writing data only in the rectangular area arbitrarily set by users on the GRAM Graphics RAM (GRAM) GRAM is graphics RAM storing bit-pattern data of 87,2 (76 x 22x 8/8) bytes, using 8 bits for each pixel Grayscale Voltage Generating Circuit The grayscale voltage generating circuit generates a liquid crystal drive voltage according to grayscale data set in the γ-correction register to display in 262,4 colors For details, see the γ-correction Register section Timing Controller The timing generator generates a timing signal for operation of internal circuits such as the internal GRAM The timing for the display operation such as RAM read operation and the timing for the internal operation such as access from the MPU are generated in the way not to interfere each other Oscillator (OSC) generates RC oscillation with an external oscillation resistor placed between the OSC and OSC2 pins The oscillation frequency is changed according to the value of an external resistor Adjust the oscillation frequency in accordance to the operating voltage or the frame frequency An operating clock can be input externally uring standby mode, RC oscillation is halted to reduce power consumption For details, see Oscillator LC river Circuit The LC driver circuit of consists of a 528-output source driver (S ~ S528) and a 22-output gate driver (G~G22) isplay pattern data are latched when the 528th bit data are input The latched data control the source driver and generate a drive waveform The gate driver for scanning gate lines outputs either VGH Page 2 of Version: 22

22 or VGL level The shift direction of 528-bit source outputs from the source driver is set with the SS bit and the shift direction of gate outputs from the gate driver is set with the GS bit The scan mode by the gate driver is set with the SM bit These bits allow setting an appropriate scan method for an LC module LC river Power Supply Circuit The LC drive power supply circuit generates the voltage levels VREGOUT, VGH, VGL and Vcom for driving an LC Page 22 of Version: 22

23 7 System Interface 7 Interface Specifications has the system interface to read/write the control registers and display graphics memory (GRAM), and the RGB Input Interface for displaying a moving picture User can select an optimum interface to display the moving or still picture with efficient data transfer All display data are stored in the GRAM to reduce the data transfer efforts and only the updating data is necessary to be transferred User can only update a sub-range of GRAM by using the window address function also has the RGB interface to transfer the display data without flicker the moving picture on the screen In RGB interface mode, the display data is written into the GRAM through the control signals of ENABLE, VSYNC, HSYNC, OTCLK and data bus [7:] operates in one of the following 4 modes The display mode can be switched by the control register When switching from one mode to another, refer to the sequences mentioned in the sections of RGB interfaces Operation Mode Internal operating clock only (isplaying still pictures) RGB interface () (isplaying moving pictures) RGB interface (2) (Rewriting still pictures while displaying moving pictures) RAM Access Setting (RM) System interface (RM = ) RGB interface (RM = ) System interface (RM = ) isplay Operation Mode (M[:]) Internal operating clock (M[:] = ) RGB interface (M[:] = ) RGB interface (M[:] = ) Note ) Registers are set only via the system interface Note 2) The RGB-I/F is not available simultaneously Page 23 of Version: 22

24 System System Interface 8/6/6 ncs RS nwr nr [7:] LC IC RGB Interface ENABLE VSYNC HSYNC OTCLK Figure System Interface and RGB Interface connection 72 Input Interfaces The following are the system interfaces available with the The interface is selected by setting the IM[3:] pins The system interface is used for setting instructions and RAM access IM3 IM2 IM IM/I Interface Mode Pin M68-system 6-bit interface [7:], [8:] M68-system 8-bit interface [7:] i8-system 6-bit interface [7:], [8:] i8-system 8-bit interface [7:] I Serial Peripheral Interface (SPI) SI, SO ([:]) Setting invalid M68-system8-bit interface [7:] M68-system 9-bit interface [7:9] i8-system8-bit interface [7:] i8-system 9-bit interface [7:9] Setting invalid Page 24 of Version: 22

25 72 i8/8-bit System Interface The i8/8-bit system interface is selected by setting the IM[3:] as levels System ncs A2 nwr nr [3:] 8 ncs RS nwr nr [7:] 8-bit System Interface (262K colors) TRI=, FM[:]= Input ata Write ata Register GRAM ata & RGB Mapping R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B Figure2 8-bit System Interface ata Format Page 25 of Version: 22

26 722 i8/6-bit System Interface The i8/6-bit system interface is selected by setting the IM[3:] as levels System ncs A nwr nr [5:] 6 ncs RS nwr nr [7:], [8:] 6-bit System Interface (65K colors) TRI=, FM[:]= Input ata Write ata Register GRAM ata & RGB Mapping R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B 6-bit System Interface MSB Mode (262K colors, 2 Transfers/pixel) TRI= ", FM[:]= " Input ata st Transfer 2 nd Transfer Write ata Register GRAM ata & RGB Mapping R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B 6-bit System Interface LSB Mode (262K colors, 2 Transfers/pixel) TRI= ", FM[:]= " Input ata st Transfer nd Transfer Write ata Register GRAM ata & RGB Mapping R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B Figure3 6-bit System Interface ata Format Page 26 of Version: 22

27 723 i8/9-bit System Interface The i8/9-bit system interface is selected by setting the IM[3:] as and the 7~9 pins are used to transfer the data When writing the 6-bit register, the data is divided into upper byte (8 bits and LSB is not used) lower byte and the upper byte is transferred first The display data is also divided in upper byte (9 bits) and lower byte, and the upper byte is transferred first The unused [8:] pins must be tied to ground System ncs A nwr nr [8:] 9 ncs RS nwr nr [7:9] 9-bit System Interface (262K colors) TRI=, FM[:]= Input ata st Transfer (Upper bits) nd Transfer (Lower bits) 2 9 Write ata Register GRAM ata & RGB Mapping R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B Figure4 9-bit System Interface ata Format 724 i8/8-bit System Interface The i8/8-bit system interface is selected by setting the IM[3:] as and the 7~ pins are used to transfer the data When writing the 6-bit register, the data is divided into upper byte (8 bits and LSB is not used) lower byte and the upper byte is transferred first The display data is also divided in upper byte (8 bits) and lower byte, and the upper byte is transferred first The written data is expanded into 8 bits internally (see the figure below) and then written into GRAM The unused [9:] pins must be tied to ground Page 27 of Version: 22

28 8-bit System Interface (65K colors) TRI=, FM[:]= Input ata 7 6 st Transfer (Upper bits) nd Transfer (Lower bits) 5 2 Write ata Register GRAM ata & RGB Mapping R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B 8-bit System Interface (496 colors) TRI=, FM[:]= Input ata Write ata Register GRAM ata & RGB Mapping R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B 8-bit System Interface (262K colors) TRI=, FM[:]= Input ata 7 6 st Transfer nd Transfer rd Transfer 5 2 Write ata Register GRAM ata & RGB Mapping R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B 8-bit System Interface (65K colors) TRI=, FM[:]= Input ata 7 6 st Transfer nd Transfer rd Transfer 5 2 Write ata Register GRAM ata & RGB Mapping R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B Figure5 8-bit System Interface ata Format Page 28 of Version: 22

29 ata transfer synchronization in 8/9-bit bus interface mode supports a data transfer synchronization function to reset upper and lower counters which count the transfers umner of upper and lower byte in 8/9-bit interface mode If a mismatch arises in then numbers of transfers between the upper and lower byte counters due to noise and so on, the h register is written 4 times consecutively to reset the upper and lower counters so that data transfer will restart with a transfer of upper byte This synchronization function can effectively prevent display error if the upper/lower counters are periodically reset RS R nwr [7:9] Upper/ Lower h h h h Upper Lower 8-/9-bit transfer synchronization Figure6 ata Transfer Synchronization in 8/9-bit System Interface 73 Serial Peripheral Interface (SPI) The Serial Peripheral Interface (SPI) is selected by setting the IM[3:] pins as x level The chip select pin (ncs), the serial transfer clock pin (SCL), the serial data input pin (SI) and the serial data output pin (SO) are used in SPI mode The I pin sets the least significant bit of the identification codethe [7:] pins, which are not used, must be tied to ground The SPI interface operation enables from the falling edge of ncs and ends of data transfer on the rising edge of ncs The start byte is transferred to start the SPI interface and the read/write operation and RS information are also included in the start byte When the start byte is matched, the subsequent data is received by The seventh bit of start byte is RS bit When RS =, either index write operation or status read operation is executed When RS =, either register write operation or RAM read/write operation is executed The eighth bit of the start byte is used to select either read or write operation (R/W bit) ata is written when the R/W bit is and read back when the R/W bit is After receiving the start byte, starts to transfer or receive the data in unit of byte and the data transfer starts from the MSB bit All the registers of the are 6-bit format and receive the first and the second Page 29 of Version: 22

30 byte datat as the upper and the lower eight bits of the 6-bit register respectively In SPI mode, 5 bytes dummy read is necessary and the valid data starts from 6 th byte of read back data Start Byte Format Transferred bits S Start byte format Transfer start evice I code RS R/W I / / Note: I bit is selected by setting the IM/I pin RS and R/W Bit Function RS R/W Function Set an index register Read a status Write a register or GRAM data Read a register or GRAM data Page 3 of Version: 22

31 Serial ata Transfer Interface (65K colors) TRI=, FM[:]= st Transfer (Upper bits) 2 nd Transfer (Lower bits) Input ata Write ata Register GRAM ata RGB mapping R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B Serial ata Transfer Interface (262K colors) TRI=, FM[:]= Input ata st Transfer (Red bits) nd Transfer (Green bits) rd Transfer (Blue bits) Write ata Register GRAM ata RGB mapping R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B Figure7 ata Format of SPI Interface Page 3 of Version: 22

32 (a) Basic data transmission through SPI Start End ncs (Input) SCL (Input) SI (Input) I RS RW Start Byte Index register, registers setting, and GRAM write SO (Output) Status, registers read and GRAM read (b) Consecutive data transmission through SPI Start ncs (Input) SCL (Input) SI (Input) Start Byte Register upper eight bits Register lower eight bits Register 2 upper eight bits Register 2 lower eight bits Note: The first byte after the start byte is always the upper eight bits Register execution time (c) GRAM data read transmission ncs (Input) Start End SCL (Input) SI (Input) Start Byte RS=, RW= SO (Output) ummy read ummy read 2 ummy read 3 ummy read 4 ummy read 5 RAM read upper byte RAM read lower byte Note: Five bytes of invalid dummy data read after the start byte (d) Status/registers read transmission Start ncs (Input) End SCL (Input) SI (Input) SO (Output) Start Byte Register upper eight bits Register lower eight bits Note: One byte of invalid dummy data read after the start byte Figure8 ata transmission through serial peripheral interface (SPI) Page 32 of Version: 22