LCD Controller. RA6963 (Datasheet simple, status:februar 2008, Ver. 1.3) admatec GmbH Elektronische Systeme und Komponenten

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1 + LCD Controller (Datasheet simple, status:februar 2008, Ver. 1.3) RoHS admatec GmbH Elektronische Systeme und Komponenten Wendenstrasse 29 D Hamburg fon +49 (0) fax +49 (0) nternet +

2 1. verview The is a dot matrix LCD Controller which fully compatible with T6963C. t supports various LCD Driver for standard or custom-made LCD module. The built-in a 256-word CG(Character Generator) RM that for ASC, Japanese and numeric display in Text mode. t also supports Graphics mode and mixed display with Text. The supported maximum external display RAM is 64Kbyte and the display Window can be moved freely within the allocated memory range. The has an 8-bit parallel data bus that can be directly connected to an 8080 series MCU. The supports a very broad range of LCD formats by allowing selection of different combinations via a set and combination text-and-graphic modes, and includes various attribute functions. 2. Features Support Display Range: Columns 32, 40, 64, 80 Rows 2, 4, 6, 8, 10, 12, 14, 16, 20, 24, 28, 32 Support bit MCU nterface Built-in 256-word Font RM: Basic ASC Japanese Numeric Support Max. 64Kbyte External Display SRAM Display Mode : Character Graphics and Mixed Mode Font Size : Horizontal 5, 6, 7, 8 Pixels Vertical 8 Pixels Support Bold Font and Reverse Display Support Various LCD Driver Support 1/16 ~1/128 Duty Built-in X tal scillator or Using External Clock Power Supply Range: 3.0~5.5V Package: LQFP-67Pin (RoHS Compliance) 3. Block Diagram A[15:0], D[7:0], FNTSEL MCE, MRW MDS 256-word CGRM Display RAM /F System Configure MD[3:0] FS[1:0] DUAL SDSEL Registers Block Cursor Controller Data Latch TEST[2:1] MCU /F X tal SC Timing Generator SD[7:0], CE,, X1 X2 CDATA, LP, FR, HSCP, C/D,, HALT LSCP, ED, HD, LD RAi TECHNLGY NC. 2/6

3 4. Package DUAL HSCP ED HD CE1 CE0 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 LP CDATA FR CH1 CH2 DSPN VDD SDSEL GND TEST2 TEST1 X1 X RAi TM L2N A/B 07xxN Date Code(Year 2007) MCE MRW D7 D6 D5 VDD D4 D3 D2 D1 D0 HALT MDS MD0 MD1 MD2 MD3 FS0 FS1 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 CE C/D L2NA : LQFP-67 Pin, RoHS Compliance Package, Font-01 L2NB : LQFP-67 Pin, RoHS Compliance Package, Font-02 (Refer to Data Sheet Chapter 6-20) 5.1 MCU nterface 5. Pin Descriptions Pin Name / Description SD[7..0] / Data Bus This is bus for data transfer between MCU and. Read Control is a data read signal. When Low, MCU read data from. Write Control is a data write signal. When Low, MCU write data into. C/ D Command/Data Select or Register Select This is a Data or Command select signal. C/ D = Low = Low High Command Write Status Read Low Data Write Data Read CS Chip Select This s chip enable of. When MCU communicate with, this pin must be Low. RAi TECHNLGY NC. 3/6

4 5.2 LCD Driver nterface Pin Name / Description FR Frame LP Latch Latch pulse for column driver. Shift clock pulse for Row Driver CDATA Synchronous Data Synchronous Data for Row Driver. HSCP Shift Clock Pulse Shift clock pulse for Column Driver in upper area of LCD. HD Data utput Data output for dd Columns in upper area of LCD. ED Data utput SDSEL = High Data output for even columns in both upper and lower area of LCD. SDSEL = Low Data output for columns in both upper and lower area of LCD. DSPN Display n Display n/ff control signal. When HALT or is Low, DSPN output Low (LCD Display ff). 5.3 Memory nterface Pin Name / Description A[15:0] Address utput for External Memory D[7:0] / Data Bus for External Memory MCE Memory Chip Enable MCE = Low Memory Enable. MCE = High Memory Disable. Memory Read/Write Control MRW MRW = Low Memory Write Enable. MRW = High Memory Read Enable. CE 0 LD CE 1 LSCP VDD P Power GND P Ground Memory Chip Enable 0 f DUAL = High Chip enable pin for display memory in the address range 0000~07FFh. f DUAL = Low Serial data output for odd columns in lower area of LCD. Memory Chip Enable 1 f DUAL = High Chip enable pin for display memory in the address range 0800~0FFFh. f DUAL = Low Shift clock output for Column Driver in lower area of LCD. RAi TECHNLGY NC. 4/6

5 5.4 Misc. nterface Pin Name / Description DUAL Scan Select DUAL = Low Dual-Scan Mode. DUAL = High Signal-Scan Mode. MDS MD[1:0] LCD Size Selection ne Screen: DUAL H H H H H H H H MDS L L L L H H H H MD1 H H L L H H L L MD0 H L H L H L H L Lines V-Dots Two Screens: DUAL L L L L L L L L MDS L L L L H H H H MD1 H H L L H H L L MD0 H L H L H L H L Lines V-Dots X1 Crystal scillator nput A crystal oscillator circuit is built in. The oscillation frequency is adjusted according to the display size. f using an external clock, use the X1 pin as the clock input. (X2 open.) External capacitors 15 to 20pF. X2 Crystal scillator utput FS[1:0] Font Selection FS0 H L H L FS1 H H L L Font 5 X 8 6 X 8 7 X 8 8 X 8 MD[3:2] SDSEL HALT Columns Selection MD2 H L H L MD3 H H L L Columns Data Transfer Mode SDSEL = Low Sending data by simple serial mode. SDSEL = High Sending data by odd/even separtion mode. Halt Signal HALT = Low Stop the Clock. HALT = High Normal Mode. RAi TECHNLGY NC. 5/6

6 Reset Signal = Low will be reset. = High Normal mode. built-in a Pull-Hi resistor. TEST [2 :1] Test Pins These are test pins. No need for connection(nc). CH1, CH2 Check Signals CGRM Font Select This pin is used to select the character of CGRM. Refer to Chapter FNTSEL Please note, this pin is only reserved for die base chip only. Refer to complete specification Chapter 7-2. FNTSEL = Low Select CGRM Font 01. FNTSEL = High Select CGRM Font System Application RA66256 SRAM LCD Driver MCU LCD Driver LCD Panel SD0 SD7 8-Bit SD0 SD7 CE C/D 4-Bit CE C/D RA66256 SRAM FS 2-Bit FS1 X-Driver X-Driver X-Driver GND VDD VEE Power Supply Y-Driver x 128 LCD Panel Y-Driver 64 RAi TECHNLGY NC. 6/6