The Processor Pipeline. Chapter 4, Patterson and Hennessy, 4ed. Section 5.3, 5.4: J P Hayes.

Transcription

1 The Processor Pipeline Chapter 4, Patterson and Hennessy, 4ed. Section 5.3, 5.4: J P Hayes.

2 Pipeline

3 A Basic MIPS Implementation Memory-reference instructions Load Word (lw) and Store Word (sw) ALU instructions add, sub, AND, OR and slt Branch on equal (beq)

4 Instruction Fetch Elements

5 Instruction Fetch

6 ALU Operations Elements Addr Data REGISTER FILE Data Write ADD R1, R2, R3

7 ADD R1, R2, R3 ALU Operations Elements

8 ADD R1, R2, R3 ALU Operations Elements

9 LW R1, -8(R2) Loads and Stores Elements

10 Branches Elements BEQ R1, R2, LABEL BEQ R1, R2, -16

11 Branches Elements BEQ R1, R2, LABEL BEQ R1, R2, -16

12 Memory and R-type Instructions

13 LW R1, -8(R2) Memory Instruction Load

14 SW R1, -8(R2) Memory Instruction Store

15 ADD R1, R2, R3 R Type Instruction ADD

16 The MIPS Datapath

17 BEQ R1, R2, -16 The MIPS Datapath BEQ

18 MIPS Datapath and Control Lines

19 Pipeline Stages Instruction Instruction Fetch Fetch (IF) (IF) ID: ID: Instruction Instruction decode/ decode/ Register Register file file read read EX: EX: Execution/ Execution/ Address Address Calculation Calculation MEM: MEM: Memory Memory Access Access WB: WB: Write Write Back Back

20 Pipelined Datapath Instruction Instruction Fetch Fetch (IF) (IF) ID: ID: Instruction Instruction decode/ decode/ Register Register file file read read EX: EX: Execution/ Execution/ Address Address Calculation Calculation MEM: MEM: Memory Memory Access Access WB: WB: Write Write Back Back

21 Pipelined vs. Nonpipelined Implementation

22 Pipelined vs. Nonpipelined Implementation Ratio of total execution times between the two versions for 10^6 instructions? Pipelining increases the instruction throughput opposed to individual instruction execution time. IF ID EX MEM WB

23 Speedup of the Pipeline The speedup of a k stage pipelined processor over an unpipelined processor S k = T unpipelined T pipelined = n k k+(n 1) n: number of instructions in the program. k: number of pipeline stages

24 Efficiency of the Pipeline Percentage of stages accomplishing tasks related to the instruction in execution η= No. of Instructions Instruction Execution Time η= n k+(n 1) n: number of instructions in the program. k: number of pipeline stages

25 Throughput of the Pipeline Number of tasks completed in unit time (one second) w=η f f: frequency of operation

26 Pipeline Hazards Hazard: n. An unavoidable danger or risk, even though often foreseeable. Situations that prevent the next instruction in the instruction stream from being executing during its designated clock cycle Reduce the performance from the ideal speedup gained by pipelining

27 Structural Hazard i1 i2 i3 i4 MEM ID EX MEM WB MEM ID EX MEM WB MEM ID EX MEM WB MEM ID EX MEM WB i5... HAZARD!!! Lack of resources Solution: Increase resources MEM ID EX MEM WB Use of separate Data and Instruction memories in the MIPS pipeline

28 Data Hazard ADD R1, R2, R3 IF ID EX MEM WB SUB R4, R1, R5 IF ID EX smem WB WRONG! Data (input operands) required by the instruction are not ready/available Data dependence RAW, WAR, WAW dependences ADD R1, R2, R3 SUB R2, R4, R5 ADD R1, R2, R3 SUB R1, R4, R5

29 Data Hazard DADD DSUB AND OR XOR R1,R2,R3 R4,R1,R5 R6,R1,R7 R8,R1,R9 R10,R1,R11 Time (clock cycles) DADD IM REG ALU DM REG DSUB IM REG ALU DM REG AND IM REG ALU DM REG OR IM REG ALU DM XOR IM REG ALU

30 Avoiding Data Hazards Forwarding DADD DSUB AND OR XOR R1,R2,R3 R4,R1,R5 R6,R1,R7 R8,R1,R9 R10,R1,R11 Time (clock cycles) DADD IM REG ALU DM REG DSUB IM REG ALU DM REG AND IM REG ALU DM REG OR IM REG ALU DM XOR IM REG ALU

31 Pipeline without Forwarding

32 Pipeline with Forwarding

33 Data Hazard Load Instruction LD DSUB AND OR R1,0(R2) R4,R1,R5 R6,R1,R7 R8,R1,R9 Time (clock cycles) LD IM REG ALU DM REG DSUB IM REG ALU DM REG AND IM REG ALU DM REG OR IM REG ALU DM

34 Data Hazards Stalls LD DSUB AND OR R1,0(R2) R4,R1,R5 R6,R1,R7 R8,R1,R9 Time (clock cycles) LD IM REG ALU DM REG DSUB IM REG ALU ALU DM REG AND IM REG ALU ALU DM OR IM REG ALU ALU

35 Data Hazard Solutions Data Forwarding Instruction Reordering

36 Control Hazard Arise from the pipelining of branches and other instructions that change the PC Also called Branch Hazards

37 Branch Hazards Time (clock cycles) BEQ IF ID EX MEM WB ADD IF ID EX MEM WB Branch Successor Branch Successor + 1 Branch Successor + 2 IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB Assumption: Branch condition evaluation completed in in the the ID ID stage

38 Reducing Pipeline Branch Penalties Freeze the pipeline Predict Taken Predict Untaken Fill Branch Delay Slot Time (clock cycles) i BEQ IF ID EX MEM WB i-1 AND IF ID EX MEM WB i+16 Branch Successor IF ID EX MEM WB i+17 Branch Successor + 1 IF ID EX MEM WB

39 Dynamic Branch Prediction Branch prediction buffers Single bit predictors Change prediction with branch behaviour No. of wrong predictions? BRANCH PREDICTION BUFFER T T T T N T T T T T T T T T T T T Wrong Predictions PC Prediction 0x x x

40 Dynamic Branch Prediction 2-bit predictors 00 0x0100 0x0154 0x0210 Branch Prediction Buffer