LEAD-FREE FEATURES: Rev. 2.0 (Sep 2015) 1 DLP Design, Inc.

Size: px

Start display at page:

Download "LEAD-FREE FEATURES: Rev. 2.0 (Sep 2015) 1 DLP Design, Inc."

Kelly McBride
6 years ago
Views:

0 Interface User I/O Channels: Differential Pairs and Global Clocks.

1 DLP-HS- FPGA-A LEAD-FREE USB - FPGA MODULE (PRELIMINARY) FEATURES: Xilinx XCS00A-FTGC FPGA Micron M x DDR SDRAM Memory Built-In Configuration Loader; Writes the Bit File Directly to SPI Flash via High-Speed USB.0 Interface User I/O Channels: Differential Pairs and Global Clocks. MHz Oscillator MHz DDR Interface Reference Design Provided USB Port Powered or V External Power Barrel Jack USB. and.0 Compatible Interface Small Footprint:.0 x. Inch PCB and Standard 0-Pin, 0.9-Inch DIP Interface Rev..0 (Sep 0) DLP Design, Inc.

2 APPLICATIONS: Rapid Prototyping Educational Tool Industrial/Process Control Data Acquisition/Processing Embedded Processor.0 INTRODUCTION The DLP-HS-FPGA module is a low-cost, compact prototyping tool that can be used for rapid proof of concept or within educational environments. The module is based on the Xilinx Spartan A and Future Technology Devices International s FTH Dual-Channel High-Speed USB IC. The DLP-HS-FPGA provides both the beginner as well as the experienced engineer with a rapid path to developing FPGA-based designs. When combined with the free ISE WebPACK tools from Xilinx, this module is more than sufficient for creating anything from basic logical functions to a highly complex system controller. As a bonus feature, one channel of the dual-channel USB interface is used to load user bit files directly to the SPI Flash no external programmer is required. This represents a savings of as much as $00 in that no additional programming cable is required for configuring the FPGA. All that is needed to load bit files to the DLP-HS-FPGA is a Windows software utility (free with purchase), a Windows PC and a USB cable. The module can also be programmed from within the Xilinx ISE tool environment using a Xilinx programming cable (purchased separately). The DLP-HS-FPGA is fully compatible with the free ISE WebPACK tools from Xilinx. ISE WebPACK offers the ideal development environment for FPGA designs with HDL synthesis and simulation, implementation, device fitting and JTAG programming. The DLP-HS-FPGA has on-board voltage regulators that generate all required power supply voltages from a single -volt source. Power for the module can be taken from either the host USB port or from a user-supplied, external -volt power supply via an onboard standard barrel connector. Connection to user electronics is made via a 0-pin, 0.9-inch wide, industry-standard 0.0 square inch post DIP header on the bottom of the board, and a -pin, 0.0-inch wide top side x header. The bottom side 0-pin header provides access to of the FPGA user input/output pins. The top side header provides access to of the FPGA user input/output pins. The bottom side header mates with a user-supplied standard 0-pin, 0.9-inch spaced DIP socket. The top side header mates with a user-supplied 0.0-inch spaced x connector such as the FFSD--D-xx.xx-0 (xx.xx = cable length) ribbon cable assembly from Samtec. Rev..0 (Sep 0) DLP Design, Inc.

DIP Socket Ribbon Cable Other on-board features include a M x DDR SDRAM memory IC for user projects and both JTAG and SPI Flash interface ports for connection to Xilinx programming tools.

The design was written in VHDL and built using the free Xilinx ISE WebPACK tools.

The SPI Flash is used to store the design s FPGA configuration file.

3 DIP Socket Ribbon Cable Other on-board features include a M x DDR SDRAM memory IC for user projects and both JTAG and SPI Flash interface ports for connection to Xilinx programming tools..0 REFERENCE DESIGN A 0,000-line reference design is available for the Spartan A FPGA on the DLP-HS-FPGA to those who purchase the module. The design was written in VHDL and built using the free Xilinx ISE WebPACK tools. The reference design consists of the following blocks: It contains a USB Interface Block, a User I/0 Block, a DDR SDRAM interface, a Heartbeat Pulse Generator and a Clock Generator. The SPI Flash is used to store the design s FPGA configuration file. The USB interface captures, interprets and returns command and data information sent from the host PC through the FTDI USB interface to the FPGA. Commands include Ping, Return Status, Loopback Data, Set a User I/O Pin High or Low, Read a User I/O Pin, Initialize the DDR SDRAM Memory and Read or Write the DDR SDRAM Memory. (Section explains these in detail.) The User I/O Block controls access to the user I/O pins accessible through the top and bottom side headers. Every one of these pins can be either an input or an output. The User I/O Block can configure these pins as inputs and read their state, or as outputs and drive them high or low. (As a Rev..0 (Sep 0) DLP Design, Inc.

side note, of these user I/O pins can be configured as differential pairs, can be configured as global clock inputs and can be configured as regional clock inputs.

The traces between the DDR SDRAM and FPGA are matched within 0 mils to accommodate reliable data transfer at Mbit/s (clocked at MHz).

4 side note, of these user I/O pins can be configured as differential pairs, can be configured as global clock inputs and can be configured as regional clock inputs.) The DDR SDRAM interface block manages the memory s initialization, the refresh cycle and the read and write access. Read and write access is available in -byte bursts. The traces between the DDR SDRAM and FPGA are matched within 0 mils to accommodate reliable data transfer at Mbit/s (clocked at MHz). The interface creates and aligns the Data Strobes (DQS) based on an external feedback trace that matches two times the trace length between the FPGA and the DDR SDRAM. The Initialization, Read, and Write commands are initiated by the USB interface block and executed by the DDR SDRAM interface block. The Heartbeat Pulse Generator takes the internal system clock and divides it down so that the onboard Heartbeat LED will be turned on and off for a duration of approximately one-half second. The Clock Generator Block receives the.mhz clock and produces both the -MHz clocks required to run the DDR SDRAM memory device and the 00-MHz clock for the remaining internal logic in the FPGA. It also handles reset and lock synchronization between internal DCM blocks. The design occupies the following FPGA resources: More reference designs are planned. Please contact DLP Design with any specific requests..0 FPGA SPECIFICATIONS The FPGA device used on the DLP-HS-FPGA is the Xilinx Spartan A: XCS00A-FTG Rev..0 (Sep 0) DLP Design, Inc.

5 Part Number: XCS00A-FTGC System Gates: 00,000 Equivalent Logic Cells:,0 CLB Array: Rows: Columns: Total CLB s: Total Slices:,9 Total Flip Flops:, Total -Input LUT s:, Distributed RAM Bits: K Block RAM Bits: K Dedicated Multipliers: DCM s: The DLP-HS-FPGA was designed with pin migration in mind for the Xilinx Spartan A family FPGA s using the FTG package. The larger Xilinx Spartan A family FPGA that will work on the current PCB design is the XCS00A. Contact DLP Design for details..0 ABSOLUTE MAXIMUM RATINGS Stresses above those listed here may cause permanent damage to the DLP-HS-FPGA: Operating Temperature: 0-0 C Voltage on Digital Inputs with Respect to Ground: -0.V to +. V Sink/Source Current on Any I/O: ma (using LVTTL as the FPGA I/O standard).0 WARNINGS Unplug from the host PC and power adapter before connecting to I/O on the DLP-HS-FPGA. Isolate the bottom of the board from all conductive surfaces. Observe static precautions to prevent damage to the DLP-HS-FPGA module..0 BITLOADAPP SOFTWARE Windows software is provided for use with the DLP-HS-FPGA that will load an FPGA configuration (*.bit) file directly to the SPI Flash device via the USB interface. This application (illustrated below) will allow the user to erase the flash, verify the erasure and then program and verify the flash: Rev..0 (Sep 0) DLP Design, Inc.

6 .0 JTAG INTERFACE The easiest way to load an FPGA configuration (*.bit) file to the FPGA is to run the BitLoadApp software, then select and program a file from the local hard drive directly to the SPI Flash. Once written to the SPI Flash, the configuration will load to the FPGA and execute. Alternatively, a traditional JTAG header location is provided on the DLP-HS-FPGA giving the user access to the specific pins required by the development tools. (Refer to the schematic contained within this datasheet for details.).0 EEPROM SETUP / MPROG The DLP-HS-FPGA has a dual-channel USB interface to the host PC. Channel A is used exclusively to load an FPGA configuration (*.bit) file to the SPI Flash. This configuration data is automatically transferred to the FPGA when power is applied to the module or when the PROG Pin is driven low and then released by the application software. Channel B is used for communication between the FPGA and host PC at run time. A 9LCB EEPROM connected to the USB interface IC is used to store the setup for the two channels. The parameters stored in the EEPROM include the Vendor ID (VID), Product ID (PID), Serial Number, Description String, driver selection (VCP or DXX) and port type (UART serial or FIFO parallel). As mentioned above, Channel A is used exclusively for loading the FPGA s configuration to the SPI Flash, and Channel B is used for communication between the host PC and the DLP-HS-FPGA. As such, the DXX drivers and FIFO mode must be selected in the EEPROM for Channel A. Channel B must use the FIFO mode, but can use either the VCP or DXX drivers. The VCP drivers make the DLP-HS-FPGA appear as an RS port to the host application. The DXX drivers provide faster throughput, but require working with a *.lib or *.dll library in the host application. The operational modes and other EEPROM selections are written to the EEPROM using the MPROG utility. This utility and its manual are available for download from the bottom of the page at Rev..0 (Sep 0) DLP Design, Inc.

7 9.0 TEST BIT FILE A test file is provided as a download from the DLP Design website that provides rudimentary access to the I/O features of the DLP-HS-FPGA. The following features are provided: Ping Read the High/Low State of the Input-Only Pins Drive I/O Pins High/Low or Read their High/Low State Simple Loopback on Channel B Byte Read/Write Access of Row, Column, and Bank Address in the DDR SDRAM This bit file is available from the DLP-HS-FPGA s download page. The command structure that supports these features is explained in Section. 0.0 USB DRIVERS USB drivers for the following operating systems are available for download from the DLP Design website at Notes: OPERATING SYSTEM SUPPORT Windows Vista, Vista x Mac OSX Windows XP, XP x Mac OS9 Windows Server 00, x Mac OS Windows Server 00, x Linux Windows 000 Windows CE..0. The bit file load utility only runs on the Windows platforms.. The bit file load utility requires the use of USB channel A, and channel A is dedicated to this function.. If you are utilizing the dual-mode drivers from FTDI (CDM.x.x) and you want to use the Virtual COM Port (VCP) drivers, then it may be necessary to disable the DXX drivers first via Device Manager. To do so, right click on the entry under USB Controllers that appears when the DLP-HS-FPGA is connected, select Properties, select the Advanced tab, check the option for Load VCP and click OK. Then unplug and replug the DLP-HS-FPGA, and a COM port should appear in Device Manager under Ports (COM & LPT). Rev..0 (Sep 0) DLP Design, Inc.

8 .0 USING THE DLP-HS-FPGA Select a power source via Header Pins and, and connect the DLP-HS-FPGA to the PC to initiate the loading of USB drivers. The easiest way to do this is to connect Pins and to each other. This will result in operational power being taken from the host PC. Once the drivers are loaded, the DLP-HS-FPGA is ready for use. Simply connect the DLP-HS-FPGA to the PC to initiate the loading of USB drivers. Once the USB drivers are loaded, the DLP-HS-FPGA is ready for use. All commands are issued as multi-byte command packets consisting of at least two bytes. You can either utilize the Test Application available from with the DLP-HS-FPGA (as described in Section ), or you can write your own program in your language of choice. If you are using the VCP drivers, begin by opening the COM port, and send multi-byte commands as shown in Table below. There is no need to set the baud rate because the DLP-HS-FPGA uses a parallel interface between the USB IC and the FPGA. (The Ping Command can be used to locate the correct COM port used for communicating with the DLP-HS-FPGA, or you can look in Device Rev..0 (Sep 0) DLP Design, Inc.

9 Manager to see which port was assigned by Windows.) If you are using the DXX drivers as with the Test Application, no COM port selection is necessary. TABLE Command Packets Command Packet Description Byte Hex Value Return/Comments Ping Issues Ping 0 0x00 Ping Command - 0x will be returned indicating that the DLP-HS-FPGA is found on the selected port Read Version/ Status Loopback Loopback Compliment Read Pin Clear Pin Set Pin Initialize Memory Accesses the internal version/ status registers Returns the data byte received Returns the compliment of data byte received Reads the state of one of the user I/O pins Forces the selected user I/O pin low Forces the selected user I/O pin high Initializes DDR SDRAM 0 0x0 Read Version/Status Registers Command 0xnn Register Address: 0xnn = 0x00 = Board ID (0x = Revision.) 0x0 = FPGA Type ID (0xA = Spartan A) 0x0 = Design Version ID (0x09 = September) 0x0 = Design Version ID (0x0 = Day) 0x0 = Design Version ID (0x09 = Year) 0x0 = Design Version ID (0xA = Version A) 0x0 = DDR Status: 0x00 = Not Initialized 0x0 = Initialized 0 0x0 Loopback Command 0xnn The byte sent to the DLP-HS-FPGA (0xnn) will be returned back 0 0x Loopback Compliment Command 0xnn The byte sent to the DLP-HS-FPGA (0xnn) will be complimented and returned back 0 0x0 Read Pin Command 0x00 0xE The user I/O pin numbers are described in Table. User I/O pin 0xnn is read and returns: 0x00 = User I/O pin 0xnn is low 0x0 = User I/O pin 0xnn is high 0 0x0 Clear Pin Command 0x00 0xE number is returned. The user I/O pin numbers are described in Table. User I/O pin 0xnn is cleared. The specified user I/O 0 0x Set Pin Command 0x00 0xE is returned. The user I/O pin numbers are described in Table. User I/O pin 0xnn is set. The specified user I/O number 0 0x0 The Initialize Memory Command configures the DDR SDRAM for access by the FPGA. The memory cannot be accessed without being initialized. Rev..0 (Sep 0) 9 DLP Design, Inc.

10 Important Note on DDR SDRAM Data Access: DDR SDRAM data accesses using the reference design on the DLP-HS-FPGA module are always performed bytes at a time due to the fact that the device is configured for a burst length of four. What this means is column address bits 0 and only change the order of the read or write bytes, they still refer to the same bytes. Therefore to increment the DDR SDRAM address for consecutive memory locations, the column address must be incremented by. Incrementing the column address by anything less than simply changes the order that the bytes specified by column address 9: are written to the memory, or returned to the user. For example a write to a column starting address of 0, will write to column locations 0,,, and. But if the user then writes to column address, they will actually be writing to column locations,,, and 0, which will overwrite the previous write operation. More details on how the DDR SDRAM column bits and 0 function can be found in figure and table 0 of the Micron MTHM datasheet. For details how the bank, row, and column bits are sent via USB to the memory, refer to the commands below. Memory Read Memory Write Reads bytes from the DDR SDRAM Writes bytes to the DDR SDRAM 0 0xn Reads bytes from the DDR SDRAM starting with the address specified. The command byte is OR d with the Most Significant Row Address Bit (). n = 0 the Most Sig Row Address Bit is low (0x0) n = the Most Sig Row Address Bit is high (0x) 0xah Bits - Middle bits of Row Address to be read from 0xam Bits - Lower bits of Row Address to be read from Bits - Upper bits Column Address to be read from 0xal Bits -: Lower bits of column address to be read from NOTE: refer to text above regarding column bits and 0 (equates to 0xal bits -). Bits -0: Bank Address to be read from NOTE: If the memory has not been initialized, the data returned will be invalid and the command returned will be 0xE indicating the error. 0 0x9n Writes bytes to the DDR SDRAM starting with the address specified. The command byte is OR d with the Most Significant Row Address bit (). n = 0 the Most Sig Row Address bit is low (0x90) n = the most Sig Row Address bit is high (0x9) 0xah Bits - Middle bits of Row Address to be written tp 0xam Bits - Lower bits of Row Address to be written to Bits - Upper bits Column Address to be written to 0xal Bits -: Lower bits of column address to be written to NOTE: refer to text above regarding column bits and 0 (equates to 0xal bits -). Bits -0: Bank Address to be written 0 0xd0 Data Byte 0 written to Address specified 0xd Data Byte written to Address specified + 0xd Data Byte written to Address specified + 0xd Data Byte written to Address specified + Returns the bytes written followed by an echo back of the command and address data sent. NOTE: If the memory has not been initialized, the command returned will be 0xE indicating the error. Rev..0 (Sep 0) 0 DLP Design, Inc.

11 The USER I/O Pin Read/Set/Clear commands I/O number mapping to the physical I/O pins on the DLP-HS-FPGA board are described in the following table: TABLE User I/O I/O Number DLP-HS- XCS00A XCS00A FPGA Pin Pin Bank FPGA Pin Configurations Available 0x00 (0) J Pin D 0 Digital Input, Output, Differential Pair 0+ 0x0 () J Pin C 0 Digital Input, Output, Differential Pair 0-0x0 () J Pin D 0 Digital Input, Output, Differential Pair - 0x0 () J Pin C 0 Digital Input, Output, Differential Pair + 0x0 () J Pin C0 0 Digital Input, Output, Differential Pair +, Global Clock 0x0 () J Pin D9 0 Digital Input, Output, Differential Pair -, Global Clock 0x0 () J Pin C 0 Digital Input, Output, Differential Pair +, Global Clock 0x0 () J Pin 9 D 0 Digital Input, Output, Differential Pair -, Global Clock 0x0 () J Pin 0 A 0 Digital Input, Output, Differential Pair + 0x09 (9) J Pin A 0 Digital Input, Output, Differential Pair - 0x0A (0) J Pin A 0 Digital Input, Output, Differential Pair + 0x0B () J Pin B 0 Digital Input, Output, Differential Pair - 0x0C () J Pin C 0 Digital Input, Output, Differential Pair + 0x0D () J Pin A 0 Digital Input, Output, Differential Pair - 0x0E () J Pin B 0 Digital Input, Output, Differential Pair -, 0x0F () J Pin A 0 Global Clock Digital Input, Output, Differential Pair +, Global Clock 0x0 () J Pin 9 C 0 Digital Input, Output, Differential Pair - 0x () J Pin 0 A 0 Digital Input, Output, Differential Pair + 0x () J Pin B 0 Digital Input, Output, Differential Pair 9-0x (9) J Pin A 0 Digital Input, Output, Differential Pair 9+ 0x (0) J Pin F Digital Input, Output, Differential Pair 0+ 0x () J Pin 9 G Digital Input, Output, Differential Pair 0-0x () J Pin 0 C Digital Input, Output, Differential Pair + 0x () J Pin C Digital Input, Output, Differential Pair - 0x () J Pin E Digital Input, Output, Differential Pair - 0x9 () J Pin D Digital Input, Output, Differential Pair + 0xA () J Pin J Digital Input, Output, Differential Pair - 0xB () J Pin J Digital Input, Output, Differential Pair + 0xC () J Pin H Digital Input, Output, Differential Pair + 0xD (9) J Pin H Digital Input, Output, Differential Pair - 0xE (0) J Pin M Digital Input, Output, Differential Pair - 0xF () J Pin 9 N Digital Input, Output, Differential Pair + 0x0 () J Pin E Digital Input, Output, Differential Pair + 0x () J Pin E Digital Input, Output, Differential Pair - 0x () J Pin H Digital Input, Output, Differential Pair + 0x () J Pin J Digital Input, Output, Differential Pair - 0x () J Pin K Digital Input, Output, Differential Pair -, Rev..0 (Sep 0) DLP Design, Inc.

12 Regional Clock 0x () J Pin K Digital Input, Output, Differential Pair +, Regional Clock 0x () J Pin P Digital Input, Output, Differential Pair 9-0x (9) J Pin N Digital Input, Output, Differential Pair 9+ 0x (0) J Pin 9 T9 Digital Input, Output, Global Clock 0x9 () J Pin B 0 Digital Input, Output 0xA () J Pin A 0 Digital Input, Output 0xB () J Pin B0 0 Digital Input, Output, Differential Pair 0+ 0xC () J Pin A0 0 Digital Input, Output, Differential Pair 0-0xD () J Pin 9 A9 0 Digital Input, Output, Global Clock 0xE () J Pin N Digital Input, Output 0xF () J Pin E 0 Digital Input, Output 0x0 () J Pin C 0 Digital Input, Output 0x (9) J Pin C 0 Digital Input, Output 0x (0) J Pin 9 K Digital Input, Output 0x () J Pin R Digital Input, Output 0x () J Pin A 0 Digital Input, Output 0x () J Pin A 0 Digital Input, Output, Differential Pair + 0x () J Pin B 0 Digital Input, Output, Differential Pair - 0x () J Pin F Digital Input, Output, Differential Pair + 0x () J Pin 0 G Digital Input, Output, Differential Pair - 0x9 () J Pin H Digital Input, Output, Regional Clock 0xA () J Pin J Digital Input, Output, Regional Clock 0xB (9) J Pin L Digital Input, Output 0xC (0) J Pin M Digital Input, Output 0xD () J Pin 0 M Digital Input, Output, Differential Pair + 0xE () J Pin L Digital Input, Output, Differential Pair - SUSPEND J Pin R Force Suspend Mode (when enabled) AWAKE J Pin T Return from Suspend Mode operation +V IN J Pin - - +V input to the DLP-HS-FPGA +V USB J Pin - - +V supplied by host PC USB port +.V OUT J Pin, V supplied by the onboard DLP-HS- J Pin J Pin, J Pin, J Pin, J Pin, J Pin 0, J Pin 0, J Pin - - FPGA regulator after module enumerated Ground Rev..0 (Sep 0) DLP Design, Inc.

.0 USING THE DLP TEST APPLICATION (OPTIONAL) Users can design their own application interface to send USB commands to the DLP-HS-FPGA module or utilize the test application tool available from DLP

13 .0 USING THE DLP TEST APPLICATION (OPTIONAL) Users can design their own application interface to send USB commands to the DLP-HS-FPGA module or utilize the test application tool available from DLP Design. The DLP Test Application is available in a free version for download from the DLP Design website at Using this tool, single- and multi-byte commands can be sent to the DLP-HS-FPGA board. Once installed the test application is used as follows: The commands used to interface to the DLP-HS-FPGA are detailed in Section 0 of this datasheet. Rev..0 (Sep 0) DLP Design, Inc.

14 .0 MECHANICAL DIMENSIONS IN INCHES (MM) (PRELIMINARY) 0. typ (. typ) 0. typ (. typ) 0. typ (. typ) 0. typ (. typ) 0. typ (. typ) 0. typ (. typ) 0.0 typ (. typ). typ (0. typ).9 typ (.9 typ).0 typ (. typ). typ (0. typ).09 typ (. typ) 0. typ (. typ) 0. typ (. typ) 0.09 typ (. typ) 0. typ (.0 typ) Rev..0 (Sep 0) DLP Design, Inc.

15 .0 DISCLAIMER DLP Design, Inc., Neither the whole nor any part of the information contained herein nor the product described in this manual may be adapted or reproduced in any material or electronic form without the prior written consent of the copyright holder. This product and its documentation are supplied on an as-is basis, and no warranty as to their suitability for any particular purpose is either made or implied. DLP Design, Inc. will not accept any claim for damages whatsoever arising as a result of the use or failure of this product. Your statutory rights are not affected. This product or any variant of it is not intended for use in any medical appliance, device or system in which the failure of the product might reasonably be expected to result in personal injury. This document provides preliminary information that may be subject to change without notice..0 CONTACT INFORMATION DLP Design, Inc. 0 Roma Lane Allen, TX 0 Phone: Fax: Sales: sales@dlpdesign.com Support: support@dlpdesign.com Website URL: Rev..0 (Sep 0) DLP Design, Inc.

16 D D C C B B A A Downloading FPGA Code For FPGA configuration via SPI only. PRELIMINARY DLP-HS-FPGA Page v. UPLOAD 00 ma DC:+. to +.0V Bottom side FPGA IO (top view) Top side FPGA IO EEDATA PWREN# EECS PV EESK PV0 USER_IO9_DP9 USER_IO_DN_RC USER_IO_DP USER_IO_DN USER_IO_DN USER_IO_DN9 USER_IO0_GC USER_IO_DP USER_IO_DP USER_IO_DP_RC USER_IO_DN_GC USER_IO_DN_RC USER_IO0_DP0 USER_IO_DN9 USER_IO_DN USER_IO_DP USER_IO_DN USER_IO_DN USER_IO_DP USER_IO0_DP0 USER_IO_DN USER_IO_DN0 USER_IO_DP USER_IO_DP_RC USER_IO_DP USER_IO_DN USER_IO_DN USER_IO9_DP9 USER_IO_DP_GC USER_IO_DN_GC USER_IO_DP USER_IO_DN_GC USER_IO9_DN USER_IO_DP_GC USER_IO_DP USER_IO_DP USER_IO9_DN USER_IO0_DN USER_IO_DP_GC USER_IO_DN0 FTDI_RXF FTDI_D FTDI_D FTDI_D FTDI_TXE FTDI_D FTDI_D0 FTDI_D FTDI_RD FTDI_SI FTDI_WR FTDI_D FTDI_D SPI_MOSI SPI_DIN SPI_CSO_B FPGA_RESET SPI_CLK VPLL VPHY VPLL VPHY PORTVCC VIN FPGA_AWAKE FPGA_SUSPEND PORTVCC VIN USER_IO0_DP USER_IO USER_IO USER_IO USER_IO_DP0 USER_IO_DN0 USER_IO_GC USER_IO USER_IO USER_IO USER_IO9 USER_IO0 USER_IO FPGA_SUSPEND USER_IO_DP USER_IO_DN USER_IO_DP USER_IO_DN USER_IO_RC USER_IO_RC USER_IO9 USER_IO0 USER_IO_DP USER_IO_DN FPGA_AWAKE SPI_PROG V V0 V V V V V V V V0 V V0 CN CN-USB C.0uF/00 C.uF CN DC BARREL JACK D MBR0TG C.uF TP SPARE_ACBUS C.0 C.uF R.K JP PROG Disable C 0.uF R K J CONN PCB x Q IRLML0 R.9K Y MHz FB 0-0- C.uF C.uF R 0K C9 0uF/0V C 0.uF R 0K % R.K C.uF R9 0 U FTHQ VCCIO VCCIO DP EECLK VCCIO VCCIO VCORE VCORE VCORE VPLL VPHY VREGIN DM A BCBUS/PWRSAV#/PWRSAV#/GPIOH BCBUS/-/-/GPIOH BCBUS/-/-/GPIOH BCBUS/RXLED#/SIWUB/GPIOH BCBUS/TXLED#/WR#/GPIOH BCBUS/RDSTB#/RD#/GPIOH BCBUS/WRSTB#/TXE#/GPIOH BCBUS0/TXDEN/RXF#/GPIOH0 ADBUS0/TXD/D0/TCK SK ADBUS/RXD/D/TDI DO ADBUS/RTS#/D/TDO DI ADBUS/CTS#/D/TMS CS ADBUS/DTR#/D/GPIOL0 ADBUS/DSR#/D/GPIOL ADBUS/DCD#/D/GPIOL ADBUS/RI#/D/GPIOL ACBUS0/TXDEN/RXF#/GPIOH0 ACBUS/WRSTB#/TXE#/GPIOH ACBUS/RDSTB#/RD#/GPIOH ACBUS/TXLED#/WR#/GPIOH ACBUS/RXLED#/SIWUA/GPIOH ACBUS/-/CLKOUT/GPIOH ACBUS/-/OE#/GPIOH ACBUS/-/-/GPIOH BDBUS0/TXD/DO/TCK SK BDBUS/RXD/D/TDI DO BDBUS/RTS#/D/TDO DI BDBUS/CTS#/D/TMS CS BDBUS/DTR#/D/GPIOL0 BDBUS/DSR#/D/GPIOL BDBUS/DCD#/D/GPIOL BDBUS/RI#/D/GPIOL OSCO OSCI RESET# REF VREGOUT EECS EEDATA TEST PWREN# SUSPEND# C.uF Q MMBT90L C 0/0 Tant FB 0-0- J CONN HDR x FB 0-0- C.uF D RED C9.uF C9.uF R 0K R 0 C0.uF C pf U 9LC CS SK DIN DOUT VCC NC NC/ORG R TP SPARE_ACBUS C.uF R R K C.uF R 0 C.uF C9 0/0 Tant R 0K C.uF TP SPARE_ACBUS C.uF U NCP0-.V VOUT VIN SENSE VIN EN C pf

17 A T F K C P E M F R B K G J H9 K9 G0 R0 B L E M C P G L A T UF VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT V DDR II parallel terminations.v REGULATOR 00mA Maximum D D VCCAUX VCCAUX VCCAUX VCCAUX G H K G9 J9 K0 F M E L C. uf 00 C9. uf 00 C 0.uF C 0.uF C 0.0uF C 0.0uF C 0.uF C0 0.uF C 0.0uF C 0.0uF C 0.uF C 0.0uF DDR_A DDR_A DDR_A DDR_WEn VTT_0V9 DDR_RFU_A DDR_A DDR_ODT DDR_A VTT_0V9.V REGULATOR.A Maximum DDR_RFU_BA VTT_0V9 DDR_BA DDR_A C C DDR_BA0 DDR_RFU_A R DDR_A 9 C DDR_A 0 uf XCS00A_FT VTT_0V9 0 R DDR_CKE 9.9K % TANT CAT-00JALF 0 Ohm RN CAT-00JALF 0 Ohm RN CAT-00JALF 0 Ohm RN VTT_0V9 DDR_A9 DDR_RFU_A DDR_A DDR_A VTT_0V9 DDR_CASn DDR_A0 DDR_CSn DDR_RASn C.uF 00 U STS0 DFN VIN_SW VIN_A IN SW INHIBIT FB OUT EN BYPASS U TPS9DBVR / SOT- L.uH C 0.0 uf 00 V C. uf 00 R 0 DDR_A0 Q IRLML0 V B 0K % B C. uf V R 0 C 0.uF Use Ceramic caps U LP99 SOIC AVIN PVIN VREF VDDQ VTT SD# VSENSE C uf C 0.uF VREF_0V9_INT VTT_0V9 C 0.uF J Xilinx Parallel Cable Header TDI TDO TMS TCK Y EN VDD OUT FXO-HC-.MHZ SPI_MOSI SPI_DIN SPI_CSO_B SPI_CLK R CLKIN R C0 0.uF 00 R0 00 %. ms ramp up C 0.uF 00 D GREEN J R.K UE JTAG_DIN JTAG_TMS LEDG_DONE JTAG_DOUT JTAG_TCK SPI_PROG A MP0 A XCS00A_FT Traditional JTAG U R.K JTAG_TCK JTAG_DOUT JTAG_DIN JTAG_TMS R9.K R.K R.K C S W HOLD SPI Flash PRELIMINARY DLP-HS-FPGA V. Page VSS VCC B B T B A A TDI TMS DONE TDO TCK PROG_B JP PROG R0.K >Din <Dout

18 D D C C B B A A Suspend powered by Vccaux (.V) Mode 00 = SPI Flash Variant Select = (Fast Read 0x0B) v. Page DLP-HS-FPGA PRELIMINARY HEARTBEAT DDR_DQS DDR_DQSn DDR_CKn DDR_CK DDR_CK DDR_CKn DDR_DQS DDR_DQSn FDBK USER_IO_DP USER_IO_DP USER_IO_DN USER_IO_DP_RC USER_IO_DP USER_IO_DN0 USER_IO_DN USER_IO0_DP0 USER_IO9_DN USER_IO9_DN USER_IO_DP DDR_CKE DDR_CASn DDR_RASn DDR_WEn DDR_CSn DDR_BA DDR_BA0 DDR_A DDR_A DDR_A0 DDR_A9 DDR_A DDR_A DDR_A DDR_A DDR_A DDR_A DDR_A DDR_A DDR_A0 DDR_DQ0 DDR_DQ DDR_DQ DDR_DQ DDR_DQ DDR_DQ DDR_DQ DDR_DQ DDR_ODT DDR_A0 DDR_A DDR_A DDR_DQ0 DDR_DQ DDR_DQ DDR_DQ DDR_DQ DDR_DQ DDR_DQ DDR_DQ DDR_ODT DDR_WEn DDR_CASn DDR_A DDR_CSn DDR_A DDR_A DDR_A DDR_CKE DDR_A DDR_A0 DDR_BA DDR_A DDR_A DDR_A DDR_RASn DDR_BA0 DDR_A9 DDR_RFU_BA DDR_RFU_A DDR_RFU_A DDR_RFU_A DDR_RFU_BA0 DDR_RFU_A VREF_0V9_INT VREF_0V9 VREF_0V9 VREF_0V9 VREF_0V9 DDR_RFU_A DDR_RFU_A VREF_0V9 FPGA_SUSPEND USER_IO_DN_RC USER_IO_DN_RC USER_IO_DP_RC USER_IO_DP USER_IO_DN USER_IO_DP USER_IO_DN USER_IO9_DP9 USER_IO_DP USER_IO0_DN USER_IO_DN9 USER_IO_DN_GC USER_IO_DP_GC USER_IO_DP_GC USER_IO0_DP0 USER_IO_DN0 SPI_MOSI DDR_IDONE FPGA_AWAKE DDR_ERROR CLKIN FPGA_RESET DDR_DVALID LEDR_HEARTB USER_IO_DN USER_IO_DP USER_IO_DN USER_IO_DP SPI_INIT USER_IO_DN USER_IO0_DP USER_IO_DP USER_IO_DN USER_IO_DP_GC USER_IO_DN_GC USER_IO_DP USER_IO_DN SPI_CSO_B USER_IO_DN_GC USER_IO_DN9 USER_IO9_DP9 USER_IO0 USER_IO USER_IO USER_IO_DP0 USER_IO_DN0 USER_IO_GC USER_IO USER_IO USER_IO USER_IO0 USER_IO USER_IO USER_IO_DP USER_IO_DN USER_IO_DP USER_IO_DN USER_IO_RC USER_IO_RC USER_IO9 USER_IO0 DDR_ERROR DDR_DVALID DDR_IDONE USER_IO9 FTDI_D FDTI_D FDTI_D FTDI_D FDTI_WR FTDI_TXE FDTI_D FTDI_SI FDTI_D FTDI_D0 FTDI_RXF FTDI_RD FDTI_D SPI_CLK SPI_DIN VREF_0V9 V V V V TP DDR_ERROR C 0.0uF D GREEN UB XCS00A_FT R N N R P P N K K M M L K M M L L J0 J J J K K K J H0 J E H F F C C D E D D G G F E F G F E G H F G H H H H J N SUSPEND IO_L0P_/HDC IO_L0N_/LDC IO_L0P_/LDC IO_L0N_/LDC0 IO_L0P_/A0 IO_L0N_/A IP_L0P_ IP_L0N_/VREF_ IO_L0P_ IO_L0N_/VREF_ IO_L0P_/A IO_L0N_/A IO_L0P_/A IO_L0N_/A IO_L0P_/A IO_L0N_/A IP_L09P_/VREF_ IP_L09N_ IO_L0P_/A IO_L0N_/A9 IO_LP_/RHCLK0 IO_LN_/RHCLK IO_LP_/RHCLK IO_LN_/TRDY/RHCLK IP_LP_ VCCO_ VCCO_ VCCO_ IP_LN_ IP_LP_/VREF_ IO_LN_/A IO_LP_/A IO_LN_/A IO_LP_/A IO_LN_/A IO_LP_/A0 IP_LN_ IP_LP_/VREF_ IO_L0N_/A9 IO_L0P_/A IO_L9N_/A IO_L9P_/A IO_LN_/A IO_LP_/A IO_LN_/A IO_LP_/A IO_LN_/A IO_LP_/A0 IO_LN_/RHCLK IO_LP_/IRDY/RHCLK IO_LN_/RHCLK IP_LN_ IO_LP_/RHCLK VCCO_ C 0.0uF C9 0.uF C 0.uF C 0.0uF C 0.uF C 0.uF C 0.0uF R 0 JP SUSPEND VIA UNUSED_K VIA UNUSED_J R.K UD XCS00A_FT C C D D D E E F E E G G F G F G G H H H G H H J H J M H D L L M N P R P N K K N M L M L K J J L L K K J J J IO_L0P_ IO_L0N_ IO_L0P_ IO_L0N_ IO_L0P_ IO_L0N_ IP_L0P_ IP_L0N_/VREF_ IO_L0P_ IO_L0N_ IP_L0P_ IP_L0N_/VREF_ IO_L0P_ IO_L0N_ IO_L0P_ IO_L0N_/VREF_ IO_L09P_ IO_L09N_ IO_L0P_ IO_L0N_ IO_LP_/LHCLK0 IO_LN_/LHCLK IO_LP_/LHCLK IO_LN_/IRDY/LHCLK IP_LP_ IP_LN_ VCCO_ VCCO_ VCCO_ IP_LN_/VREF_ IP_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IP_LN_ IP_LP_ IO_L0N_ IO_L0P_ IO_L9N_ IO_L9P_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_/VREF_ IO_LN_/LHCLK IO_LP_/TRDY/LHCLK IO_LN_/LHCLK IO_LP_/LHCLK VCCO_ C 0.uF R 0 R 00 TP DDR_DVALID UC XCS00A_FT N P N R T R T L N P M T R T T N P P N R T M P T N9 P9 R M9 R R R T M P N R T P T L0 N P R T P0 T0 L9 M0 N0 T9 R9 L IO_L0P_/M IO_L0N_/M0 IP_/VREF_ IO_L0P_/M IO_L0N_/CSO_B IO_L0P_/RDWR_B IO_L0N_/VS IP_ IO_L0P_/VS IO_L0N_/VS0 IP_/VREF_ IO_L0P_ IO_L0N_ IO_L0P_/D IO_L0N_/D IO_L0P_ IO_L0N_ IO_L0P_/D IO_L0N_/D IO_L09P_/GCLK IO_L09N_/GCLK IP_/VREF_ IO_L0P_/GCLK IO_L0N_/GCLK IO_LP_/GCLK0 IO_LN_/GCLK VCCO_ VCCO_ VCCO_ VCCO_ IO_L0N_/CCLK IO_L0P_/D0/DIN/MISO IP_/VREF_ IO_L9N_ IO_L9P_ IO_LN_/D IO_LP_/D IO_LN_/D IO_LP_/INIT_B IP_/VREF_ IO_LN_ IO_LP_ IO_LN_/DOUT IO_LP_/AWAKE IO_LN_/MOSI/CSI_B IO_LP_ IP_/VREF_ IO_LN_ IO_LP_ IO_LN_/GCLK IO_LP_/GCLK IP_ C0 0.0uF R C 0.uF C 0.0uF C 0.0uF C. uf 00 C9 0.0uF C0 0.uF R C 0.0uF R 0 C 0.uF R0 00 TP DDR_IDONE C0. uf 00 VIA UNUSED_R C 0.uF C0 0.0uF C 0.uF C 0.uF C 0.uF U9 MTHMBP-E C C D D F G F G G G H H H H J F J J J K K K K F E B A E D D9 B B9 A E9 H9 L A9 C C B D B A C9 D C L K9 J E A E G L L L E F9 B A DQ0 DQ DQ DQ WE CAS RAS CS BA0 BA A0 A0 A A A CK# A A A A A A9 A CKE CK DQS VSS VSS DQ DQ DQ DQ VDD VDD VDD VDD VDDQ VDDQ VDDQ VSSQ VSSQ VSSQ VSSQ VDDQ VSSQ VDDQ A VSS VSS VSSDL DQS# VDDL RFU_BA RFU_A RFU_A RFU_A VREF ODT DM RDSQ#/NU C 0.0uF C. uf 00 C 0.uF R9.K TP U A C 0.uF VIA UNUSED_E0 C 0.uF UA XCS00A_FT D C D B B C D A A B A D0 E0 C A F0 B0 A0 C0 D9 E9 C9 A9 C D B B9 E B D C E B A B A D C A C D F B A E F C A B A F9 IO_L0P_0 IO_L0N_0 IP_0 IO_L0P_0/VREF_0 IO_L0N_0 IO_L0P_0 IO_L0N_0 IO_L0P_0 IO_L0N_0 IO_L0P_0 IO_L0N_0 IO_L0P_0 IO_L0N_0/VREF_0 IO_L0P_0 IO_L0N_0 IP_0 IO_L0P_0 IO_L0N_0 IO_L09P_0/GCLK IO_L09N_0/GCLK IP_0/VREF_0 IO_L0P_0/GCLK IO_L0N_0/GCLK IO_LP_0/GCLK IO_LN_0/GCLK9 VCCO_0 VCCO_0 VCCO_0 VCCO_0 IO_L0N_0/PUDC_B IO_L0P_0/VREF_0 IP_0 IO_L9N_0 IO_L9P_0 IO_LN_0 IO_LP_0 IP_0 IO_LN_0 IO_LP_0 IO_LN_0 IO_LP_0 IP_0 IO_LN_0 IO_LP_0 IO_LN_0/VREF_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LN_0/GCLK IO_LP_0/GCLK0 IP_0 C 0.uF R

LEAD FREE FEATURES: Rev. 1.7 (May 2011) 1 DLP Design, Inc.

LEAD FREE FEATURES: Rev. 1.7 (May 2011) 1 DLP Design, Inc. USB - FPGA MODULE DLP-HS-FPGA DLP-HS-FPGA LEAD FREE FEATURES: Xilinx XCS00A-FTGC FPGA utilized on the DLP-HS-FPGA Xilinx XCS00A-FTGC FPGA utilized on the DLP-HS-FPGA Micron M x DDR SDRAM Memory Built-In