ice40hx-8k Breakout Board User s Guide

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1 icehx-8k reakout oard User s Guide November E8_.

2 icehx-8k reakout oard Introduction Thank you for choosing the Lattice icehx-8k reakout oard. This document provides technical information and instructions for using the icehx-8k reakout oard. This kit is based on the Lattice ice-hx8k-ct high performance FPGA device. Two source codes, one written in Verilog and the other in VHDL, are available to download for the icehx-8k reakout oard. oth codes are functionally the same. The contents of this user s guide include demo operation, top-level functional descriptions of the various portions of the evaluation board, descriptions of the on-board connectors, switches, a complete set of schematics and the bill of materials for the icehx-8k Evaluation oard. Features The icehx-8k reakout oard includes: icehx-8k Evaluation oard The icehx-8k Evaluation oard features the following on board capabilities: icehx-8k CT device 8 user accessible LEDs SPI Flash for programming configuration pin. header for user connectivity. holes for user connectivity FTDI H for US interface Mhz oscillator Jumpers to select programming the SPI flash or icehx-8k Pre-loaded Demo The kit comes with a default design that flashes the LEDs on and off US connector Cable A mini US cable for programming the SRAM fabric of the icehx-8k or the onboard SPI flash. The US cable also powers the icehx-8k evaluation board. Figure shows the top side of the icehx-8k Evaluation oard indicating the specific features that are designed on the board.

3 icehx-8k reakout oard Figure. icehx-8k Evaluation oard (Top Side) LEDs icehx-8k pin header." spaced holes US Figure. lock Diagram LEDS(-8) ANK US CONNECTOR US to SPI / RS Power from US V RS ANK FPGA icehx8k-ct ANK ANK SPI

4 ice Device icehx-8k reakout oard This board features an icehx-8k device with a.v core supply. It is packaged in a caga package. For a complete description of this device, see H, ice LP/LX/LM Family Handbook. Software Requirements You should install the following software before you begin developing designs for the evaluation board: Lattice icecube Release:.9SP.98 or later Diamond Programmer: Version. or later These software are available at the Lattice website Design Software & IP page. Make sure you log in to the Lattice website, otherwise these software downloads will not be visible. Demonstration Design The demonstration design icehx8kled.zip file contains the following files: LED_VHDL.vhd (VHDL code) LED_Verilog.v (Verilog code) LED.pcf (pin constraint file) LED_VHDL_bitmap.hex (it stream file for programming FPGA.) LED_Verilog_bitmap.hex (it stream file for programming FPGA.) Two source codes are provided, one written in VHDL and the other in Verilog. oth of these codes function identically. This provides you with an option to use either one of the code when programming the reakout oard. When the FPGA is programmed with one of these codes, the red LEDs (D thru D9) will flash on for ½ second and off for ½ second. Figure shows the block diagram of the Verilog or VHDL code. Figure. lock Diagram of the Verilog or VHDL Code MHz Clk ½ second pulse 9 bit counter Decoder LED LED LED LED 9 The source code has two counters that are used to divide the MHz clock by and 9 generating a approximately ½ second pulse. This pulse along with the decoder will turn the LEDs (D thru D9) on for ½ second and off for ½ second. The decoder can be modified to have any type of LED sequence by changing either the VHDL or Verilog code. When the board is plugged into a US port, a + volt power is applied to the board that will light a green LED (D). After the FPGA has been programmed, a green LED (D) will light. This LED is connected to the CDONE line of the FPGA.

5 oard Power icehx-8k reakout oard The icehx-8k evaluation board is powered with the US cable. LED location D indicates that the board is powered up. All are driven at.v. oard The that feed the holes and the. connector are driven at.v levels. Location J is the populated x row connector. Locations J, J and J have hole locations that the users can connect to for their specific I/O requirements. Programming Options Two jumpers, J and J7 can be set for two types of FPGA Configurations: SPI Flash Mode, for programming the serial flash memory. SPI Peripheral Mode, for configuring the volatile CRAM in the FPGA. In SPI Flash Mode the SPI signals, from the FTDI US interface chip, programs the serial flash memory. After the memory is programmed the FPGA reads from the memory and configures its self. The advantage of programming the serial flash is that the FPGA will be re-configured after power-up. Jumpers must be in locations J7:-, J:-, and J:-. See Figure Figure. SPI Flash Programming In SPI Peripheral Mode the SPI signals loads the program file into the CRAM (configuration ram) of the FPGA directly. In this mode the FPGA will lose its configuration when power is removed and must be re-configured. Jump-

6 icehx-8k reakout oard ers must be in locations J:- and J:-. Jumper J7 is not installed. See Figure Figure. CRAM Programming LED in location D is connected to the CDONE pin of the icehx-8k. This can be monitored to determine that the icehx-8k is programmed correctly. Ordering Information Description ICEHX-8K reakout oard Ordering Part ICEHX8K--EVN China RoHS Environment- Friendly Use Period (EFUP)

7 Technical Support Assistance Internet: ision History Date Version Change Summary November. Initial release. Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

8 Appendix A. Schematic Diagrams Figure. lock Diagram D D LEDS(-8) ANK C C ANK FPGA icehx8k-ct ANK RS Power from US V US to SPI / RS US CONNECTOR ANK SPI A A ice-hx8k reakout oard - lock Diagram ICEHX8K--EVN A D ate: Jul, of

9 Figure 7. US to SPI/RS +.V C C +.V.7uF D D C C.7uF VCC_8FT +.V +.V C C C8 C9 VCC_8FT +.V SCK R ice_sck ADUS 7 SI R VREGIN ADUS FLASH_MOSI 8 SO R C FLASH_MISO C 9 ADUS 9 VREGOUT ADUS SS R ADUS ice_ss_ +.V DM 7 ADUS R DM ice_cdone DP 8 ADUS R DP ADUS7 ice_crest U FTHL VPHY VPLL VCORE VCORE VCORE 9 7 VCCIO VCCIO VCCIO VCCIO C7 C C R7.K ACUS 7 +.V uf RESET# ACUS 8 R8 R9 R R K ACUS 9 ACUS K K K REF ACUS U ACUS ACUS 8 FT_EECS ACUS7 7 VCC CS FT_EECLK EECS 8 R RS_Rx_TTL NU CLK FT_EEDATA EECLK DUS 9 R RS_Tx_TTL ORG DI EEDATA DUS R RTSn C VSS DO DUS R CTSn 9LC-SO8 R.K DUS R7 DTRn OSCI DUS R8 DUS DSRn R9 DCDn +.V DUS DUS7 OSCO 8 CUS X C CUS CUS STANDY# VDD TEST CUS CUS 7 CUS FTDI High-Speed US 8 CUS 9 OUTPUT CUS7.MHZ R ice_clk FTH PWREN# SUSPEND# 7 A A A ice-hx8k reakout oard - US to SPI/RS ICEHX8K--EVN A D ate: Jul, of

10 Figure 8. FPGA D D C C A A MAKE PWR TRACES CAPALE OF A MAKE PWR TRACES CAPALE OF A PIO_ PIO_ PIO_7 PIO_8 PIO_9 PIO_ PIO_ PIO_ PIO_7 PIO_8 PIO_ PIO_7 PIO_9 PIO_ PIO_ PIO_ PIO_ PIO_ PIO_ PIO_8 PIO_9 PIO_ PIO_ PIO_ PIO_ PIO_ PIO_7 PIO_ PIO_7 PIO_ PIO_8 PIO_9 PIO_ PIO_ PIO_ PIO_8 PIO_ PIO_7 PIO_ PIO_ PIO_7 PIO_9 PIO_ PIO_ PIO_ PIO_ PIO_ PIO_ PIO_ PIO_8 PIO_ PIO_9 PIO_ PIO_ PIO_7 PIO_ PIO_ PIO_ PIO_8 PIO_ PIO_9 PIO_8 PIO_ PIO_ PIO_ PIO_ PIO_ PIO_ PIO_9 PIO_ PIO_ PIO_ PIO_8 PIO_7 PIO_ PIO_ PIO_ PIO_9 PIO_7 PIO_ PIO_ PIO_ GIN/PIO_8 PIO_ PIO_ PIO_ PIO_8 PIO_ PIO_ PIO_7 PIO_8 PIO_9 GIN/PIO_8 PIO_ PIO_ PIO_7 PIO_ PIO_8 PIO_ PIO_ PIO_ PIO_ PIO_ PIO_9 PIO_ PIO_ PIO_ PIO_ PIO_ PIO_9 PIO_ PIO_ VCCIO VCCIO +.V +.V +.V VCCIO VCCIO VCC_.V LED7 LED LED LED LED LED LED LED RS_Tx_TTL RS_Rx_TTL DSRn RTSn DTRn DCDn CTSn ate: D of ICEHX8K--EVN A ice-hx8k reakout oard - FPGA Jul 7, ate: D of ICEHX8K--EVN A ice-hx8k reakout oard - FPGA Jul 7, ate: D of ICEHX8K--EVN A ice-hx8k reakout oard - FPGA Jul 7, ANK icehx8k-ct UA ANK icehx8k-ct UA PLLVCC E8 PLL_ E7 GIN/PIO_ C8 GIN/PIO_ F7 VCCIO_ A VCCIO_ A VCCIO_ A8 VCCIO_ F8 PIO_ C PIO_ PIO_ D PIO_ PIO_ C PIO_ E PIO_ C PIO_7 A PIO_8 A PIO_9 PIO_ E PIO_ C PIO_ D PIO_ PIO_ PIO_ PIO_ C PIO_7 A PIO_8 A PIO_9 D PIO_ C9 PIO_ E9 PIO_ D9 PIO_ A9 PIO_ F9 PIO_7 9 PIO_8 D8 PIO_9 8 PIO_ A7 PIO_ C7 PIO_ 7 PIO_ PIO_ C PIO_ D7 PIO_ A PIO_7 D PIO_8 A PIO_9 PIO_ E PIO_ PIO_ A PIO_ D PIO_ A PIO_ C PIO_ C PIO_7 PIO_8 D PIO_9 E PIO_ D PIO_ C C C C C C8 C8 TP7 TP7 TP8 TP8 R R C9 C9 TP TP C7 C7 J Headerx J Headerx R K R K J Headerx J Headerx C7 C7 C C TP TP ANK icehx8k-ct U ANK icehx8k-ct U PIO_ R PIO_ R PIO_ P PIO_ P TRST_ N GIN/PIO_7 H GIN/PIO_8 H VCCIO_ H VCCIO_ C VCCIO_ H VCCIO_ N PIO_ P PIO_ M PIO_ M PIO_7 L PIO_8 N PIO_9 L PIO_ L PIO_ K PIO_ M PIO_ J PIO_ M PIO_ J PIO_ L PIO_7 K PIO_8 K PIO_9 J PIO_ K PIO_ K PIO_ J PIO_ J PIO_ J PIO_ J PIO_ H PIO_9 H PIO_ G PIO_ H PIO_ G PIO_ G PIO_ F PIO_ G PIO_ F PIO_7 G PIO_8 E PIO_9 G PIO_ D PIO_ G PIO_ F PIO_ F PIO_ D PIO_ F PIO_ E PIO_7 C PIO_8 F PIO_9 PIO_ E PIO_ D C C C C R R TP9 TP9 C C TP TP C uf C uf C C R R C C C C

11 Figure 9. FPGA D D C C A A MAKE PWR TRACES CAPALE OF A MAKE PWR TRACES CAPALE OF A GIN/PIO_/DPA PIO_ PIO_ PIO_7 PIO_ PIO_9 PIO_8 PIO_ PIO_ PIO_8 PIO_7 PIO_ PIO_ PIO_ PIO_8 PIO_ PIO_9 PIO_ PIO_ PIO_ PIO_ PIO_ PIO_9 PIO_8 PIO_7 PIO_ PIO_ PIO_/CSEL GIN/PIO_ PIO_/DP PIO_/DP PIO_/DP PIO_/DPA PIO_7/DP PIO_9/DP PIO_/DP PIO_7/DP8 PIO_9/DP9 PIO_/DP PIO_/DP PIO_7/DP PIO_/DP7 PIO_/DPA PIO_/DP PIO_9/DP PIO_8/DPA PIO_/DP PIO_9/DP9 PIO_7/DP8 PIO_/DP PIO_/DPA PIO_/DP PIO_8/DPA PIO_/DPA GIN7/PIO_/DP PIO_ PIO_ PIO_ PIO_8 PIO_ PIO_9 PIO_/CSEL PIO_ PIO_7 PIO_ PIO_ PIO_ PIO_9 PIO_7 PIO_8 PIO_ GIN/PIO_ PIO_ PIO_ PIO_8 PIO_ PIO_ PIO_8 PIO_7 PIO_ PIO_ PIO_9 PIO_ PIO_ PIO_/DPA PIO_/DPA PIO_8/DPA PIO_/DP PIO_/DP PIO_9/DP9 PIO_/DP7 PIO_7/DP8 PIO_/DP PIO_/DP PIO_/DPA PIO_8/DPA PIO_9/DP PIO_/DP GIN/PIO_/DPA PIO_/DP PIO_7/DP PIO_7/DP8 GIN7/PIO_/DP PIO_/DP PIO_9/DP9 PIO_9/DP PIO_7/DP PIO_/DPA PIO_/DP PIO_/DP PIO_/DP PIO_ VCCIO +.V VCCIO +.V +.V VCCIO +.V VCCIO VCC_.V VCCIO ice_clk ice_cdone ice_crest ate: D of ICEHX8K--EVN A ice-hx8k reakout oard - FPGA Jul, ate: D of ICEHX8K--EVN A ice-hx8k reakout oard - FPGA Jul, ate: D of ICEHX8K--EVN A ice-hx8k reakout oard - FPGA Jul, R R C C C C J Headerx J Headerx D Green D Green C C C7 C7 C C C8 C8 C C TP TP TP TP TP TP C C C9 C9 R9 K R9 K C C ANK icehx8k-ct UD ANK icehx8k-ct UD GIN7/PIO_/DP G GIN/PIO_/DPA J VCCIO_ E VCCIO_ G VCCIO_ J VCCIO_ N PIO_/DPA E PIO_/DP PIO_/DPA F PIO_/DP PIO_/DPA C PIO_/DP C PIO_/DPA F PIO_7/DP D PIO_8/DPA G PIO_9/DP D PIO_/DPA G PIO_/DP E PIO_/DPA H PIO_/DP E PIO_/DP7A G PIO_/DP7 F PIO_/DP8A H PIO_7/DP8 F PIO_8/DP9A H PIO_9/DP9 F PIO_/DPA H PIO_/DP G PIO_/DPA J PIO_/DP H PIO_/DPA J PIO_7/DP H PIO_8/DPA J PIO_9/DP J PIO_/DPA K PIO_/DP K PIO_/DPA L PIO_/DP L PIO_/DP7A K PIO_/DP7 M PIO_/DP8A L PIO_7/DP8 L PIO_8/DP9A K PIO_9/DP9 M PIO_/DPA L7 PIO_/DP N PIO_/DPA M PIO_/DP M PIO_/DPA L PIO_/DP N PIO_/DPA P PIO_7/DP M PIO_8/DPA P PIO_9/DP M PIO_/DPA R PIO_/DP N C uf C uf R R C C C9 C9 ANK icehx8k-ct UC ANK icehx8k-ct UC GIN/PIO_ R9 GIN/PIO_7 K9 PLL_ N8 PLLVCC L8 PIO_/CSEL K PIO_/CSEL P CDONE M CRESET_ N VCCIO_ K8 VCCIO_ P VCCIO_ R VCCIO_ R8 PIO_ N PIO_ T PIO_ P PIO_ R PIO_ N PIO_ T PIO_ P PIO_7 R PIO_8 R PIO_9 T PIO_ R PIO_ M7 PIO_ N7 PIO_ P PIO_ M8 PIO_ T PIO_ R PIO_7 P8 PIO_8 T PIO_9 L9 PIO_ T7 PIO_ T8 PIO_ P7 PIO_ N9 PIO_ T9 PIO_ M9 PIO_8 P9 PIO_9 R PIO_ L PIO_ P PIO_ N PIO_ T PIO_ T PIO_ T PIO_ T PIO_7 M PIO_8 T PIO_9 N PIO_ L PIO_ T PIO_ M PIO_ R TP TP R7 R7 C8 C8 TP TP J Headerx J Headerx R8 9 R8 9 TP TP TP TP

12 Figure. Power and LEDs +.V +.V C C C C C C7 C8 uf uf.uf D C9 C C C D uf uf.uf VUS_V U +.V VCC_.V +.V R L 8 7 IN_ OUT_ IN_ C. Ohm ma IN_ OUT_ R C R C C7 IN_.uF C R R 7K uf uf SHDN YP R K uf M M TP TP TP SHDN ADJ C +.V VCC_.V +.V +.V +.V C 9 R7 L R8 PWRGD OUT_ PWRGD C9. Ohm ma OUT_ C8 R9 C.uF.7uF uf THERMPAD YP LEDs LED LED LED LED VUS_V LED LED R LED K +.V LED7 D UF C Green icehx8k-ct L A D D R R R R R R R R7 A _ VPP_FAST E Ohm ma E _ VPP_V K K K K K K K K G7 _ CDU G8 _ G9 _ H7 _ H8 _7 _8 POWER H9 D D D D D D7 D8 D9 J7 _9 +.V J _ J8 VCC J9 D- DM K A _ D+ DP K7 VCC_ F ID R8 L _ VCC_ F R7 _ VCC_ K C T _ VCC_ K _7 A T VCC_ L A SKT_MINIUS RA _8 VCC_ ice-hx8k reakout oard - Power, LEDs ICEHX8K--EVN A D ate: Jul, of ADJ LTEFE#TRPF 7 8 9

13 Figure. SPI +.V D D R9 UE K icehx8k-ct N ice_miso SPI_VCC PIOS_/SPI_SO P P ice_mosi C PIOS_/SPI_SI R PIOS_/SPI_SCK SPI R PIOS_/SPI_SS_ C R R R FLASH_MOSI FLASH_MISO C SDI SDO C U K K K ice_sck J7 SCK WP ice_ss_ CS HOLD 7 Short-circuit Jumper NQAESCF JU JU JU 9-LF 9-LF 9-LF J7: Remove shunt only for Programming ice. Replace shunt for programming Flash and for normal operation. J FLASH_MOSI ice_miso ice_mosi FLASH_MISO For programming Flash - Shunt, and, (default) For programming ice - Shunt, and, A A ice-hx8k reakout oard - SPI ICEHX8K--EVN A D ate: Jul, of VCC 8

14 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Lattice: ICEHX8K--EVN

ice40hx-8k Breakout Board User Guide EB85 Version 1.1, January 2016

ice40hx-8k Breakout Board User Guide EB85 Version 1.1, January 2016 icehx-k reakout oard User Guide E Version., January icehx-k reakout oard Introduction Thank you for choosing the Lattice icehx-k reakout oard. This document provides technical information and instructions