To read more. CS 6354: Homework 1 Related / Precise Interrupts. Homework 1. On paper reviews

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Molly Lambert
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1 To read more CS 6354: Homework Related / Precise Interrupts 9 September 06 This day s paper: Smith and Pleszkan, Implementation of Precise Interrupts in Pipelined Processors Materials on virtual memory/demand paging (a reason we need precise interrupts): Hennessy and Patterson, Computer Architecture: A Quantitative Approach, sections B.5-B.6 (graduate text) Bryant and O Hallaron, Computer Systems: A Programmer s Perspective, section.7, sections 9.-7 (undergrad text) Supplementary readings on precise interrupts: Hennessy and Patterson, Computer Architecture: A Quantitative Approach, section 3.6 Shin and Lipatsi, Modern Processor Design, section Homework data cache sizes instruction cache sizes TLB size data cache associativity TLB associativity throughput (read/write; sequential/random) latency (maximum) prefetching? two of many choices On paper reviews What was your most significant insight from the paper? Example good answers: Implementing precise interrupts requires degrading processor performance To get good performance in a heavily d processor, we need to allow instructions to use values from prior instructions that aren t finished yet. One can provide precise interrupts by allowing instructions to complete out-of-order, but maintaining a consistent state to restore if an interrupt occurs. Not-so-good answers: There are several ways to implement precise interrupts. 3

2 Reasons for precise interrupts Virtual memory virtual memory debugging multiprocessing (timer interrupts) virtual machines trap-and-emulate VirtualBox, VMWare, Xen, parallels future hardware trap-and-emulate example: floating point support Program Virtual Virtual Page 7: 0x7000 0x7FFF Virtual Page 6: Virtual Page 5: Virtual Page 4: Virtual Page 3: Virtual Page : 0x000 0xFFF Virtual Page : 0x000 0xFFF Virtual Page 0: Page Table Physical Physical Page 6: Physical Page 5: Physical Page 4: Physical Page 3: Physical Page : 0x000 0xFFF Physical Page : 0x000 0xFFF Physical Page 0: Program Virtual Virtual Page 7: 0x7000 0x7FFF Virtual Page 6: Virtual Page 5: Virtual Page 4: Virtual Page 3: Virtual Page : 0x000 0xFFF Virtual Page : 0x000 0xFFF Virtual Page 0: 4 5 Virtual memory Page tables and the TLB () Program Virtual Virtual Page 7: 0x7000 0x7FFF Virtual Page 6: Virtual Page 5: Virtual Page 4: Virtual Page 3: Virtual Page : 0x000 0xFFF Virtual Page : 0x000 0xFFF Virtual Page 0: Page Table Physical Physical Page 6: Physical Page 5: Physical Page 4: Physical Page 3: Physical Page : 0x000 0xFFF Physical Page : 0x000 0xFFF Physical Page 0: 7 yes 5 5 yes 4 yes 6 no yes 7 yes 5 5 yes 4 yes 6 no yes fully-associative TLB (fast cache) tag (virt.) physical last use 7 5 most recent 5 6

3 TLB access pattern () TLB access pattern () 7 yes 5 5 yes 4 yes 6 no yes access pattern memory access split of address result load 0x7050 virtual page 7, offset 0x050 hit load 0x003 virtual page, offset 0x003 hit load 0x5F05 virtual page 5, offset 0xF05 miss (replace 6) load 0x7D57 virtual page 7, offset 0xD57 hit load 0x543 virtual page 5, offset 0x43 hit fully-associative TLB (fast cache) tag (virt.) physical last use 7 5 most recent most recent 55 (was 4)4 6 (was 6) most recent 7 yes 5 5 yes 4 yes 6 no yes access pattern memory access split of address result load 0x7050 virtual page 7, offset 0x050 hit load 0x003 virtual page, offset 0x003 hit load 0x5F05 virtual page 5, offset 0xF05 miss (replace 7) load 0x7D57 virtual page 7, offset 0xD57 miss (replace ) load 0x543 virtual page 5, offset 0x43 hit fully-associative TLB (fast cache) tag physical last use (virt.) 75 5 most recent 7 5 most recent 7 8 Demand Paging Caches on Caches 7 noyes 5 (just allocated)5 6 no 5 no 4 no no noyes (just loaded) access pattern OS s information virtual valid? location on disk 7 yes (none, allocate 0s) 5 no 4 no 3 yes 0x4000 yes 0x3000 yes 0x000 memory access split of address result load 0x004 virtual page, offset 0x004 not present, page fault load 0x008 virtual page, offset 0x008 present load 0x7FF4 virtual page 7, offset 0xFF4 not present, page fault load 0x00C virtual page, offset 0x00C present load 0x7FF0 virtual page 7, offset 0xEE0 present memory as software-managed cache for disk operating system makes all decisions page faults are hardware support for the software way to ask operating system to make decision illusion of much larger memory (with worse performance disk/ssd is slow) 9 0

4 The Page Fault Handler operating system code called when user code wants not present virtual page operating system often restarts instruction restart reset registers, jump to after making the page present A Page Fault User Program $sp 0x7FF4 Mem[$sp+4] $a0 $a0 0x000 Mem[$sp+8] $a 7 noyes 5 (just allocated) 6 no 5 no 4 no no yes Operating System page_fault_handler: ; address of Mem[$sp + 4] $a0 in $exception_pc (special register) ; faulting address 0x7FF4 in $bad_addr (special register) save user registers insert page table based on $bad_addr restore user registers rfi ; return from interrupt jump to $exception_pc Setup: a more complex The Precise Interrupts Problem multiple dynamic issue Buffer and Read Simple User Program R 0x7000 Mem[R] R // Mem[0x7000] R R R + 0 Mem[4 + R] R3 // Mem[0x7004] R3 R3 R3 + 0 multiple dynamic issue Buffer and Read Simple Modified R, R3 already. Can t restart without fixing. R R + 0 R3 R Mem[R] R (triggers page fault) 4

5 Precise Interrupt Options Precise Interrupt Options 5 6 In-order completion In-order completion: Example Buffer and multiple dynamic issue Read Read Simple (one at a time) require instructions to write back in order don t schedule if it wouldn t 7 Buffer and R 0x7000 // () Mem[R] R // () R R + 0 // (3) Mem[4 + R] R3 // (4) R3 R3 + 0 // (5) R5 Mem[8 + R] // (6) Read Simple Read (one 3 4 at a 5time) complete in store completes simple + 3 = 4 () memory + 4 = 5 () 3 fancy + 4 = 53+ simple (3)(3) 3 = 6 3 (3) memory would complete with = 7 () (4) disallowed 5 simple = 8 (5) 4 memory = 9 (6) 8

6 In-order completion: An exception Result-Shift Register complete in simple + 3 = 4 () memory + 4 = 5 () 3 simple = 6 (3) 3 memory = 7 (4) 5 simple = 8 (5) 4 memory = 9 (6) out-oforder issue in-order commit Exception during ()? Detect at 5 register writes/memory stores suppressed complete in simple + 3 = 4 () memory + 4 = 5 () 3 simple = 6 (3) 3 memory = 7 (4) 5 simple = 8 (5) 4 memory = 9 (6) result shift register (t=) (t=) (t=3) (t=4) (t=5) time to complete used? dest no yes memory simple R (mem.) R () () (3) no yes simple memory R R (mem.) () () (3) (4) 3 yes memory simple R R (mem.) R3 () () (3) (4) (5) 4 yes simple memory R (mem.) R3 R5 () (3) (4) (5) (6) 5 yes no simple memory R (mem.) R3 R5 (3) (4) (5) (6) not started yet Rules: Place entries in result shift register in program order. Always place after all existing entries. (Also, don t break data dependencies.) 9 0 Precise Interrupt Options The Re-Order Buffer Reserve and Read multiple dynamic issue Simple () Commit: Copy Commit from to Commit # used? dest result 4 yes R (waiting) () 5 yes (mem.) (waiting) () 6 yes R (waiting) (3) 7 yes (mem.) (waiting) (4) 8 yes R3 (waiting) (5) 9 yes R5 (waiting) (6) reserved in-order written whenever ready committed to regs. in-order

7 Scheduling with Operating the R 0x7000 // () Mem[R] R // () R R + 0 // (3) Mem[4 + R] R3 // (4) R3 R3 + 0 // (5) R5 Mem[8 + R] // (6) to in simple + 3 = 4 () memory + 4 = 6 () fancy + 4 = 5 (3) 3 memory + 4 = 7 (4) simple + 3 = 5 (5) memory + 5 = 6 (6) # () used? dest result 4 yes R (waiting) () 5 yes (mem.) (ask mem) () 6 yes R (waiting) (3) 7 yes (mem.) (ask mem) (4) 8 yes R3 (waiting) (5) 9 yes R5 (waiting) (6) 3 Look at for first instruction in program order Wait for result of that instruction to be available Then, copy result to destination register (or send signal to memory system) to in simple + 3 = 4 () memory + 4 = 6 () fancy + 4 = 5 (3) 3 memory + 4 = 7 (4) simple + 3 = 5 (5) memory + 5 = 6 (6) reorder buffer () () (t=5) (t=6) (t=4) (t=) # used? dest used? dest result result result 4 yes copied R 0x7000 (waiting)() () () memory 5 yes (mem.) (ask mem) () to yes (mem.) (ask (ask mem) cache) () () () not ready R ready 6 yes yes R 0x000 (3) R (waiting) (3) (3) (3) 7 yes (mem.) (ask mem) (4) yes (mem.) (ask (ask mem) cache) (4) (4) (4) 8 yes R3 0x0050 0x0050 (5) yes R3 (waiting) (5) (5) (5) 9 yes R5 0x34567 (waiting) (6) yes R5 (waiting) (6) (6) (6) 4 and exceptions and forwarding result is exception instead of value to store clear rest of instead of committing to register then call OS Exception info needs to be stored in why? MEM[R6] R7 ; () R R + R3 ; () R4 R + R5 ; (3) increases time to write registers (3) needs to wait for () to finish otherwise, old value of R unless bypass to read instead of regfile likely more delay than MIPS-style forwarding 5 6

8 circular buffer and memory () (t=6) # 0 (next to commit) head used? dest result defer stores until at top of also loads unless they use different addresses than stores more complicated with multiple processors 3 yes 4 yes 5 yes 6 yes 7 yes tail yes next added Precise Interrupt Options 9 no 0 no Future file maintain two copies of registers use for one in-order commit use other one for forwarding easier than bypass logic? 9 30

9 Precise Interrupt Options History buffer Like but holds prior values On exception: wait for all pending operations to finish copy prior values for everything after exception (in program order) 3 3 Speculation predict a branch? make for branch in if result is not expected treat like exception avoid committing speculated register changes 33 Summary restriction on when instructions start but store results in buffer commit from buffer to registers in program order bypassing to make buffered values available early instead of bypassing, maintain two copies of registers store results out-of-order to registers but store prior values in buffer copy from buffer on exception 34

Topic 18: Virtual Memory

Topic 18: Virtual Memory COS / ELE 375 Computer Architecture and Organization Princeton University Fall 2015 Prof. David August 1 Virtual Memory Any time you see virtual, think using a level of indirection