A Few Problems with Physical Addressing. Virtual Memory Process Abstraction, Part 2: Private Address Space

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1 Process Abstraction, Part : Private Motivation: why not direct physical memory access? Address translation with pages Optimizing translation: translation lookaside buffer Extra benefits: sharing and protection A Few Problems with Addressing address (PA) Main memory : : : : : : : 7: 8: M-:... as a contiguous array of bytes is a lie! Why? Solution: (address indirection) Addressing and Address Translation Process Process n address space address space virtual addresses virtual addresses virtual-to-physical mapping data physical addresses memory data Management Unit translates virtual address to physical address Chip address () : : address : (PA) : : : : 7: 8: Main memory M-:... Private virtual address space per process. Single physical address space managed by OS/hardware. addresses are invisible to programs. 9

2 -based Mapping fixed-size, aligned pages page size = power of two Design for a Slow Disk: Exploit Locality n - v - Map virtual pages onto physical pages. m - p - Some virtual pages do not fit! Where are they stored? n - v - on disk m - p - Table array of entries (s) mapping virtual page to where it is stored 7 Valid Number or disk address resident, managed by HW (), OS VP VP VP VP PP PP Address Translation with a Table table base register (PTBR) Base address of current process's page mapped to physical page? Yes = Hit address () page number (VPN) table Valid page number (PPN) page number (PPN) address (PA) page offset (VPO) page offset (PPO) How many s are in the system? 7 8

3 Hit: virtual page in memory Number Number PP PP On disk PP On disk 7 PP VP VP VP VP PP PP Fault: exceptional control flow Process accessed virtual address in a page that is not in physical memory. Process User Code movl exception: page fault return OS exception handler Load page into memory 9 Returns to faulting instruction: movl is executed again! Fault:. page not in memory Number Number PP PP On disk PP On disk 7 PP What now? OS handles fault VP VP VP VP PP PP Fault:. OS evicts another page. Number 7 Number On disk PP On disk PP On disk PP VP VP VP VP VP " out" PP PP

4 Fault:. OS loads needed page. Number Number On disk PP PP PP On disk 7 PP Finally: Re-execute faulting instruction. hit! VP VP VP VP VP " in" PP PP Terminology context switch Switch control between processes on the same. page in Move page of virtual memory from disk to physical memory. page out Move page of virtual memory from physical memory to disk. thrash Total working set size of processes is larger than physical memory. Most time is spent paging in and out instead of doing useful computation. (I find all these terms useful when talking to other computer scientists about my brain) Useful for "real life" too. swap Address Translation: Hit Address Translation: Fault Exception fault handler Chip A PA Chip 7 A Victim page New page Disk ) Processor sends virtual address to (memory management unit) -) fetches from in cache/memory ) sends physical address to cache/memory ) memory sends data word to processor ) Processor sends virtual address to -) fetches from in cache/memory ) Valid bit is zero, so triggers page fault exception ) Handler identifies victim (and, if dirty, pages it out to disk) ) Handler pages in new page and updates in memory 7) Handler returns to original process, restarting faulting instruction 7

5 How fast is translation? TLB Hit How many physical memory accesses are required to complete one virtual memory access? Chip TLB Translation Lookaside Buffer (TLB) Small hardware cache in just for entries e.g., 8 or entries VPN PA Much faster than a lookup in memory. In the running for "un/classiest name of a thing in CS" A TLB hit eliminates a memory access 8 9 TLB Miss Simple System Example (small) Chip TLB Addressing -bit virtual addresses -bit physical address size = bytes Simulate accessing these virtual addresses on the system: xd, xb8f, x VPN A PA VPN VPO Number Offset A TLB miss incurs an additional memory access (the ) Fortunately, TLB misses are rare. Does a TLB miss require disk access? PPN Number PPO Offset

6 Simple System Table Only showing first entries (out of = 8 ) virtual page # TLB index TLB tag TLB Hit? Fault? physical page #: Simple System TLB entries -way associative TLB ignores page offset. Why? VPN PPN Valid VPN PPN Valid A 9 B C D D E 7 F D What about a real address space? Read more in the book TLB tag TLB index virtual page number virtual page offset virtual page # TLB index TLB tag TLB Hit? Fault? physical page #: Set Tag PPN Valid Tag PPN Valid Tag PPN Valid Tag PPN Valid 9 D 7 D A 8 7 D A Simple System Cache lines -byte block size ly addressed Direct mapped cache tag cache index cache offset physical page number physical page offset cache offset cache index cache tag Hit? Byte: Idx Tag 9 B Valid B 99 B D B 8F B 8 9 Idx 8 9 A B C Tag D D B Valid B A 9 B B DA B 89 B 7 D 7 C F DF D D E F B D