ARMv8: The Next Generation. Minlin Fan & Zenon Xiu December 8, 2015
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1 ARMv8: The Next Generation Minlin Fan & Zenon Xiu December 8,
2 Introducing Ourselves Minlin Fan Application Engineering Manager Zenon Xiu Application Engineering Software Team Lead 2
3 ARM Partner Enablement 3
4 Where to Find ARM Documentation ARM s documentation can be found at Useful sections: ARM architecture ARM and GIC architecture reference manuals ARM Technical Support Knowledge Articles FAQs Cortex -A/R/M series processors Technical Reference Manuals Developer Guides and Articles Detailed discussions of TrustZone, barriers 4
5 Global ARM Support 5
6 Active Assist 6
7 ARM Training 7
8 Training Options From ARM Onsite, anywhere delivery Face-to-face with ARM experts Customized agendas ARM hosted Public schedule Open enrolment Live broadcast from ARM Distributed teams Targeted, agile delivery 8
9 ARMv8-A Overview 9
10 Development of the ARM Architecture ARMv8-A is one of the most significant architecture changes in ARM s history Positions ARM to continue servicing current markets as their needs grow 10
11 What s New in ARMv8-A? ARMv8-A introduces two execution states: AArch32 and AArch64 AArch32 Evolution of ARMv7-A A32 (ARM) and T32 (Thumb) instruction sets ARMv8-A adds some new instructions Traditional ARM exception model Virtual addresses stored in 32-bit registers AArch64 New 64-bit general purpose registers (X0 to X30) New instructions A64, fixed length 32-bit instruction set Includes SIMD, floating point and crypto instructions New exception model Virtual addresses now stored in 64-bit registers 11
12 Agenda Architecture versions Privilege levels AArch64 Registers and A64 Instruction Set AArch64 Exception Model AArch64 Memory Model ARMv8.1 12
13 AArch64 Privilege Model AArch64 has four exception levels, and two security states EL0 = least privileged, EL3 = most privileged Secure state and non-secure (or Normal) state Non-secure Secure EL0 App App App App Trusted Services EL1 OS OS Trusted Kernel EL2 Hypervisor No EL2 in Secure world EL3 Secure Monitor EL2 and EL3 are optional A processor may not implement EL2/3 if Security or Virtualization are not required 13
14 Moving Between AArch32 & AArch64 Execution state can only change on exception entry or return Moving to a lower EL, execution state can stay the same or switch to AArch32 Moving to a higher EL, execution state can stay the same or switch to AArch64 AArch64 OS can host a mix of AArch64 and AArch32 applications AArch32 App AArch64 App AArch32 App AArch64 App An AArch32 OS cannot host a AArch64 application AArch64 OS AArch32 OS AArch64 Hypervisor can host AArch64 and AArch32 OSs AArch64 Hypervisor AArch32 Hypervisor cannot host AArch64 OSs 14
15 Agenda Architecture versions Privilege levels AArch64 registers and the A64 Instruction Set AArch64 Exception Model AArch64 Memory Model ARMv8.1 15
16 Register Banks AArch64 provides 31 general purpose registers Each register has a 32-bit (w0-w30) and 64-bit (x0-x30) form Separate register file for floating point, SIMD and crypto operations - Vn 32 registers, each 128-bits Can also be accessed in 32-bit (Sn) or 64-bit (Dn) forms Xn Wn V0 D0 S0 V1 D1 S1 16
17 AArch64 AArch32 Register Mappings X0-X7 X8-X15 X16-X23 X24-X30 R0 R8_usr R14_irq R8_fiq R1 R9_usr R13_irq R9_fiq R2 R10_usr R14_svc R10_fiq R3 R11_usr R13_svc R11_fiq R4 R12_usr R14_abt R12_fiq R5 R13_usr R13_abt R13_fiq R6 R14_usr R14_und R14_fiq R7 R13_hyp R13_und When moving from AArch32 to AArch64 Registers accessible in both registers widths Top 32 bits: UNKNOWN Bottom 32 bits: The value of the AArch32 register Registers that are not accessible in AArch32 retain value from previous AArch64 execution 17
18 A64 AArch64 introduces new A64 instruction set Similar set of functionality as traditional A32 (ARM) and T32 (Thumb) ISAs Fixed length 32-bit instructions Syntax similar to A32 and T32 ADD W0, W1, W2 ADD X0, X1, X2 w0 = w1 + w2 (32-bit addition) x0 = x1 + x2 (64-bit addition) Most instructions are not conditional Optional floating point and Advanced SIMD instructions Optional cryptographic extensions Low level acceleration for AES, SHA1, SHA224 and
19 Agenda Architecture versions Privilege levels AArch64 registers and the A64 Instruction Set AArch64 Exception Model AArch64 Memory Model ARMv8.1 19
20 AArch64 Exceptions In AArch64 exceptions are split between: Synchronous Data aborts from MMU, permission/alignment failures, service call instructions, etc. Asynchronous IRQ/FIQ SError (System Error) On taking an exception the EL can stay the same OR get higher Exceptions are never taken to EL0 IRQ? Asynchronous exceptions can be routed to a specific EL Separate bits to control routing of IRQs, FIQs and SErrors EL0 (App) EL1 (OS) EL2 (Hyp) EL3 (Monitor) 20
21 Agenda Architecture versions Privilege levels AArch64 registers and the A64 Instruction Set AArch64 Exception Model AArch64 Memory Model ARMv8.1 21
22 Virtual Address Space Virtual addresses are 64-bit wide, but not all addresses are accessible Virtual memory address space split between two translation tables Each covering a configurable size, up to 48 bits of address space (TCR_ELn) Addresses not covered by either translation table generate translation faults 0xFFFF,FFFF,FFFF,FFFF Not available in EL2 or EL3 Virtual address space Peripherals OS Translation Tables Physical address space Peripherals 0xFFFF,0000,0000,0000 TTBR1_EL1 FLASH FAULT 0x0000,FFFF,FFFF,FFFF RAM Application Translation Tables 0x0 TTBR0_ELn 22
23 Multiple Translation Regimes The virtualization extensions introduce a second stage of translation First stage: Virtual Address (VA) Intermediate Physical Address (IPA) Operation of MMU appears unchanged for guest OSs, still use TTBRn_EL1 and TCR_EL1 Second stage: Intermediate Physical Address (IPA) Physical Address (PA) Controlled by the Hypervisor The Hypervisor and Secure Monitor also have a set of stage 1 Translation Tables Mapping directly from VA to PA OS (EL1) Stage 1 Peripherals Stage 2 Peripherals Application (EL0) Guest OS Translation Tables TTBRn_EL1 FLASH RAM Translation Tables VTTBR0_EL2 RAM Peripherals Virtual memory map Under control of guest OS Hypervisor (EL2) Hypervisor Translation Tables TTBR0_EL2 Physical memory map seen by guest (IPA) RAM FLASH Secure Mon (EL3) Virtual memory space seen by Hypervisor & Secure Monitor Monitor Translation Tables TTBR0_EL3 Real physical memory map 23
24 Physical Address Spaces ARMv8-A defines two security states: Secure and Non-secure (Normal) It also defines two physical address spaces: Secure and Non-secure These are in theory completely separate: SP:0x8000!= NP:0x8000 But most systems treat Secure/Non-Secure as an attribute for access control Normal world can only access the non-secure physical address space Secure EL1/EL0 Secure Peripherals Secure Data Non-Secure Data Secure Code Translation Tables Secure physical address space RAM Peripherals FLASH Secure world can access BOTH physical address spaces Controlled through translation tables Non-secure EL1/EL0 Non-Secure Peripherals Non-Secure Data Translation Tables Non-secure physical address space RAM Peripherals Non-Secure Code FLASH 24
25 Agenda Architecture versions Privilege levels AArch64 registers and the A64 Instruction Set AArch64 Exception Model AArch64 Memory Model ARMv8.1 25
26 ARMv8.1-A The ARM architecture continues to evolve, with the announcement of ARMv8.1-A Instruction set enhancements Atomic read-write instructions added to A64 For example: Compare and swap Additional SIMD instructions Example use case is colour space conversion Load and stores with ordering limited to a configurable region Virtualization Host Extensions To improve performance of Type 2 Hypervisors And other enhancements to the memory system architecture, such as Privileged Access Never (PAN) state bit 26
27 ARMv8-A Overview 27
28 So Much to Say Day 0 ARMv7-A Architecture The ARM Architecture Day 1 Introduction to ARMv8-A AArch64 A64 ISA Overview AArch64 Exception Model AArch64 Memory Management AArch64 Memory Model Caches and Branch Prediction Day 2 Barriers Synchronization Cache Coherency Operating System Support SW Engineer s Guide to Cortex-A5x Booting Day 3 Security Virtualization Power Management (optional) GIC Programming (optional) Debug (optional) so little time! 28
29 Where to Go Next? 29
30 Thank you Any questions? 30
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