ECE 2300 Digital Logic & Computer Organization

Transcription

1 ECE 2300 Digital Logic & Computer Organization Spring 201 Memories Lecture 14: 1

2 Announcements HW6 will be posted tonight Lab 4b next week: Debug your design before the in-lab exercise Lecture 14: 2

3 Review: ALU Operation Encodings NAME OP BSEL CI LOP SOP OSEL Operation ADD Y = A + B + CI SUB Y = A + B + 1 AND Y = A AND B OR Y = A OR B SHL Y = A[6..0],SI SHR Y = SI,A[7..1] PASS A Y = A A B CI Adder A Y B CO CI O Logical A Y B LOP CO O Y OP Control Logic BSEL 3 OP LOP SOP OSEL 2 2 SI Shifter A Y SI SO SOP SO NOR Z Lecture 14: 3

4 Comparison Operations (Byproduct of SUB) To compare A and B, perform A B If the result is 0, then A = B Z flag set to 1 whenever ALU result is 0 Can check for A B and A < B by observing the MSB of the result of A B A B CI Adder A Y B CO CI O Logical A Y B LOP CO O Y OP Control Logic BSEL 3 OP LOP SOP OSEL 2 2 SI Shifter A Y SI SO SOP SO NOR Z Lecture 14: 4

5 Our Microprocessor Needs Memory +2 sext({off,0}) Adder MUX 0 1 MP PC Inst. RAM DR SA SB MB FS MD RW MW Decoder RF RW SA SB DR D_in DataA DataB SE IMM 0 1 MB F m F 0 ALU V C Z N M_address Data_in Data RAM MW 0 1 MD Lecture 14: 5

6 General Memory Organization Two dimensional array of bit cells Each bit cell stores 1 bit Address selects a word with multiple bit cells Address Data A 3-bit word Address 2 Array depth Data width Lecture 14: 6

7 General Memory Structure 2:4 Decoder decoder bitline 2 bitline 1 bitline 0 11 wordline 3 Address wordline 2 wordline 1 wordline 0 stored bit = 0 stored bit = 1 stored bit = 1 stored bit = 0 stored bit = 1 stored bit = 0 stored bit = 1 stored bit = 1 stored bit = 0 stored bit = 0 stored bit = 0 stored bit = 1 Data 2 Data 1 Data 0 Lecture 14: 7

8 Types of Memories Read-Only Memory (ROM) Truly read-only Written in the factory, and never written after installation Mostly read and rarely written Much faster to read than write Non-volatile, e.g., flash memory Random Access Memory (RAM) Read and write any location at similar speeds Volatile: loses contents when powered off SRAM, DRAM Lecture 14:

9 Read-Only Memory (ROM) Structure fixed at factory or rarely written n address lines decoder 2 n word lines memory array (2 n m) m bit lines Lecture 14: 9

10 Example ROM Implementation resistors word line bit line data output Lecture 14: 10

11 Applications of ROM Program storage e.g., Boot code for personal computers, Complete application storage for embedded systems Data storage e.g., Configuration information, music players, SSDs Combinational logic functions Lookup table Address inputs = function inputs Data outputs = function outputs Lecture 14: 11

12 Using ROMs for Combinational Logic F0 = A' B' C + A B' C' + A B' C F1 = A' B' C + A' B C' + A B C F2 = A' B' C' + A' B' C + A B' C' F3 = A' B C + A B' C' + A B C' A B C F0 F1 F2 F A B C decoder word lines memory array ( words by 4 bits) F0 F1 F2 F3 Lecture 14: 12

13 What Function does this ROM Implement? Y1, Y0, X1, X0 (address) Z3, Z2, Z1, Z0 (output) x 4 ROM Y1 Y0 X1 X0 A3 A2 A1 A0 D3 D2 D1 D0 Z3 Z2 Z1 Z Lecture 14: 13

14 ROM As a Random-Logic Circuit ROM advantages Design time is short Can implement any function of n inputs ROM problems Size doubles for each additional input Cannot exploit logic minimization (e.g., don't cares) Lecture 14: 14

15 Types of Memories Read-Only Memory (ROM) Truly read-only Written in the factory, and never written after installation Mostly read and rarely written Much faster to read than write Non-volatile, e.g., flash memory Random Access Memory (RAM) Read and write any location at similar speeds Volatile: loses contents when powered off SRAM, DRAM Lecture 14: 15

16 Dynamic RAM (DRAM) Lecture 14: 16

17 Capacitor accessed through a transistor Capacitor is charged or discharged to produce a 1 or a 0 DRAM Bit Cell Word line (WL) 1-Bit DRAM Cell Bit line (BL) DRAM cells loses their state overtime and must be refreshed periodically, hence the name dynamic Lecture 14: 17

18 Word line is asserted DRAM Write Bit line is driven with the desired value Capacitor is charged by the bit line to store a 1 Or discharged by the bit line to store a 0 Word line (WL) 1-Bit DRAM Cell Bit line (BL) Lecture 14: 1

19 Word line is asserted DRAM Read Bit line precharged halfway between 0 and 1 Capacitor voltage pulls the bit line slightly higher or lower Sense amplifier detects this small change (1 or 0) Word line (WL) 1-Bit DRAM Cell Bit line (BL) Read destroys the stored value Need to rewrite the value afterwards Lecture 14: 19

20 Common DRAM Structure (1) Multiplexed address inputs Row and column address share same pins Row address bits arrive first; followed by column address bits Row-address strobe (RAS) Selects a row Column-address strobe (CAS) Selects a column Row and column address bits combined form the complete address Row Addr Latch & Row Decoder RAS ADDR CAS Memory Array Sense Amps Colum Addr Latch, Column Mux & Demux WE Data In/Out Buffer Lecture 14: 20

21 Example: Read Access to 1Mx1 DRAM Chip 1Mb DRAM array = 1024 rows x 1024 columns 10 row address bits arrive first Row Addr Latch & Row Decoder Memory Array RAS asserted 10 column address bits arrive later 1024 bits are read out Colum Addr Latch Column Mux & Demux 1 bit returned CAS asserted Lecture 14: 21

22 Common DRAM Structure (2) Row Addr Latch & Row Decoder Memory Array Bi-directional data input/output (to save pins) Write enable strobe (WE) WE = 1 : Write mode WE = 0 : Read mode RAS Sense Amps WE ADDR CAS Colum Addr Latch, Column Mux & Demux D inout WE Data In/Out Buffer Bit line Lecture 14: 22

23 Tri-State Drivers Along with 0 and 1, there is a third Hi-Z output Output floats - no connection to supply or ground EN A OUT Hi-Z Hi-Z 0 1 Allows bidirectional data bus Allows multiple circuits drive the same line (e.g., wire, bus) Only one node drives the line; others in Hi-Z state Lecture 14: 23

24 Tri-State Drivers EN C Q2 OUT A D Q1 EN A C D Q1 Q2 OUT L L H L off off Hi-Z L H H L off off Hi-Z H L H H on off L H H L L off on H Lecture 14: 24

25 Bidirectional Input/Output via Tri-State Drivers Write Enable (WE) D inout Bit line WE = 0 (read mode): D inout is used as output and driven by Bit line WE = 1 (write mode): D inout is used as input and driving Bit line Lecture 14: 25

26 DRAM Refresh Capacitors discharge over time Refresh cycles recharge each memory bit Refresh an entire row at a time Each row periodically accessed using RAS, which restores the charge V cap 0 written 1 written refresh refresh refresh V DD HIGH LOW 0V time Lecture 14: 26

27 Static RAM (SRAM) Bit Cell One cell requires six transistors The core is two cross-coupled inverters Maintaining the state of the cell requires a constant power The cell is stable; no refresh cycles needed WL 6-Transistor SRAM Cell V dd BL = bit line WL = word line BL BL Lecture 14: 27

28 SRAM Write Drive one bit line high, the other low (depending on the desired value) WL Then turn on word line Bit lines over power cell with new value BL BL Lecture 14: 2

29 SRAM Read Precharge both bit lines high Then turn on word line WL One of the two bit lines will be pulled down by the cell Change detected by sensor amplifier BL BL Lecture 14: 29

30 Write Enable SRAM Architecture Din n-1 Din n-2 Din 1 Din 0 Column Driver Column Driver Column Driver Column Driver... WL A0 An-1 Address Decoder... WL WL BL BL BL BL BL BL BL BL Sense Amp Sense Amp Sense Amp Sense Amp Dout n-1 Dout n-2 Dout 1 Dout 0 Lecture 14: 30

31 H&H Before Next Class Next Time Single Cycle Microprocessor Lecture 14: 31