# Unit 6 1.Random Access Memory (RAM) Chapter 3 Combinational Logic Design 2.Programmable Logic

Size: px
Start display at page:

Download "Unit 6 1.Random Access Memory (RAM) Chapter 3 Combinational Logic Design 2.Programmable Logic"

Transcription

1 EE 200: Digital Logic Circuit Design Dr Radwan E Abdel-Aal, COE Unit 6.Random Access Memory (RAM) Chapter 3 Combinational Logic Design 2. Logic Logic and Computer Design Fundamentals Part Implementation Technology and Logic Design (Sections ) Charles Kime & Thomas Kaminski 2004 Pearson Education, Inc. Terms of Use (Hyperlinks are active in View Show mode) (Sections ). Random Access Memory (Read/Write) Storage element Memory device for data storage A latch or a flip flop stores one bit A register of m such flip flops stores m bits m = 8: Byte, m = 6: Word, m = 32: double words, m = 64: Quad words, etc. Over the years, Processors have used larger and larger registers to store/ process data: m = 4, 8, 6, 32, 64, 28 bits

2 Computer Storage The computer needs to store programs and data Primary Storage Solid State (Semiconductor) Memory (Random Access) Volatile Read/Write (RAM)* - Faster Speed - More Costly (per bit) - Smaller Capacity - Closer to processor Non Volatile (e.g. for booting) Read Only (ROM) Secondary (Mass) Storage Discs, tapes, CDs (Sequential Access) Now new mass storage devices are Solid State (semiconductor)! Static Dynamic SRAM ROM PROM EPROM EEPROM? DRAM: - Larger Capacity - Cheaper per bit - Lower power - But needs continuous refreshing to maintain data * Misnomer Why? The Read/Write becoming a misnomer as well! Chapter 3 - Part 3 Random Access (Read/Write) Memory (RAM) - A RAM memory Chip effectively contains a number of registers - Why random access? Time taken to transfer data to or from any address (storage location) is the same regardless of the address - This is different from sequential storage, e.g. Disc, CD, or tape Example: 024 ( k) locations 6-bit each Chapter 3 - Part 4 2

4 Memory Write and Read Cycles Processor 0 Data at I/Ps into addressed location here t setup t hold Data must be valid here Memory Write and Read Cycles Processor Access time (e.g. 20 ns) Old data on the O/P data bus New data retrieved from the addressed location 4

5 Types of RAM (Read/Write) Memories Two Basic Types: Static RAM (SRAM): Data stored in latch ( latch per bit) and remains as long as power remains ON -bit Cell 4 Transistors SRAM Dynamic (DRAM): Data stored as a charge on a capacitor can be lost due to leakage, needs to be periodically refreshed, otherwise data will be lost even with power ON Comparison: Speed, Cost, Density, Applications () Bit Only Transistor Per -bit cell Bare Circuits (Storage Only) Write Read DRAM Modeling a Complete bit circuit (BC) with controls = to select bit Here, a cell that is not selected Produces a (0/) O/P? Data Q Data Encapsulated SR=00: No Change (Read) /0 Chapter 3 - Part 0 5

6 4 words (locations) x 4 bits (6-bit) RAM With Direct Decoding ( Enable for each word ) A0 Bus A Select all bits in a row (word) 4-bit (Write) Bus Bit Control I/P to all bits in a column Word (location) 0 puts 0s on all word select lines To all bits Problem: large RAMs require large decoders K Byte RAM: Decoder has K 0-input ANDs 4-bit (Read) Bus Represents 4 wires I/Ps to the OR Tri-state Can help! Chapter 3 - Part Solution: 2-D Decoding (2 Enables for each word) Uses 2 smaller (/2 size) decoders (, Y) K Words Memory (0-bit address: 0 address pins on the chip) Use two 5-to-32 decoders LS Half of address bits Decoder has 32 gates (5 I/Ps) 2 wires enable the selected word MS Half of address bits Each Decoder now has 32 gates (of 5 I/Ps each) Verify: This reduces # of AND gates needed for building decoders by a factor of 6 Chapter 3 - Part 2 6

7 Further Improvements for DRAM Address Multiplexing (reduced the # of address pins DRAMs are large in capacity Their large address needs a Large number of pins on the chip We can half the number of pins If we use separate registers for the row and column Addresses on the chip 64K = 2 6 locations (6-bit address) Row, then Column The 6 bit address is Supplied to the chip on only 8-pins:. Row part with the RAS signal 2. Column part with the CAS signal Helps reduce the physical size of DRAM chips 8 ½ normal size of the address bus of 6 bits 256 row enables column enables = 64 K bits In a 2-D array 256 rows x 256 columns Chapter 3 - Part 3 2. Logic Implementation Technologies Overview Why programmable logic? logic: Technologies and Configurations Examples of Logic Devices: Read-Only Memory (ROM) Array Logic (PAL) Logic Array (PLA) VLSI Logic Devices (Field Gate Arrays- FPGA) Chapter 3 - Part 4 7

8 The Rationale: Why Logic? Facts: (Economy of Scale) It is most economical to produce ICs in large volumes But: In many situations users require: ICs in smaller volumes Integrated Circuits Frequent changes to be done in the field, e.g. on the Firmware of a product under development A programmable logic device can be a good compromise: Produced in large quantities But also allows users to program it many times* (in the field) to accommodate changes on small volumes (*nowadays: erasable, reprogrammable, etc.) 5 Logic Concept Locations of connections inserted/removed by user determine the logic function implemented Chapter 3 - Part 6 8

9 Hardware Programming Technologies How connections are made: The ROM case ROM: In the Factory (not user-programmable) Cannot be erased or reprogrammed by user Programmed permanently through the VLSI mask during manufacturing of the chip PROM: only once, e.g. using fusible links (metal connections) many times (Erase & then Re-program) Ultra-Violet (UV) Erasable, e.g. EPROMs (off situ) Electrically Erasable, (in situ) e.g. EEPROMs Flash Memory Chapter 3 - Part 7 Logic Configurations: (SOm or SOP) All use AND-OR structure- differ in which is programmable AND OR How many Possibilities? Connections to the AND Connections to the OR Fixed Read Only (non-volatile) Memory (PROM) Fixed Array Logic (PAL) Logic Array (PLA) (Maximum flexibility) 8 9

10 ROM, PAL and PLA Configurations Inputs Fixed Connections PROM Fixed AND array (e.g. decoder) Connections (a) read-only memory (PROM) OR array Outputs Inputs Connections AND array Fixed Connections Fixed OR array Outputs PAL (b) array logic (PAL) device Inputs Connections AND array Connections OR array Outputs PLA (c) logic array (PLA) device Chapter 3 - Part 9 Wiring Conventions for Logic We deal with a large number of gates and gate inputs Need a more concise way of expressing gate circuits graphically Inputs Inputs (literals) A A B B wire F marks a connection, i.e. an input to the OR For the connections shown, F =? Chapter 3 - Part 20 0

11 a. Read Only Memory (ROM): &: Fixed- OR: Prog sum of fixed minterms Example: 8 4 PROM (n = 3 i/p (address) lines, m = 4 o/p lines) The fixed "AND" array is in a 3-to-8 decoder giving all 8 minterms "OR s. We use a single line to A B represent all inputs to an LSB C OR gate. An in the n I/Ps array indicates connecting the minterm to the OR Example: For input (A,B,C) = 00: output is (F 3,F 2,F,F 0 ) = input fixed ANDs give all 8 minterms m0 Exercise: Express the F as - Σm() - an algebraic expression in A,B,C A2 A A0 D0 D D2 D3 D4 D5 D6 D7 m O/Ps m7 F3 F2 F F0 2 n x m Connections 8 Minterms ROM 3-input 4-output CL cct seen differently This ROM implements this truth table Can look at it in several ways: - As an 8 words x 4-bit memory: at address 000 we permanently stored data 0 (non volatile) - As a look-up table: Enter I/P 000 you get corresponding O/P 0 - As an implementation of 3-I/P 4 O/P Combinational Logic (Using a decoder and 4 OR gate- Unit 3) Chapter 3 - Part 22

13 ROM-based Designs (Canonical Form), Som for Combinational & Sequential circuits For Combinational Circuits: ROMs can be used to implement a combinational circuit given its truth tables Example: Look up table example: 3 ; is a 4-bit Cuber 3 unsigned integer You should be able to determine the minimum ROM size (# of locations x word size) required for a given problem For Sequential Circuits: Use ROMs to implement the combinational part of the sequential circuit ROM-based Designs: Combinational Circuits: Individual O/Ps Example : Implement the following two combinational functions using a ROM F (,Y) = m (,2,3) F2 (,Y) = m (0,2) Solution should: Specify the smallest ROM required: ROM has n = 2 inputs ( 2 2 = 4 locations) and m = 2 outputs ( Each location has 2 bits) i.e. a 4 x 2 bit ROM Specifying the ROM data content (to be programmed into the ROM): Directly from the truth table of the two functions Show the connection diagram for this ROM (Decoder + ORs) Index Give Logic Diagram ROM Programming Table 3

14 ROM-based Design Examples: Combinational Circuits: Look-up Tables Example 2: 2 look-up table, is 3-bit binary number Specification: Use a ROM to implement a combinational circuit that accepts a 3-bit unsigned binary number at the input and generates its squared value at the output. 2 Formulation: 8 x 6 bits ROM, Truth Table Observations on the truth table:. Output B 0 = Input A 0 2. Output B = Always 0 8 Locations 6 bits No need to store data for B0 and B This reduces the size of the ROM required from 8 x 6 bits to 8 x 4 bits ROM-based Designs: Combinational Circuits : Look-up Tables Example 2, Continued Truth Table for Reduced ROM 8 Locations Implementations of the 2 Look-up Table: 4 bits 4

15 ROM-based Designs: Sequential Circuits Conventional Design Individual FFs ROM-Register Sequential Cct Design Very compact! Present State Assume D type FFs: D inputs ROM provides O/P per FF (= Next state!) Present State ROM Input (address) ROM Output (data stored at each address) ROM-based Designs: Sequential Circuit- D FF D-type The ROM Required Present State Inputs to FFs D- FF: per FF External I/P Careful with order of inputs Q2 Q LSB Q2+ Q+ Y External O/P Organization Assume D type FFs: ROM provides O/P per FF ROM Truth Table Derive the state diagram For this sequential circuit Present State I/P Next State O/P 5

16 Array Logic (PAL) PAL is the opposite of the ROM, having a set of programmable ANDs combined with a set of fixed ORs- ( = has selectable I/Ps) PAL has some outputs from OR terms that can be fed back (as internal inputs) to all other AND terms, allowing implementation as multi-level (>2) logic circuits Some PALs have outputs that can be complemented, allowing F implementation as a POS: F = F Advantages over ROM SOP Allows optimized implementation as Sum of a few Products (usually not all minterms would be available) For a given total # of gates, a PAL can support larger n and m than a ROM Limitation:. Functions with many products: may not be possible 2. Sharing of products between sections is not possible! multiple generation! Chapter 3 - Part 32 6

17 PAL Example sum of > 3 products Remove all unused connections Product term AND gates inputs A A B B C C D D W W For this totally unused product, Leave all connections intact A Why? W All fuses intact (always = 5 0) F: Deceptively 2-level! but its is not! 5 F Opposite of ROM: AND I/Ps: programmable OR I/Ps: Fixed B Handling a sum of > 3 products F2 C For a totally unused product, Leave all connections intact D 0 2 A A B B C C D D W W Fuse intact Fuse blown For Unused Section: O/P = 0 or? Chapter 3 - Part 33 PAL Programming Table Equations: F = A B C + A B C + A B C + ABC F2 = AB + BC + AC F was factored - has four terms (> 3) Factor out last two terms as W Product term AND Inputs A B C D W 0 0 Keep True & remove other. 2 Full gate not used. 3 Keep both * * * * * Keep Complement. & remove other Remove both connections Outputs W = A BC + ABC F = = A B C + AB C + W = W PAL Programming Table F2 = Y = AB + BC +AC Section PAL comes with all Connections made. 0 Unused Section Connections that are 2 Keep All Connections 0 O/P not needed should be removed How many connections are removed for product Chapter?, for 3 product - Part 3? 34 7

18 c. Logic Array (PLA) Programming at both the product and the sum levels n inputs (n = 3) A B What are the equations for F and F 2? Note: Now Products can be shared among O/Ps C 3 groups of Connections, Get size of each group of connections for a PLA with: n inputs, p products, m outputs CC B B AA 0 PLA with 3-inputs, 4 product terms, 2-outputs, & programmable output inversions A B B C A C A B p products (p = 4) Fuse intact Fuse blown Programming the Output inversions F m outputs (m = 2) F 2 F 2 Express F2 as a SOP Chapter and 3 POS - Part 35 Logic Array (PLA) Compared to ROMs and PALs, PLA is the most flexible & economical programmable device: having programmable ANDs, programmable ORs, and even programmable output inversions! Advantages More concise implementations than ROM Uses K-map optimized products Allows larger 2-level sums than with PALs: All product terms are available for sharing by all summing Ors You do not have to generate a product more than once as in PAL PLAs have outputs that can be complemented, so a SOP can be that of either F or F, whichever proves more optimal - globally But still The limited # of product terms can limit the application of a PLA. Solution: Use global multiple-output optimization to reduce the number of product terms required to fit it into the PLA. Chapter 3 - Part 36 8

19 PLA Global Optimization Example F(A,B,C), F2(A,B,C), PLA: (3 inputs, 4 products, 2 outputs with programmable o/p inversion) BC K-map A specifications 0 0 How can this be implemented A with only four products? Complete the programming table Choose implementations (F or F) that has the largest # of shared products! Is this PLA enough if we choose to implement F & F2 directly? C F = A BC + A B C + A B C F = AB + AC + BC + A B C AB AC BC ABC B PLA programming table Product term Inputs A B C BC A A F map C F2 map F 2 = AB + AC + BC F 2 = AC + AB + BC Outputs (C) F 0 (T) F 2 B 0 SUM (OR) Programming (Vertically) Product (AND) Programming (horizontally) Chapter 3 - Part 37 Logic Array (PLA) Example, Contd. A B C Good sharing of products! The 4 products AB Give algebraic expressions of F and F2 C C B B A A F2 F We implement F as a SOP Using the PLA and then invert it, as this is more economical AC BC ABC Fuse intact Fuse blown 0 But we actually need F as an O/P, not F- So invert F With the OR F F 2 Chapter 3 - Part 38 9

### Chapter 6 Selected Design Topics

Logic and Computer Design Fundamentals Chapter 6 Selected Design Topics Part 4 Programmable Implementation Technologies Charles Kime & Thomas Kaminski 2008 Pearson Education, Inc. (Hyperlinks are active

### Memory and Programmable Logic

Memory and Programmable Logic Memory units allow us to store and/or retrieve information Essentially look-up tables Good for storing data, not for function implementation Programmable logic device (PLD),

### Semiconductor Memories: RAMs and ROMs

Semiconductor Memories: RAMs and ROMs Lesson Objectives: In this lesson you will be introduced to: Different memory devices like, RAM, ROM, PROM, EPROM, EEPROM, etc. Different terms like: read, write,

### Lecture 13: Memory and Programmable Logic

Lecture 13: Memory and Programmable Logic Syed M. Mahmud, Ph.D ECE Department Wayne State University Aby K George, ECE Department, Wayne State University Contents Introduction Random Access Memory Memory

### Concept of Memory. The memory of computer is broadly categories into two categories:

Concept of Memory We have already mentioned that digital computer works on stored programmed concept introduced by Von Neumann. We use memory to store the information, which includes both program and data.

### Microcontroller Systems. ELET 3232 Topic 11: General Memory Interfacing

Microcontroller Systems ELET 3232 Topic 11: General Memory Interfacing 1 Objectives To become familiar with the concepts of memory expansion and the data and address bus To design embedded systems circuits

### Presentation 4: Programmable Combinational Devices

Presentation 4: Programmable Combinational Devices Asst. Prof Dr. Ahmet ÖZKURT DEUEEE Based on the Presentation by Prof. Kim, Young Ho Dept. of Information Computer Engineering E-mail : yhkim@hyowon.cs.pusan.ac.kr

### ELCT 912: Advanced Embedded Systems

Advanced Embedded Systems Lecture 2: Memory and Programmable Logic Dr. Mohamed Abd El Ghany, Memory Random Access Memory (RAM) Can be read and written Static Random Access Memory (SRAM) Data stored so

### Memory and Programmable Logic

Memory and Programmable Logic Mano & Ciletti Chapter 7 By Suleyman TOSUN Ankara University Outline RAM Memory decoding Error detection and correction ROM Programmable Logic Array (PLA) Programmable Array

### 8051 INTERFACING TO EXTERNAL MEMORY

8051 INTERFACING TO EXTERNAL MEMORY Memory Capacity The number of bits that a semiconductor memory chip can store Called chip capacity It can be in units of Kbits (kilobits), Mbits (megabits), and so on

### PROGRAMMABLE LOGIC DEVICES

PROGRAMMABLE LOGIC DEVICES Programmable logic devices (PLDs) are used for designing logic circuits. PLDs can be configured by the user to perform specific functions. The different types of PLDs available

### Review: Chip Design Styles

MPT-50 Introduction to omputer Design SFU, Harbour entre, Spring 007 Lecture 9: Feb. 6, 007 Programmable Logic Devices (PLDs) - Read Only Memory (ROM) - Programmable Array Logic (PAL) - Programmable Logic

### UNIT V (PROGRAMMABLE LOGIC DEVICES)

UNIT V (PROGRAMMABLE LOGIC DEVICES) Introduction There are two types of memories that are used in digital systems: Random-access memory(ram): perform both the write and read operations. Read-only memory(rom):

### Read-only memory Implementing logic with ROM Programmable logic devices Implementing logic with PLDs Static hazards

Points Addressed in this Lecture Lecture 7: ROM Programmable Logic Devices Professor Peter Cheung Department of EEE, Imperial College London Read-only memory Implementing logic with ROM Programmable logic

### Basic Organization Memory Cell Operation. CSCI 4717 Computer Architecture. ROM Uses. Random Access Memory. Semiconductor Memory Types

CSCI 4717/5717 Computer Architecture Topic: Internal Memory Details Reading: Stallings, Sections 5.1 & 5.3 Basic Organization Memory Cell Operation Represent two stable/semi-stable states representing

### UNIT - V MEMORY P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT

UNIT - V MEMORY P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents Memory: Introduction, Random-Access memory, Memory decoding, ROM, Programmable Logic Array, Programmable Array Logic, Sequential programmable

Read and Write Cycles The read cycle is shown. Figure 41.1a. The RAS and CAS signals are activated one after the other to latch the multiplexed row and column addresses respectively applied at the multiplexed

### DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422)

COURSE / CODE DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) Memory In computing, memory refers to the computer hardware devices used to store information for immediate use

### SECTION-A

M.Sc(CS) ( First Semester) Examination,2013 Digital Electronics Paper: Fifth ------------------------------------------------------------------------------------- SECTION-A I) An electronics circuit/ device

### MEMORY AND PROGRAMMABLE LOGIC

MEMORY AND PROGRAMMABLE LOGIC Memory is a device where we can store and retrieve information It can execute a read and a write Programmable Logic is a device where we can store and retrieve information

### Chapter 5 Internal Memory

Chapter 5 Internal Memory Memory Type Category Erasure Write Mechanism Volatility Random-access memory (RAM) Read-write memory Electrically, byte-level Electrically Volatile Read-only memory (ROM) Read-only

### ECE/Comp Sci 352 Digital Systems Fundamentals Kewal K. Saluja and Yu Hen Hu Spring Logic and Computer Design Fundamentals.

University of Wisconsin - Madison ECE/Comp Sci 352 Digital Systems Fundamentals Kewal K. Saluja and Yu Hen Hu Spring 2002 Chapter 6 Part 2 Memories & Programmable Logic Devices Originals by: Charles R.

### DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE4220. PROGRAMMABLE LOGIC DEVICES (PLDs)

COURSE / CODE DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE4220 PROGRAMMABLE LOGIC DEVICES (PLDs) A PLD, or programmable logic device, is an electronic component that is used

### MEMORY BHARAT SCHOOL OF BANKING- VELLORE

A memory is just like a human brain. It is used to store data and instructions. Computer memory is the storage space in computer where data is to be processed and instructions required for processing are

### Logic and Computer Design Fundamentals. Chapter 8 Memory Basics

Logic and Computer Design Fundamentals Memory Basics Overview Memory definitions Random Access Memory (RAM) Static RAM (SRAM) integrated circuits Arrays of SRAM integrated circuits Dynamic RAM (DRAM) Read

### CSEE 3827: Fundamentals of Computer Systems. Storage

CSEE 387: Fundamentals of Computer Systems Storage The big picture General purpose processor (e.g., Power PC, Pentium, MIPS) Internet router (intrusion detection, pacet routing, etc.) WIreless transceiver

### CHAPTER 9 MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES

CHAPTER 9 MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES This chapter in the book includes: Objectives Study Guide 9.1 Introduction 9.2 Multiplexers 9.3 Three-State Buffers 9.4 Decoders and Encoders

### Memory and Programmable Logic

Digital Circuit Design and Language Memory and Programmable Logic Chang, Ik Joon Kyunghee University Memory Classification based on functionality ROM : Read-Only Memory RWM : Read-Write Memory RWM NVRWM

### Introduction to Programmable Logic Devices (Class 7.2 2/28/2013)

Introduction to Programmable Logic Devices (Class 7.2 2/28/2013) CSE 2441 Introduction to Digital Logic Spring 2013 Instructor Bill Carroll, Professor of CSE Today s Topics Complexity issues Implementation

### Lecture-7 Characteristics of Memory: In the broad sense, a microcomputer memory system can be logically divided into three groups: 1) Processor

Lecture-7 Characteristics of Memory: In the broad sense, a microcomputer memory system can be logically divided into three groups: 1) Processor memory 2) Primary or main memory 3) Secondary memory Processor

### Programmable Logic Devices

Programmable Logic Devices Programmable Logic Devices Fig. (1) General structure of PLDs Programmable Logic Device (PLD): is an integrated circuit with internal logic gates and/or connections that can

### B.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN

B.Tech II Year I Semester () Regular Examinations December 2014 (Common to IT and CSE) (a) If 1010 2 + 10 2 = X 10, then X is ----- Write the first 9 decimal digits in base 3. (c) What is meant by don

### VALLIAMMAI ENGINEERING COLLEGE. SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS

VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur-603 203 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS YEAR / SEMESTER: II / III ACADEMIC YEAR: 2015-2016 (ODD

### Digital Design, Kyung Hee Univ. Chapter 7. Memory and Programmable Logic

Chapter 7. Memory and Programmable Logic 1 7.1 Introduction Memory unit: A device to which binary information is transferred for storage and from which information is retrieved when needed for processing

### Chapter 6 (Lect 3) Counters Continued. Unused States Ring counter. Implementing with Registers Implementing with Counter and Decoder

Chapter 6 (Lect 3) Counters Continued Unused States Ring counter Implementing with Registers Implementing with Counter and Decoder Sequential Logic and Unused States Not all states need to be used Can

### Memory Overview. Overview - Memory Types 2/17/16. Curtis Nelson Walla Walla University

Memory Overview Curtis Nelson Walla Walla University Overview - Memory Types n n n Magnetic tape (used primarily for long term archive) Magnetic disk n Hard disk (File, Directory, Folder) n Floppy disks

### Programmable Logic Devices (PLDs)

Programmable Logic Devices (PLDs) 212: Digital Design I, week 13 PLDs basically store binary information in a volatile/nonvolatile device. Data is specified by designer and physically inserted (Programmed)

### Principles of Digital Techniques PDT (17320) Assignment No State advantages of digital system over analog system.

Assignment No. 1 1. State advantages of digital system over analog system. 2. Convert following numbers a. (138.56) 10 = (?) 2 = (?) 8 = (?) 16 b. (1110011.011) 2 = (?) 10 = (?) 8 = (?) 16 c. (3004.06)

### Memory & Simple I/O Interfacing

Chapter 10 Memory & Simple I/O Interfacing Expected Outcomes Explain the importance of tri-state devices in microprocessor system Distinguish basic type of semiconductor memory and their applications Relate

### Embedded Systems Design: A Unified Hardware/Software Introduction. Outline. Chapter 5 Memory. Introduction. Memory: basic concepts

Hardware/Software Introduction Chapter 5 Memory Outline Memory Write Ability and Storage Permanence Common Memory Types Composing Memory Memory Hierarchy and Cache Advanced RAM 1 2 Introduction Memory:

### Embedded Systems Design: A Unified Hardware/Software Introduction. Chapter 5 Memory. Outline. Introduction

Hardware/Software Introduction Chapter 5 Memory 1 Outline Memory Write Ability and Storage Permanence Common Memory Types Composing Memory Memory Hierarchy and Cache Advanced RAM 2 Introduction Embedded

### William Stallings Computer Organization and Architecture 6th Edition. Chapter 5 Internal Memory

William Stallings Computer Organization and Architecture 6th Edition Chapter 5 Internal Memory Semiconductor Memory Types Semiconductor Memory RAM Misnamed as all semiconductor memory is random access

### DIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES

DIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES 1 Learning Objectives 1. Explain the function of a multiplexer. Implement a multiplexer using gates. 2. Explain the

### COMP3221: Microprocessors and. and Embedded Systems. Overview. Lecture 23: Memory Systems (I)

COMP3221: Microprocessors and Embedded Systems Lecture 23: Memory Systems (I) Overview Memory System Hierarchy RAM, ROM, EPROM, EEPROM and FLASH http://www.cse.unsw.edu.au/~cs3221 Lecturer: Hui Wu Session

### Menu. word size # of words byte = 8 bits

Menu LSI Components >Random Access Memory (RAM) Static RAM (SRAM) Dynamic RAM (DRAM) Read-Only Memory (ROM) Look into my... See figures from Lam text on web: RAM_ROM_ch6.pdf 1 It can be thought of as 1

### Code No: R Set No. 1

Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2006 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems

### ECSE-2610 Computer Components & Operations (COCO)

ECSE-2610 Computer Components & Operations (COCO) Part 18: Random Access Memory 1 Read-Only Memories 2 Why ROM? Program storage Boot ROM for personal computers Complete application storage for embedded

### P-2 Digital Design & Applications

P-2 Digital Design & Applications Semiconductor Memory (Unit-V) By: A K Verma SOS in Electronics & Photonics Pt. Ravishankar Shukla University, Raipur (C.G.) 1 What is Memory? In computing, memory refers

### CS 320 February 2, 2018 Ch 5 Memory

CS 320 February 2, 2018 Ch 5 Memory Main memory often referred to as core by the older generation because core memory was a mainstay of computers until the advent of cheap semi-conductor memory in the

### COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS UNIT I

KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS YEAR / SEM: III / V UNIT I NUMBER SYSTEM & BOOLEAN ALGEBRA

### Slide Set 10. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary

Slide Set 10 for ENEL 353 Fall 2017 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary Fall Term, 2017 SN s ENEL 353 Fall 2017 Slide Set 10 slide

### Chapter 8 Memory Basics

Logic and Computer Design Fundamentals Chapter 8 Memory Basics Charles Kime & Thomas Kaminski 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Overview Memory definitions Random Access

### R10. II B. Tech I Semester, Supplementary Examinations, May

SET - 1 1. a) Convert the following decimal numbers into an equivalent binary numbers. i) 53.625 ii) 4097.188 iii) 167 iv) 0.4475 b) Add the following numbers using 2 s complement method. i) -48 and +31

### ELCT 501: Digital System Design

ELCT 501: Digital System Lecture 3: Memory and Programmable Logic (continue) Dr. Mohamed Abd El Ghany, Memory Model 32-bit address space can address up to 4 GB (2 32 ) different memory locations 0x00000000

### II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION. Answer ONE question from each unit.

Hall Ticket Number: 14CS IT303 November, 2017 Third Semester Time: Three Hours Answer Question No.1 compulsorily. II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION Common for CSE & IT Digital Logic

### UMBC. Select. Read. Write. Output/Input-output connection. 1 (Feb. 25, 2002) Four commonly used memories: Address connection ... Dynamic RAM (DRAM)

Memory Types Two basic types: ROM: Read-only memory RAM: Read-Write memory Four commonly used memories: ROM Flash (EEPROM) Static RAM (SRAM) Dynamic RAM (DRAM) Generic pin configuration: Address connection

### Summer 2003 Lecture 18 07/09/03

Summer 2003 Lecture 18 07/09/03 NEW HOMEWORK Instruction Execution Times: The 8088 CPU is a synchronous machine that operates at a particular clock frequency. In the case of the original IBM PC, that clock

### END-TERM EXAMINATION

(Please Write your Exam Roll No. immediately) END-TERM EXAMINATION DECEMBER 2006 Exam. Roll No... Exam Series code: 100919DEC06200963 Paper Code: MCA-103 Subject: Digital Electronics Time: 3 Hours Maximum

### I 4 I 3 I 2 I 1 I 0 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 T-125. ROM Truth Table (Partial) 1997 by Prentice-Hall, Inc.

997 by Prentice-Hall, Inc. ano & Kime Upper Saddle River, New Jersey 7458 T-5 Inputs Outputs I 4 I 3 I I I A 7 A 6 A 5 A 4 A 3 A A A...... RO Truth Table (Partial) 997 by Prentice-Hall, Inc. ano & Kime

### Computer Organization. 8th Edition. Chapter 5 Internal Memory

William Stallings Computer Organization and Architecture 8th Edition Chapter 5 Internal Memory Semiconductor Memory Types Memory Type Category Erasure Write Mechanism Volatility Random-access memory (RAM)

### Organization. 5.1 Semiconductor Main Memory. William Stallings Computer Organization and Architecture 6th Edition

William Stallings Computer Organization and Architecture 6th Edition Chapter 5 Internal Memory 5.1 Semiconductor Main Memory 5.2 Error Correction 5.3 Advanced DRAM Organization 5.1 Semiconductor Main Memory

CREATED BY M BILAL & Arslan Ahmad Shaad Visit: www.techo786.wordpress.com Q1: Define microprocessor? Short Questions Chapter No 01 Fundamental Concepts Microprocessor is a program-controlled and semiconductor

### IT T35 Digital system desigm y - ii /s - iii

UNIT - IV Sequential Logic II Memory and Programmable Logic: Random Access Memory memory decoding error detection and correction Read Only Memory Programmable Logic Arrays Programmable Array Logic. PRE-REQUISITE

### Code No: R Set No. 1

Code No: R059210504 Set No. 1 II B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science

### Programmable Logic Devices UNIT II DIGITAL SYSTEM DESIGN

Programmable Logic Devices UNIT II DIGITAL SYSTEM DESIGN 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 2 Implementation in Sequential Logic 2 PAL Logic Implementation Design Example: BCD to Gray Code Converter A B

### CENG 4480 L09 Memory 3

CENG 4480 L09 Memory 3 Bei Yu Chapter 11 Memories Reference: CMOS VLSI Design A Circuits and Systems Perspective by H.E.Weste and D.M.Harris 1 Memory Arrays Memory Arrays Random Access Memory Serial Access

### Programmable Logic Devices. Programmable Read Only Memory (PROM) Example

Programmable Logic Devices Programmable Logic Devices (PLDs) are the integrated circuits. They contain an array of AND gates & another array of OR gates. There are three kinds of PLDs based on the type

### Injntu.com Injntu.com Injntu.com R16

1. a) What are the three methods of obtaining the 2 s complement of a given binary (3M) number? b) What do you mean by K-map? Name it advantages and disadvantages. (3M) c) Distinguish between a half-adder

### Sir Sadiq s computer notes for class IX. Chapter no 4. Storage Devices

17 Q: Define Computer memory or storage. Ans: Memory: Memory refers to the place where data is kept for later use. For example, a human being has a memory where he/she stores the things that can be recalled

### DKT 122/3 DIGITAL SYSTEM 1

Company LOGO DKT 122/3 DIGITAL SYSTEM 1 BOOLEAN ALGEBRA (PART 2) Boolean Algebra Contents Boolean Operations & Expression Laws & Rules of Boolean algebra DeMorgan s Theorems Boolean analysis of logic circuits

### Chapter 4 Main Memory

Chapter 4 Main Memory Course Outcome (CO) - CO2 Describe the architecture and organization of computer systems Program Outcome (PO) PO1 Apply knowledge of mathematics, science and engineering fundamentals

### Experiment 3: Logic Simplification

Module: Logic Design Name:... University no:.. Group no:. Lab Partner Name: Mr. Mohamed El-Saied Experiment : Logic Simplification Objective: How to implement and verify the operation of the logical functions

### Combinational Logic Circuits

Chapter 3 Combinational Logic Circuits 12 Hours 24 Marks 3.1 Standard representation for logical functions Boolean expressions / logic expressions / logical functions are expressed in terms of logical

### KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK NAME OF THE SUBJECT: EE 2255 DIGITAL LOGIC CIRCUITS

KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK NAME OF THE SUBJECT: EE 2255 DIGITAL LOGIC CIRCUITS YEAR / SEM: II / IV UNIT I BOOLEAN ALGEBRA AND COMBINATIONAL

### CMPE 415 Programmable Logic Devices FPGA Technology I

Department of Computer Science and Electrical Engineering CMPE 415 Programmable Logic Devices FPGA Technology I Prof. Ryan Robucci Some slides (blue-frame) developed by Jim Plusquellic Some images credited

### Memory & Logic Array. Lecture # 23 & 24 By : Ali Mustafa

Memory & Logic Array Lecture # 23 & 24 By : Ali Mustafa Memory Memory unit is a device to which a binary information is transferred for storage. From which information is retrieved when needed. Types of

### Very Large Scale Integration (VLSI)

Very Large Scale Integration (VLSI) Lecture 6 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. Madian-VLSI 1 Contents FPGA Technology Programmable logic Cell (PLC) Mux-based cells Look up table PLA

### CS24: INTRODUCTION TO COMPUTING SYSTEMS. Spring 2017 Lecture 13

CS24: INTRODUCTION TO COMPUTING SYSTEMS Spring 2017 Lecture 13 COMPUTER MEMORY So far, have viewed computer memory in a very simple way Two memory areas in our computer: The register file Small number

### Address connections Data connections Selection connections

Interface (cont..) We have four common types of memory: Read only memory ( ROM ) Flash memory ( EEPROM ) Static Random access memory ( SARAM ) Dynamic Random access memory ( DRAM ). Pin connections common

### Fig. 6-1 Conventional and Array Logic Symbols for OR Gate

6- (a) Conventional symbol (b) Array logic symbol Fig. 6- Conventional and Array Logic Symbols for OR Gate 2 Prentice Hall, Inc. 6-2 k address lines Read n data input lines emory unit 2 k words n bits

### William Stallings Computer Organization and Architecture 8th Edition. Chapter 5 Internal Memory

William Stallings Computer Organization and Architecture 8th Edition Chapter 5 Internal Memory Semiconductor Memory The basic element of a semiconductor memory is the memory cell. Although a variety of

### Lecture 20: CAMs, ROMs, PLAs

Lecture 2: CAMs, ROMs, PLAs Outline Content-Addressable Memories Read-Only Memories Programmable Logic Arrays 2: CAMs, ROMs, and PLAs CMOS VLSI Design 4th Ed. 2 CAMs Extension of ordinary memory (e.g.

### Introduction read-only memory random access memory

Memory Interface Introduction Simple or complex, every microprocessorbased system has a memory system. Almost all systems contain two main types of memory: read-only memory (ROM) and random access memory

### Model EXAM Question Bank

VELAMMAL COLLEGE OF ENGINEERING AND TECHNOLOGY, MADURAI Department of Information Technology Model Exam -1 1. List the main difference between PLA and PAL. PLA: Both AND and OR arrays are programmable

### MODULE 12 APPLICATIONS OF MEMORY DEVICES:

Introduction to Digital Electronic Design, Module 12 Application of Memory Devices 1 MODULE 12 APPLICATIONS OF MEMORY DEVICES: CONCEPT 12-1: REVIEW OF HOW MEMORY DEVICES WORK Memory consists of two parts.

### Memory memories memory

Memory Organization Memory Hierarchy Memory is used for storing programs and data that are required to perform a specific task. For CPU to operate at its maximum speed, it required an uninterrupted and

1 Memory + 2 Location Internal (e.g. processor registers, cache, main memory) External (e.g. optical disks, magnetic disks, tapes) Capacity Number of words Number of bytes Unit of Transfer Word Block Access

### ORG ; Week8. Memory and Memory Interfacing

Dec 10 Hex A Bin 00001010 ORG ; Week8 Memory and Memory Interfacing OBJECTIVES this chapter enables the student to: Define the terms capacity, organization, and speed as used in semiconductor memories.

Computer Architecture Prof. Dr. Nizamettin AYDIN naydin@yildiz.edu.tr nizamettinaydin@gmail.com Internal Memory http://www.yildiz.edu.tr/~naydin 1 2 Outline Semiconductor main memory Random Access Memory

### Chapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1>

Chapter 5 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 5 Chapter 5 :: Topics Introduction Arithmetic Circuits umber Systems Sequential Building

### Logical Design of Digital Systems

.5.27 Lecture 3 Summer Semester 27 Table of Content. Combinational circuit design 2. Elementary combinatorial circuits for data transmission 3. Memories 3. Semiconductor memory classification s 3.2. General

### Random Access Memory (RAM)

Random Access Memory (RAM) EED2003 Digital Design Dr. Ahmet ÖZKURT Dr. Hakkı YALAZAN 1 Overview Memory is a collection of storage cells with associated input and output circuitry Possible to read and write

### Computer Structure. Unit 2: Memory and programmable devices

Computer Structure Unit 2: Memory and programmable devices Translated from Francisco Pérez García (fperez at us.es) by Mª Carmen Romero (mcromerot at us.es, Office G1.51, 954554324) Electronic Technology

Summary Boolean Addition In Boolean algebra, a variable is a symbol used to represent an action, a condition, or data. A single variable can only have a value of or 0. The complement represents the inverse

### PLAs & PALs. Programmable Logic Devices (PLDs) PLAs and PALs

PLAs & PALs Programmable Logic Devices (PLDs) PLAs and PALs PLAs&PALs By the late 1970s, standard logic devices were all the rage, and printed circuit boards were loaded with them. To offer the ultimate

### Lecture Objectives. Introduction to Computing Chapter 0. Topics. Numbering Systems 04/09/2017

Lecture Objectives Introduction to Computing Chapter The AVR microcontroller and embedded systems using assembly and c Students should be able to: Convert between base and. Explain the difference between

### INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad

INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad - 500 043 COMPUTER SCIENCE AND ENGINEERING TUTORIAL QUESTION BANK Name : DIGITAL LOGIC DESISN Code : AEC020 Class : B Tech III Semester

### Chapter 13 Programmable Logic Device Architectures

Chapter 13 Programmable Logic Device Architectures Chapter 13 Objectives Selected areas covered in this chapter: Describing different categories of digital system devices. Describing different types of