CMOS Logic Circuit Design Link( リンク ): センター教官講義ノートの下 CMOS 論理回路設計

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1 CMOS Logic Circuit Design Link( リンク ): センター教官講義ノートの下 CMOS 論理回路設計 Memory Circuits (Part 1) Overview of Memory Types Memory with Address-Based Access Principle of Data Access by Address Decoding Volatile Random Read/Write-Access Memory Non-Volatile Random Read-Only Memory Non-Volatile Random Read/Write-Access Memory Memory with Content-Based Access Principle of Data Access by Content Matching Conventional Content-Addressable Memory Mattausch, CMOS Design, H19/6/29 1

2 Overview of the Memory Types Semiconductor Memory Address-Based Access Content-Based Access Volatile Storage Non-Volatile Storage Exact Match Best Match DRAM Read-Only Access Read/Write Access Conventional CAM Ternary CAM SRAM EEPROM Flash EEPROM Distance-Measure Based CAM ROM FRAM MRAM Most widely used: Today in use: Today today under development: Mattausch, CMOS Design, H19/6/29 2

3 Memory with Address-Based Access - Principle of Data Access by Address Decoding Row Decoding Column Decoding - Volatile Random Read/Write-Access Memory Static Random Access Memory (SRAM) Dynamic Random Access Memory (DRAM) Mattausch, CMOS Design, H19/6/29 3

4 Principle of Data Access by Address Decoding word lines 2 k columns memory cell row decoder 2 n-k rows n-k k n Address column decoder read/write amplifiers Data bit lines All conventional memory circuits use a positive binary address to identify and access the stored data. Mattausch, CMOS Design, H19/6/29 4

5 Single Stage Row Decoder AND-decoder for 2 address bits 2-input AND circuit VDD PMOS-transistor NMOS-transistor VSS The row-decoder has to activate exactly one row for each row address. With an n-bit address 1 of 2 n rows is selectable. Mattausch, CMOS Design, H19/6/29 5

6 Pre-decode Stage Two Stage Row Decoder Final Row- Decode Stage 2-stage row-decoder circuit for a 3-bit address Pre-decoding in a first decoder stage keeps the AND-gate fan-in small. Shorter delay times result. Mattausch, CMOS Design, H19/6/29 6

7 Tree Column Decoder (Example SRAM) Inverted Selected Data to Sense Amplifier Normal Selected Data The column decoder connects the selected data column to the sense amplifier. The tree decoder has the best area efficiency but a large delay for many column-address bits. Mattausch, CMOS Design, H19/6/29 7

8 Decoded Column Decoder (Example SRAM) bit <0> bit <1> bit <2> bit <3> - bit <0> - bit <1> - bit <2> - bit <3> -Data Data The decoded column decoder reduces the number of stages through which the data signal has to pass. Area efficiency is lower but access time is shorter than with the tree decoder. Mattausch, CMOS Design, H19/6/29 8

9 Memory with Address-Based Access - Principle of Data Access by Address Decoding Row Decoding Column Decoding - Volatile Random Read/Write-Access Memory Static Random Access Memory (SRAM) Dynamic Random Access Memory (DRAM) Mattausch, CMOS Design, H19/6/29 9

10 Basic SRAM Architecture Elements Additional to Decoding Shown is just one bit of the complete SRAM! The SRAM architecture requires also the elements RAM cell, bit line conditioning, sense amplifier and write buffers. Mattausch, CMOS Design, H19/6/29 10

11 SRAM Storage Cells 6 transistor CMOS SRAM cell 4 transistor NMOS SRAM cell A 6-transistor CMOS SRAM cell has lower power dissipation, but requires larger area than a 4-transistor NMOS SRAM cell. Mattausch, CMOS Design, H19/6/29 11

12 SRAM Read Operation Read Operation Circuitry VDD Signal Waveforms (Voltages) and Critical Circuit Part for Reading static-load bitline conditioning word VSS data current mirror sense amplifier bitline voltage cell-internal voltage The SRAM read operation requires a careful combined design of memory cell, bitline conditioning and sense amplifier. Mattausch, CMOS Design, H19/6/29 12

13 SRAM Write Operation Write Operation Circuitry Signal Waveforms (Voltages) for Writing static-load bitline conditioning write buffer and selector The SRAM write operation requires enough driving power of the buffer and careful design of transistors N 1 /N 2 and N 3 /N 4. Mattausch, CMOS Design, H19/6/29 13

14 4 Transistor NMOS DRAM Cell DRAM Storage Cells 3 Transistor NMOS DRAM Cell 2 Transistor NMOS DRAM Cell (1 Transistor used as Capacitor) 1 Transistor + Capacitor NMOS DRAM Cell (Free Capacitor Construction Method ) Today only the 1 transistor DRAM cell is used in DRAM chips. Mattausch, CMOS Design, H19/6/29 14

15 DRAM Storage Cells Capacitor Plate (Poly 2) Inversion Layer Planar Capacitor Cell Capacitor Plate (Poly 2) Insulator Inversion Layer Trench Capacitor Cell Stacked Capacitor Cell Today the stacked capacitor cell is most widely used. Mattausch, CMOS Design, H19/6/29 15

16 Basic DRAM Architecture RAS (Row Address Select) Buffer Row-Address Row Decoder 2 n-k Field of Memory Cells φ p, φ a Timing Generator 2 k Data In Input Buffer Write Circuit Multiplexer Sense Amp. Output Driver Data Out Ak+1 - An Column Decoder Column-Address Buffer Address Signals A1-An A1 - Ak CAS (Column Address Select) The dynamic memory cell requires a complicated timing generator and periodical refresh of the stored data. Mattausch, CMOS Design, H19/6/29 16

17 DRAM Read/Write Circuitry Lower dummy storage cell Bitline conditioning Upper dummy storage cell Upper and lower field of storage cell The DRAM Read/Write circuitry is more complicated than that of an SRAM. Write circuit Sense amp and Output driver Preamplifier and Multiplexer Dummy storage cells and preamplifiers are used. Mattausch, CMOS Design, H19/6/29 17

18 Memory with Address-Based Access - Non-Volatile Random Read-Only-Access Memory Conventional Read Only Memory (ROM) - Non-Volatile Random Read/Write-Access Memory Electrically Erasable Programmable ROM (EEPROM) Mattausch, CMOS Design, H19/6/29 18

19 Conventional ROM Architecture ROM Structure Example Storage Cell W = 1 Field of Memory Cells B W Decoded Column Decoder (select stage) = 0 B Single Stage Row Decoder Decoded Column Decoder (decode stage) Data stored in conventional ROMs needs presence/absence of hardware and thus cannot be changed after fabrication. Mattausch, CMOS Design, H19/6/29 19

20 EEPROM Principle: Floating Gate Transistor Storage Element in ROM (Normal NMOS Transistor) Storage Element in EEPROM (Floating Gate NMOS Transistor) Gate Gate Floating Gate Source Drain Source Drain Logic 1 State in EEPROM (No Electrons on Floating Gate) Logic 0 State in EEPROM (Electrons on Floating Gate) Source Gate Floating Gate Drain = 1! Source Gate Floating Gate Drain = 0! Information is stored in the EEPROM by changing the charge on the floating gate, i.e. the transistor threshold voltage. Mattausch, CMOS Design, H19/6/29 20

21 Programming Method of the Floating Gate Floating Gate (Programming) Floating Gate (Erasing) V prog Gate VSS Gate Source Floating Gate Drain n + n + Source Floating Gate Drain n + n + Bulk p - Bulk p - VSS V prog Information storage on the floating gate requires the on-chip generation of a relatively high programming voltage (~ 20V). Mattausch, CMOS Design, H19/6/29 21

22 Memory with Content-Based Access - Principle of Data Access by Content Matching - Conventional Content Addressable Memory (CAM) Mattausch, CMOS Design, H19/6/29 22

23 Principle of Memory Access by Content Matching Input Data IN={IN 1, IN 2,,IN W } Reference Data 1 REF 1 ={REF 11, REF 12,, REF 1W } Distance Calculation D 1 (IN, REF 1 ) Reference Data 2 REF 2 ={REF 21, REF 22,, REF 2W } Distance Calculation D 2 (IN, REF 2 ) Best Match Calculation MIN(D 1,,D R ) Winner of Content Matching Reference Data R REF R ={REF R1, REF R2,, REF RW } Distance Calculation D R (IN, REF R ) High content-matching performance requires a parallel distance calculation for all reference data. Mattausch, CMOS Design, H19/6/29 23

24 Common Distance Measures and Applications Common Distance Measure Important Applications D i = W j =1 IN j REF ij Data-base systems with fast data retrieval. D i is called Hamming distance, if IN j and REF ij are 1-bit binaries. D i is called Manhattan distance, if IN j and REF ij are n-bit binaries with n>1. Computers with high performance memory hierarchy (e.g. cache and virtual memory). Speech and picture recognition or language translation with code books. Intelligent systems with recognition and learning capability. Content-based memory access is an important concept for realizing intelligent systems in the future information society. Mattausch, CMOS Design, H19/6/29 24

25 Conventional Content-Addressable Memory Conventional Distance Measure Conventional CAM Cell D i = W IN j REF ij = 0 j =1 -cell cell 6 Transistor SRAM Cell Conventional hardware for content-addressable memories can only retrieve data with distance zero to the input. EXOR bit cell ( ) Distributed NOR (Pull-Down Transistor) Capabilities of the conventional content-addressable memory (CAM) are very limited, because only D i =0 can be evaluated. Mattausch, CMOS Design, H19/6/29 25

26 Basic Hardware Structure of Conventional CAM Pull-up transistors of 1st distributed NOR 2nd distributed NOR for general match signal Conventional CAM evaluates all reference data in parallel for a D i =0 match with two distributed NOR functions. Mattausch, CMOS Design, H19/6/29 26

27 Principle of Data Retrieval with CAM Input of Search Key CAM Memory Array (N Key Pattern, each m Bit) Exact Matching of Input Key and Stored Keys N Match Lines of CAM = RAM Word Lines RAM Memory Array (N Data Words, each k Bit) Output of Retrieved Data Word Conventional CAMs with only D i =0 match capability can be used for fast data retrieval problems, e. g. in internet routers. Mattausch, CMOS Design, H19/6/29 27

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