RTL Design (2) Memory Components (RAMs & ROMs)

Transcription

1 RTL Design (2) Memory Components (RAMs & ROMs)

2 Memory Components All sequential circuit have a form of memory Register, latches, etc However, the term memory is generally reserved for bits that are stored in a structured way. N Memory components are generally instantiated outside of the controller and path. Memory components are generally differentiated from disk storage The RAM of a computer is the memory, not the hard disk.

3 Early Storage In the early days of digital circuits, memories did not exist. Bits were stored on a magnetic drum or disk To read or write an address, the disk or drum has to be rotated to the correct spot. This was a slow process Bits were accessed serially. Most hard drives still operate in this fashion. Memories were a major evolution over disks and drums Any address could be accessed in any order Access was no longer serial. >

4 Memory Terminology Address A code used to identify a storage location Word A element stored at a memory > location. Word length The number of bits that can be stored in a word. In most modern architectures, a word is 32-bits. A microprocessor may have an 8-bit word. M x N M is the number of words N is the word length

5 RAM Random Access Memory A RAM is a memory structure that allows random (i.e. not sequential) access to each word ( element) stored in the memory. RAM is logically structured the same as a register file > Less than approximately words Register File Greater than approximately words RAM Ports Most RAMs have a single bi-directional port that is used for both reading and writing Most register files are dual ported Storage elements differ between register files and RAMs RF s use registers Memories need smaller elements due to the large size of the device. We will discuss two types.

6 RAM Due to the large size of RAMs, physical layout is important Square shapes are most efficient to minimize wire lengths. > Shorter wires mean smaller delays RAM layout is broken into word lines and bit lines Word lines turn on all storage elements that correspond to the word Each storage element is connected to a bit line where is read and written.

7 RAM Symbol 32 0 addr r w en 024x32 RAM > is bi-directional addr is the address of the word we wish to operate on. rw indicates our operation is write 0 is read en enables the requested operation.

8 RAM Schematic 32 0 addr rw en 024x32 RAM addr0 addr addr(a-) Let A = log 2 M d0 a0 a AxM d decoder a(a-) w(n-) word enable w(n-2) w0 bit storage block (aka cell ) word cell rw Combining rd and wr lines r (N-) w (N-) r0 clk en rw w0 e d(m-) to all cells r(n-) r(n-2) r0 word word enable enable rw RAM cell (N-) 0 Larger designs replicate this simple structure and enable multiple words with a single word line. A demux is used to choose the output bits of the desired word.

9 Static RAM (SRAM) word enable d 0 cell d Inverters create a bistable storage element Transistors are used to enable access to the cell. Both and must be provided to write a value to the cell.

10 SRAM Operations Write. Place the desired value on the bit lines. 2. Enabled the word line. 3. New values pass through the transistors and overwrite the old values. word enable d 0 0

11 SRAM Operations Read. Precharge both and to. 2. Enable the word line. 3. Stored values cause the precharged values to raise (for a stored ) or drop (for a stored 0). 4. A sense amplifier reads the difference of the two lines to determine the value. word enable d 0 < To sense amplifiers

12 Dynamic RAM (DRAM) word enable d cell capacitor slowly discharging Value is stored as a charge on the capacitor. Charge must be periodically restored due to parasitic resistance. Very compact storage method.

13 DRAM Operations Read. Pre-charge the word line with a voltage halfway between 0 and. 2. Enable the word line. The stored value alters the bit line voltage, discharging the cap. 3. Sense the voltage change to determine the value. 4. Write the previous value back to restore the cap s charge.

14 DRAM Operations Write. Set to the desired value. 2. Enable the word line. Capacitor is charged () or discharged (0). 3. Parasitic resistance starts to discharge the capacitor Large capacitors are used to make this a slow process.

15 DRAM Operations Refresh Due to parasitic resistances, the value stored on a cap drains over time. Periodically, all storage cells must be refreshed:. Read the value 2. Write it back The requirement for a refresh means that dynamic RAM cells are slower than SRAM cells. Speed is traded for reduced size. enable discharges

16 Comparing Memory Types Register file Fastest But biggest size SRAM Fast More compact than register file DRAM Slowest And refreshing takes time But very compact Use register file for small items, SRAM for large items, and DRAM for huge items Note: DRAM s big capacitor requires a special chip design process, so DRAM is often a separate chip register file MxN Memory implemented as a: SRAM DRAM Size comparison for same number of bits (not to scale)

17 RAM Timing RAMs have setup and hold timing requirements. Access time is the propagation delay for reading a value.

18 Reading and Writing a RAM clk addr rw en means write 999 Z 500 RAM[9] RAM[3] now equals 500 now equals 999 Writing (b) Put address on addr lines, on lines, set rw=, en= Reading Set addr and en lines, but put nothing (Z) on lines, set rw=0 Data will appear on lines Don t forget to obey setup and hold times In short keep inputs stable before and after a clock edge Access time is the propagation delay for reading a value. 3 clk addr rw valid valid setup time hold time setup time Z 500 access time

19 ROM Read Only Memory ROMs are a type of memory that can only be read. The act of writing initial values to a ROM is called programming. Advantages over RAM: More Compact very simple storage elements Non-volatile values are stored ever when power is removed. Increased Speed Low Power Several different storage elements can be used.

20 ROM Symbol is read only addr 024x32 ROM addr is the address of the word we wish to read. en en enables the a read operation.

21 ROM Schematic 32 0 addr en 024x32 ROM ROM block symbol addr0 addr addr addr(a-) clk en Let A = log 2 M d0 a0 a AxM d decoder a(a-) e d(m-) word enable 㩰 ю bit storage block (aka cell ) word word word enable enable r(n-) r(n-2) r0 ROM cell Internal logical structure similar to RAM, without the input lines

22 ROM Storage Types Mask Programmed ROM is programmed at the time of manufacture by hardwiring values. line 0 line Most compact type of ROM. Very fast 池 ю word enable cell cell Impossible to change without expensive redesign. word enable (from decoder) simply passes the hardwired value through transistor

23 ROM Storage Types Fuse-Based Programmable ROM (PROM) line line One Time Programmable (OTP) Fuses a blown to disable connections (programs a zero). 貰 э word enable cell fuse cell blown fuse ROM must be replaced to change stored values.

24 ROM Storage Types Erasable PROM (EPROM) Utilizes a floating gate transistor. Transistor has two gates. The floating gate has no electrical connections and is surrounded by 邀 э high impedance insulation. Unprogrammed, a floating gate transistor operates as normal. Stores a Programming involves placing a large voltage on the gate to trap electrons in the floating gate, disabling it s ability to conduct. Stores a 0 Programming can be erased by exposure to UV light Gives electrons enough energy to escape. floating-gate transistor word enable line line cell cell 0 e - e - trapped electrons

25 ROM Storage Types Electrically Erasable PROM (EEPROM) Like an EPROM, but thinner insulation around the floating gate allows it to be de-programmed with a high negative voltage. Programming is slow. At this point, ROMs start to resemble RAMs. Flash Memory A type of EEPROM Words are organized in blocks All words in a block can be erased quickly 溰 Ձ Both types are in-system programmable Can be programmed with new stored bits while in the system in which the ROM operates Requires bi-directional lines, and write control input Also need busy output to indicate that erasing is in progress erasing takes some time

26 EEPROM Symbol 32 0 addr en write busy 024x32 EEPROM 섀 Ծ is bi-directional addr is the address of the word we wish to operate on. en enables the a read operation. write = write the value of at the address. busy = indicates that programming is not yet complete.