Engineer-to-Engineer Note

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1 Engineer-to-Engineer Note EE-201 Technicl notes on using Anlog Devices DSPs, processors nd development tools Contct our technicl support t dsp.support@nlog.com nd t dsptools.support@nlog.com Or visit our on-line resources nd The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller Contributed by Mikel Kokly-Bnnourh Rev 1 Februry 4, Introduction This Engineer-to-Engineer Note introduces chrcteristics of the ADSP-TS20x TigerSHARC processor on-chip SDRAM controller. Although, this document is bsed on the ADSP-TS201 TigerSHARC processor, list highlighting the differences between TigerSHARC processor fmily derivtives (such s ADSP-TS201, ADSP-TS202, nd ADSP-TS203) is provided t the end of this document. The internl signl chin is shown with the necessry ddress-mpping scheme. The commnd truth tble gives detiled informtion bout execution in the SDRAM. The power-up sequence summrizes detil informtion to strt successful designs. A timing overview demonstrtes the performnce for different ccess modes. For bsic understnding of SDRAM memories, refer to the ppliction note The ABC of SDRAMemory (EE-126) [5]. Copyright 2004, Anlog Devices, Inc. All rights reserved. Anlog Devices ssumes no responsibility for customer product design or the use or ppliction of customers products or for ny infringements of ptents or rights of others which my result from Anlog Devices ssistnce. All trdemrks nd logos re property of their respective holders. Informtion furnished by Anlog Devices pplictions nd development tools engineers is believed to be ccurte nd relible, however no responsibility is ssumed by Anlog Devices regrding technicl ccurcy nd topiclity of the content provided in Anlog Devices Engineer-to-Engineer Notes.

2 2 Tble of Contents 1 Introduction Tble of Contents Listings Signl Chin of SDRAM On-Chip Controller Architecture Controller Commnd Interfce TigerSHARC Processor Output FIFO Controller Address Multiplexer Controller Dt Dely Buffer SDRAM Types Commnd Coding Controller s Pin Definition Controller Commnd Truth Tble Setup nd Hold Times Simplified Stte Digrm SDRAM Controller Properties Address Mpping Scheme TigerSHARC Processor SDRAM Memory Select Signls (~MSSDx) Burst Stop (BST) Dt Msk Function ([H:L]DQM) SDRAM Bnk Select...12 STANDARD SDRAMS LOW-POWER SDRAMS Controller Address 10 (SDA10) Burst Mode Prechrge All (PREA) Circulr Access Auto Refresh (REF) Self-Refresh (SREF) Mode Register Set (MRS) Extended Mode Register Set (EMRS) SDRAM Progrmming SYSCON Register SDRCON Register SDRAM Mode of Opertion ADSP-TS201S Processor EZ-KIT Lite Evlution Systems SDRAM Setting Overview Power-Up Sequence Hrdwre Initiliztion Softwre Initiliztion SDRAM Initiliztion Exmple SDRAM Interfce After Reset...22 The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 2 of 49

3 10 DMA Trnsfers Internl Memory nd SDRAM Externl Device nd SDRAM (FLY-BY) SDRAM Interfce in Host Mode Multiprocessing Commnd Decoding MRS Decoding REF Decoding SREF Decoding Bus Trnsition Cycle SDRAM nd Booting Loder Kernel Booting Modes SDRAM Interfce Throughput Sequentil Reds Without Interruption Non Sequentil Reds Without Interruption Sequentil Reds with Minimum Interruption Sequentil Writes Without Interruption Non Sequentil Writes Without Interruption Sequentil Writes with Minimum Interruption Reds Between Pge/Bnk Writes Between Pge/Bnk Minimum Red-to-Write Intervl Minimum Write-to-Red Intervl Chined DMA Trnsfers Auto-Refresh Self-Refresh nd Host Accesses SDRAM Performnce Tble Optimizing SDRAM Performnce Externl Buffering Using PC Modules Generl Rules for Optimized Performnce ADSP-TS20x TigerSHARC Processor Fmily Derivtives References Document History...49 The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 3 of 49

4 3 Listings Figure 1. ADSP-TS201 to SDRAM Signl Chin (64-bit bus configurtion)... 5 Figure 2. ADSP-TS201S SDRAM Controller Simplified Stte Digrm... 9 Figure 3. ADSP-TS201S SDRAM Controller Mpping Scheme Exmple Figure 4. ADSP-TS201S Processor SDRAM Controller Access Structure Figure 5. ADSP-TS201S Processor Externl Port Dt Alignment Figure 6. Power-Up nd Initiliztion: PREA-REF-MRS Figure 7. Signl Chin: Fly-by DMA nd SDRAM Figure 8. Signl Chin: Host to ADSP-TS201S Processor Figure 9. Bus Trnsition Cycle During SDRAM Accesses Figure 10. Signl Chin: ADSP-TS201S Processor to SDRAM Using Externl Buffer Tble 1. Supported SDRAM devices... 6 Tble 2. ADSP-TS201 SDRAM Controller Pins Description... 7 Tble 3. SDRAM Commnds Truth Tble... 7 Tble 4. [H:L]DQM Pins Functionlity Tble 5. Bnk Select Pins for 2-Bnked LVTTL SDRAMs Tble 6. Bnk Select Pins for 4-Bnked LVTTL SDRAMs Tble 7. Bnk Select Pins for 2-Bnked Low-Power SDRAMs Tble 8. Bnk Select Pins for 4-Bnked Low-Power SDRAMs Tble 9. Refresh Counter Vlues Tble 10. ADSP-TS201 EZ-Kit Lite SDRAM Settings Tble 11. ADSP-TS201 Processor SDRAM Pin Description After Reset Tble 12. Multiprocessing Commnd Decoding Tble 13. ADSP-TS20x TigerSHARC Processor Fmily Product Differences The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 4 of 49

5 4 Signl Chin of SDRAM Figure 1 illustrtes the signl chin between the ADSP-TS201S, the on-chip SDRAM controller, nd the externl memory device for 64-bit bus configurtion: ADSP-TS201S Core DMA SCLK int. RD int. WR int. Reset int. ACK busy ~MSSDx Commnd Logic SDCKE ~RAS ~CAS ~SDWE [H:L]DQM SDA10 ~MSSDx SCLK CLK CKE ~RAS ~CAS ~WE DQM A10 ~CS SDRAM Externl Port Buffers A25:0 Pipe depth Address Multiplexer A14 A13 A1:10, A12 Dt buffer BA0 BA1 A0:9, A11 DQ31:0 A31:0 D63:0 (non SDRAM) Figure 1. ADSP-TS201 to SDRAM Signl Chin (64-bit bus configurtion) Consider the three prts of the signl flow: ADSP-TS201S (core, DMA engine, I/O processor, nd the ddress buffer) The SDRAM Controller (control interfce, dely buffer, nd ddress multiplexer) SDRAM device The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 5 of 49

6 5 On-Chip Controller Architecture The synchronous interfce between the ADSP-TS201S processor nd the on-chip controller re described in four bsic prts: 5.1 Controller Commnd Interfce Becuse of the two different timing protocols, the TigerSHARC processor's internl commnds re converted to comply with the JEDEC stndrd for SDRAMs. The 125 MHz (mximum) externl clock is used for synchronous opertion. The TigerSHARC s internl request lines or strobes re used to ccess the SDRAM with pulsed commnds. The controller s internl ACK line inserts vrible wit sttes to the processor during overhed cycles, cused by DRAM technology. 5.2 TigerSHARC Processor Output FIFO The TigerSHARC processor s output FIFO is ctive for externl port ddresses like SDRAM. The processor's six-stge FIFO depth supports ddress pipelining for high-speed non-sequentil red opertions without performnce loss. 5.3 Controller Address Multiplexer Every first red or write ction is issued in multiplexed mode. A mximum of 8192 rows (64-bit bus configurtion) nd rows (32-bit bus configurtion) within 1024 columns cn be ddressed. 5.4 Controller Dt Dely Buffer If systems incorporte hevy buslod, n dditionl dt buffer is used to decouple the input from the cpcitive lod. This dely buffer, in conjunction with n externl buffer for SDRAM control nd ddress lines, reduces dditionl logic. 5.5 SDRAM Types The ADSP-TS201S processor's on-chip SDRAM controller interfce supports vrious LVTTL (3.3V) s well s mobile low-power SDRAM devices (2.5V), depending on size nd internl orgniztion (I/O cpbility, number of rows, nd pge size). The following tble summrizes ll the supported types: Size I/O cpbility Row x Pge Size I/O cpbility Row x Pge 1M x 16 2K x 256 8M x 32 8K x Mbits 2M x 8 2K x Mbits 16M x 16 8K x 512 4M x 4 2K x M x 8 8K x M x 32 2K x 256 8M x 32 8K x 256 4M x 16 4K x Mbits 64 Mbits 16M x 16 8K x 512 8M x 8 4K x M x 8 8K x M x 4 4K x M x 32 4K x Mbits 8M x 16 4K x M x 8 4K x 1024 Tble 1. Supported SDRAM devices The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 6 of 49

7 6 Commnd Coding 6.1 Controller s Pin Definition Pin Type Description ~MSSD[3:0] I/O/T (pu) SDRAM bnks Memory select signls ~RAS I/O/T (pu) Row select signl ~CAS I/O/T (pu) Column select signl ~SDWE I/O/T (pu) Write enble signl HDQM O/T (pu) Msk dt high lne signl LDQM O/T (pu) Msk dt low lne signl SDA10 O/T (pu) Address10 /commnd select signl SDCKE I/O/T (pu/pd) Clock enble signl A[1:10,:12-15] I/O/T ddresses for 64-bit A[0:9,11-15] I/O/T ddresses for 32-bit A[11:15] I/O/T Bnk select signl D[63:0] I/O/T Dt signls I = input, O = output, T = Hi-Z, pd = pull-down, pu = pull-up Tble 2. ADSP-TS201 SDRAM Controller Pins Description 6.2 Controller Commnd Truth Tble Tble 3 provides n overview of ll commnds provided by the SDRAM controller. These commnds re utomticlly hndled by the interfce. SDCKE = high CMD SDCKE(n-1) SDCKE(n) ~MSSDx ~RAS ~CAS ~SDWE SDA10 ADDR MRS V V ACT V V RD V WR V SDCKE = high, no vlidity of ddress CMD SDCKE(n-1) SDCKE(n) ~MSSDx ~RAS ~CAS ~SDWE SDA10 ADDR NOP x x x x x BST x x REF x PREA x Commnds with SDCKE trnsition CMD SDCKE(n-1) SDCKE(n) ~MSSDx ~RAS ~CAS ~SDWE SDA10 ADDR SREF En x x SREF M 0 0 x x x X x x SREF Ex x x x x x x=don t cre, v=vlid dt input, 0=logic 0, 1=logic 1, En=entry, M=mintin, Ex=exit Tble 3. SDRAM Commnds Truth Tble The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 7 of 49

8 Although the SDCKE line toggles in n synchronous mnner, the commnds re smpled synchronous to the CLK signl. Note tht Power-down nd Suspend modes re not supported, nd tht the controller does not llow uto prechrge. Lstly, keep in mind tht ll SDRAM commnds re fully trnsprent to the user. 6.3 Setup nd Hold Times The synchronous opertion uses the externl clock s reference. Commnds, ddresses, nd dt re ltched t the rising edge of clock. The vlid time mrgin round the rising edge is defined s setup time (time before rising edge) nd hold time (time fter rising edge) to gurntee tht both the controller nd the SDRAM re working together relibly. Signl slew rtes, propgtion delys (PCB), nd cpcitive lods (devices) influence these prmeters nd should be tken into considertion. Refer to the ADSP- TS201S Dt sheet for SDRAM interfce AC signl specifictions. 6.4 Simplified Stte Digrm The following stte digrm (Figure 2) shows ll possible SDRAM commnds sequences to help nlyze the controller s functionlity. The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 8 of 49

9 if "EMRS bit set Mode Register MRS tmrd=2 Idle Stte SREF Exit txsr=trc Self Refresh (Host) ACT REF Core DMA MMS Host BST Row ctivte BST Refresh Counter expired Auto Refresh only one bnk t the time cn be ctive trcd=cl RD trcd 1-3 BST BST WR trcd 1-3 CL 1-3 Red burst Write burst SDRAM burst: full pge ( words) PREA Controller burst: Qud-word (128-bits) 32-bit => 4 words 64-bit => 2 words set bit "SDRAM enble" Trigger MRS Sequence Prechrge ll tras 2-8 Automtic sequence Controller input trp 2-5 Figure 2. ADSP-TS201S SDRAM Controller Simplified Stte Digrm The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 9 of 49

10 7 SDRAM Controller Properties Following, the ADSP-TS201S processor's on-chip SDRAM controller properties re exmined: 7.1 Address Mpping Scheme There re vrious possibilities when ccessing the SDRAM. For instnce, ll rows in bnk (or ll bnks in row) cn be ccessed sequentilly. PC DIMM modules re ccessed in different mnner compred to typicl DSP ppliction. The ADSP-TS201S controller uses hrdwre mp scheme optimized for digitl signl processing. The ddress mpping scheme is decoded from the pge size nd the bus width (both configurble by softwre in the SDRCON nd SYSCON registers respectively; refer to section 8 SDRAM Progrmming). For more informtion regrding the ddress mpping scheme, refer to the SDRAM chpter of the ADSP- TS201 TigerSHARC Processor Hrdwre Reference [1]. Figure 3 reproduces n exmple of the controller s ddress mpping for 64-bit dt. In bnk A, the SDRAM s columns re sequentilly ccessed until the end of the row. Similrly, the SDRAM s rows re sequentilly selected until the bnk s end. Exmple: Address Multiplexing of 128MBits SDRAM (4k x 512 x 4 Bnks x 16bit) (64-bit bus configurtion) Bnk Row Column ~MSSDx Row Input: Controller ddress 1. Output: Row ddress ~CS Column Output: Column ddress Figure 3. ADSP-TS201S SDRAM Controller Mpping Scheme Exmple Note tht only one bnk my be ctive t time, which results in overhed cycles when switching between bnks (off-bnk ccesses). Similrly, moving from one row to nother (off-pge ccess) results in the sme overhed cycles. Figure 4 shows how the ADSP-TS201S TigerSHARC processor's on-chip SDRAM controller ccesses SDRAM. The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 10 of 49

11 4M x 4bit x 4 Bnks, 4096 Rows, Pge size 1024 words Column 0 On Pge Access Column 1023 Row 0 Row 1 Off Pge Access Row 4095 Off Bnk Access Bnk A Bnk B Bnk C Bnk D Figure 4. ADSP-TS201S Processor SDRAM Controller Access Structure 7.2 TigerSHARC Processor SDRAM Memory Select Signls (~MSSDx) The ADSP-TS201 TigerSHARC processor hs four SDRAM Memory Select lines (~MSSD[3:0]) to ddress the four SDRAM memory bnks: ~MSSD0 SDRAM ddress memory spce: 0x x ~MSSD1 SDRAM ddress memory spce: 0x x ~MSSD2 SDRAM ddress memory spce: 0x x ~MSSD3 SDRAM ddress memory spce: 0x x These signls cn be used for SDRAM ccesses only. In this memory region, the controller s ddress multiplexer will be ctive. 7.3 Burst Stop (BST) Although the controller works in burst mode, there is one wy to interrupt the burst with the burst stop commnd. BST is issued if the next instruction is: Non externl SDRAM ccess (ccess to nother TigerSHARC bnk) Core ccess (depending on the number of ccesses, dely nd externl port FIFOs stte) DMA opertion (externl port DMA to SDRAM interrupted by higher priority DMA) The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 11 of 49

12 Refresh counter expired (refresh period counter) SDRAM red to write nd write to red trnsitions SDRAM off pge/bnk ccess ~HBR sserted (host interfce) During Bus Trnsition Cycle (multiprocessing) 7.4 Dt Msk Function ([H:L]DQM) The [H:L]DQM pins re used by the controller to msk write opertions. HDQM msks the SDRAM DQ buffers when performing 32-bit writes to even ddresses in 64-bit bus configurtion. LDQM msks the SDRAM DQ buffers when performing writes to odd ddresses in 64-bit bus configurtion. This dt msk function does not pply for red opertions, where the LDQM nd HDQM pins re lwys low (inctive). This is summrized in the following tble: Bus Width* 64-bit 32-bit Access type 32-bit Even 32-bit Odd 64-bit 32-bit Even/Odd HDQM x LDQM *Bus Width bit setting in SYSCON x = don t cre, 0 = logic 0, 1 = logic 1 Tble 4. [H:L]DQM Pins Functionlity 7.5 SDRAM Bnk Select The connections of the ddress pins s bnk select lines for the SDRAM device vries, depending the opertionl voltge of the SDRAM device (stndrd or low-power) nd the number of bnks tht the prt hs. Stndrd SDRAMs The next tbles show the ddress lines selection for the different bnks: 2-bnked ccess Bnks A[11:15] SDA10 Bnk_A 0 0 Bnk_B 1 0 Bnks A/B x 1 x = don t cre, 0 = logic 0, 1 = logic 1 Tble 5. Bnk Select Pins for 2-Bnked LVTTL SDRAMs Note: Any ddress line from ddress rnge A[11:15] cn be used for bnk select s long s it is re not driven s row or column ddress. The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 12 of 49

13 4-bnked ccess Bnks A[11,13,15] A[12,14] SDA10 Bnk_A Bnk_B Bnk_C Bnk_D All Bnks X X 1 x = don t cre, 0 = logic 0, 1 = logic 1 Tble 6. Bnk Select Pins for 4-Bnked LVTTL SDRAMs Note: Any ddress line pir from ddress rnge A[11:15] cn be used for bnk select s long s they re not driven s row or column ddress. Low-Power SDRAMs The following tbles show ddress line selection for the different bnks: 2-bnked ccess Bnks A[14:15] SDA10 Bnk_A 0 0 Bnk_B 1 0 Bnks A/B x 1 x = don t cre, 0 = logic 0, 1 = logic 1 Tble 7. Bnk Select Pins for 2-Bnked Low-Power SDRAMs Note: Any ddress line from the two ddress lines A[14:15] cn be used for bnk select s long s it is not driven s row- or column ddress. 4-bnked ccess Bnks A[14] A[15] SDA10 Bnk_A Bnk_B Bnk_C Bnk_D All Bnks X X 1 x = don t cre, 0 = logic 0, 1 = logic 1 Tble 8. Bnk Select Pins for 4-Bnked Low-Power SDRAMs Note: Address lines A[14:15] must be used for bnk select. The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 13 of 49

14 7.6 Controller Address 10 (SDA10) This pin provides specil solution to gin control of the SDRAM, even when the processor opertes s slve (multiprocessing). The SDA10 pin llows simultneous ccess to ll bnks during refresh nd prechrge-ll commnd. This pin must be connected to the A10 pin of the SDRAM. Note: The SDA10 pin replces the processor s A[10] nd A[11] pins in 32-bi nd 64-bit bus width configurtion, respectively. Also, during ccess to the ~MSSDx spce, these pins re not used. 7.7 Burst Mode Although the SDRAM device is progrmmed for full-pge burst, the controller uses qud-word (128-bits) burst mode. For 32-bit bus width, the burst length is 4 words; for 64-bit width, the burst length is 2 words. Only the first red or write commnd is ccompnied with n externl ddress, which is driven by the controller until the burst is interrupted by nother ddress. Note tht the SDRAM Controller burst mode cnnot be chnged. 7.8 Prechrge All (PREA) This commnd prechrges ll SDRAM bnks simultneously (SDA10 must be high to select ll bnks), which plces the bnks into the idle stte. Although only one bnk my be ctive t time, the controller does not support single bnk prechrge. 7.9 Circulr Access The controller supports circulr ccesses during sequentil red or writes within pge, performing fixed throughput of 1 cycle/word. At the end of the pge (defined in the SDRCON register), the instructions xr3:0=q[j1+=lst_word];; followed by xr7:4=q[j1+=first_word];; re lso executed with 1-cycle/word throughput. This functionlity is similr to the IALU s circulr buffering mode supported by the TigerSHARC processor's core Auto Refresh (REF) After the SDRAM registers the CAS before RAS refresh commnd, it internlly sserts CAS nd delyed RAS to execute row s refresh. The row intervl (trefi) is typiclly 15,6 or 7,8 µs, depending on the SDRAM device being used. The limit of refresh period is given by the trefmx specifiction. Note tht the controller does not support burst refresh Self-Refresh (SREF) The self-refresh is very effective wy of reducing the ppliction s power consumption to minimum. When host processor gins control of the cluster bus, the TigerSHARC processor's SDRAM controller plces the SDRAM into self-refresh mode before the bus is relinquished to the host. When triggered by n The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 14 of 49

15 internl timer, the SDRAM strts refreshing itself. The controller does not llow the softwre to plce the SDRAM into self-refresh mode, only during host ccesses Mode Register Set (MRS) During the MRS commnd, the SDRAM controller initilizes the SDRAM with the following fixed settings: Burst length is hrdwired to full-pge burst Burst type is hrdwired to sequentil burst Red ltency (CL) is user progrmmble (1-3 cycles) 7.13 Extended Mode Register Set (EMRS) Although, this is lso n MRS commnd, the difference between the two sequences, MRS nd EMRS, relies on the dt sent vi the ddress lines driven by the TigerSHARC processor SDRAM controller (lso see section SDRAM Bnk Select). The Extended Mode register controls power-sving relted functions nd initilizes the SDRAM with the following fixed settings: Prtil Arry Self-Refresh (PASR) self-refresh coverge is set to 4 bnks Temperture Compensted Self-Refresh (TCSR) - self-refresh frequency is set to its mximum (mximum cse temperture 85 C) The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 15 of 49

16 8 SDRAM Progrmming Before externl bus trnsctions to SDRAM strt, the system nd SDRAM control registers must be configured ccordingly. 8.1 SYSCON Register SYSCON, the system configurtion register, must be configured fter hrdwre reset t the beginning of the source code. This register is composed of different fields, lthough only the following pplies for SDRAM: Bus Width: 0: 32-bit bus 1: 64-bit bus For proper opertion, mke sure tht the dedicted bus width bits settings is: Note tht if either the host or memory bus width is 64 bits, the multiprocessing width must lso be 64 bits. Also, when using 64-bit mode, the TigerSHARC s ddress 0 pin becomes redundnt, since its informtion is contined in the strobes. Therefore, this pin is not connected for SDRAM ccesses in 64-bit mode. The following digrm shows the ADSP-TS201S processor's externl port dt lignment for both 32- nd 64-bit bus configurtions: Figure 5. ADSP-TS201S Processor Externl Port Dt Alignment 8.2 SDRCON Register The SDRAM progrmming is done by the SDRCON register. Similr to SYSCON, configure SDRCON fter hrdwre reset t the beginning of the source code before trying to ccess the SDRAM memory. In multiprocessor systemsprocessor, this register must be progrmmed to the sme setup in every processor. The SDRCON bit fields re: SDRAM Enble: set whenever n SDRAM is present in the system. CAS Ltency: this bit defines the red ltency (CLmin) relted to the vendor s device. This vlue cn be set from 1 to 3 cycles, depending on the SDRAM chrcteristics nd the clock frequency. The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 16 of 49

17 Pipe depth: this bit llows the SDRAM ddress nd control lines to be pipelined. Setting this bit introduces one-cycle dely during red nd write ccesses. Pge Boundry: this bit, which cn be set to either 256, 512, or 1024 words, determines the pge size of the SDRAM. Refresh Counters: these bits enble coordintion of the SOC bus clock rte (SOCCLK) with the SDRAM s required refresh rte. They select between 4 different refresh rtes clculted with the following eqution: Cycles = SOCCLK tref Rows = ( SOCCLK refresh _ rte ) The ADSP-TS201S processor supports refresh rtes of 1100, 1850, 2200, or 3700 cycles. The following tble illustrtes how to select between the different rtes bsed on the formul bove. SOC Clock frequency (MHz) SDRAM Memory Refresh Rte (µsecs) SDRAM Memory Refresh Rte (cycles) ADSP-TS201 Supported Refresh rte (cycles) SDRCON Bits [8:7] * Note tht the SOCCLK frequency equls ½ CCLK. Tble 9. Refresh Counter Vlues Prechrge to RAS dely (trp): this bit defines the prechrge time (trpmin) relted to the vendor s device. This vlue cn be set from 2 to 5 cycles. Note tht most SDRAMs specify this prmeter in nnoseconds rther thn number of cycles. RAS to prechrge dely (tras): this bit defines the row ctive time (trasmin) relted to the vendor s device. This vlue cn be progrmmed from 2 to 8 cycles. Note tht this prmeter is lso specified in nnoseconds rther thn number of cycles. Initiliztion Sequence: this bit determines the order of the MRS (Mode Register set) nd refresh sequences. When set, MRS follows refresh in the SDRAM initiliztion sequence. Otherwise, the MRS precedes refresh: Init Sequence = 0 PREA commnd - plces the SDRAM in the defined idle stte. 8 REF commnds - chrges SDRAM s internl nodes. MRS commnd - initilizes the SDRAM s working mode. The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 17 of 49

18 Init Sequence = 1 PREA commnd - plces the SDRAM in the defined idle stte. MRS commnd - initilizes the SDRAM s working mode. 8 REF commnds - chrges SDRAM s internl nodes. EMR Enble: this bit, when set (=1), enbles n Extended Mode Register set (EMRS) sequence, which is issued proceeding the initil MRS (see Initiliztion Sequence bove). This bit must be set when interfcing to low-power SDRAM devices only. Otherwise, this bit should remin clered. tras nd trp re used for the refresh cycle, which cn be expressed s: trc=tras+trp. Also, the specifiction requires tht trasmin, trpmin, nd CLmin be defined s frction of the SCLK period. 8.3 SDRAM Mode of Opertion During the MRS, ddress bits ADDR[13:0] of the SDRAM re used to progrm the device. The MRS, issued by the TigerSHARC processor with ID=000, is executed during power-up only. MRS initilizes the following prmeters: A[2:0] - Burst length is hrdwired to full-pge burst. A[3] - Burst type is hrdwired to sequentil burst. A[6:4] - Ltency mode set ccording to the CAS ltency progrmmed in SDRCON (1-3 cycles). A[13:7] - Hrdwired to zero (reserved mode of opertion for future needs). Additionlly, when the EMR Enble bit is set, second MRS sequence (EMRS) is issued by the controller. The Extended Mode register controls power sving relted functions nd initilizes the following prmeters: A[2:0] - Prtil rry self-refresh (PASR). The self-refresh coverge is hrdwired to four bnks A[4:3] - Temperture-compensted self-refresh (TCSR). The self-refresh frequency is hrdwired to its mximum cse temperture, 85 C Bits 13 5 Hrdwired nd set to ADSP-TS201S Processor EZ-KIT Lite Evlution Systems The ADSP-TS201 TigerSHARC processor EZ-KIT Lite evlution bord includes 256 Mbits of SDRAM memory (32 Mbytes - 4M x 64bits). The following tble shows the SDRAM control register (SDRCON) settings for the EZ-KIT Lite bord: SDRAM Device SDRAM Clock (MHz) SDRAM Settings SDRCON 2x MT48LC4M32B2 100 SDRAM Enble = 1 CAS Ltency = 2 Pipe Depth = 0 Pge size = 256 Refresh rte = 3700 trp = 2, tras = 5 Init Sequence = 1 EMR Enble = 0 Tble 10. ADSP-TS201 EZ-KIT Lite SDRAM Settings 0x5983 The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 18 of 49

19 8.5 SDRAM Setting Overview Timing spec Controller Description tck MHz Clock cycle time, hrdwre trefmx cycles Refresh period Clmin 1-3 cycles Red ltency trasmin 2-8 cycles Activte to prechrge trpmin 2-5 cycles Prechrge period trcd trcd = CL (fixed) RAS to CAS dely trfcmin trc = tras+ trp (fixed) Activte period trrd trrd = trc (fixed) Activte A to ctivte B tmrd 2 cycles (fixed) Mode register to commnd txsr trc + trp (fixed) Exit self refresh to ctive Power up Mode Burst Mode Burst Length CL SDRAM (Mode Register Set) PREA-MRS-REF or PREA-REF-MRS Sequentil (fixed) Full pge (fixed) 1-3 cycles Prtil Arry Self Refresh (PASR) Temperture Compensted Self-refresh (TCSR) SDRAM (Extended Mode Register Set) Self-refresh coverge set to four bnks (fixed) Self-refresh frequency set to its mximum cse temperture, 85 C (fixed) The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 19 of 49

20 9 Power-Up Sequence Figure 6 shows the power-up procedure for the SDRAM interfce: HW- Reset required to strt power up mode SDCKE Self refresh enbled CLOCK ~MSSDx Controller Initiliztion SDRAM's commnd decoder enbled [H:L]DQM SDRAM Initiliztion DQ Buffers enbled SDA10 CMD strt of power up sequence 8 x REF PREA NOP REF REF MRS NOP ACT VDD, VDDQ nd clock stble Commnd decoder disbled trp 8 x trcmin tmrd strt norml opertion 1. Hrdwre init. 2. Softwre init. Figure 6. Power-Up nd Initiliztion: PREA-REF-MRS 9.1 Hrdwre Initiliztion After hrdwre reset of the ADSP-TS201S processor, the clock nd the SDRAM s power supply pins (VDD nd VDDQ) must provide stble signl for typicl minimum time of 200µs. The SDRCON register cn be ccessed only fter this time hs elpsed. 9.2 Softwre Initiliztion Writing to the SDRCON register initilizes the SDRAM controller. As soon s ~MSSDx is sserted, the SDRAM s commnd decoder is enbled. The Init Sequence bit in SDRCON strts the initiliztion sequence (refer to section 8.2 SDRCON Register). During this time, [H:L]DQM lines remins high, three-stting the SDRAM DQ buffers. Once The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 20 of 49

21 the initiliztion sequence is completed, buffers re enbled nd the SDRAM is redy for norml opertion. Note tht when the EMRS bit in the SDRCON register is set (required for interfcing to low-power SDRAM), n dditionl MRS commnd, which follows the MRS commnd shown in Figure 6, is executed (see 7.13 Extended Mode Register Set (EMRS) for more detils). The time elpsed before the first ccess to SDRAM cn be represented s: tccess trp + 8(tRAS + trp) + tmrd (SCLK cycles) Note: To properly initilize the SDRAM, the first ccess is delyed with the internl cknowledge until the power-up sequence hs finished. 9.3 SDRAM Initiliztion Exmple This section shows how to initilize the SDRCON register ccording to the following device specifictions. 2x 128Mb (4Mx32 bit) SDRAM 3.3 Volts (EMR bit clered) 4 bnks, pge size: 256 words SDRAM clock: 100 MHz (SOCCLK: 250 MHz) Refresh cycles: 4K/64ms (15.6µsecs) Power-up mode: PRE - MRS - REF CLmin = trasmin = 42 ns, trpmin = 18 ns No self-refresh nd no buffering Therefore, the SDRAM initiliztion code would look s follows: j1 = j31 + 0x ;; SDRCON = j1;; // SDRAM ENA=1, CL=2, pipedepth=0, pge=256w // refresh rte=3700, trp=2, trs=5, init=1, EMR=0 Note tht the minimum timing specifictions for tras, trp, nd CL must be gurnteed. Setting these to vlues lrger thn the minimum required cuses loss of performnce (i.e. longer dely cycles or unnecessry refresh cycles). The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 21 of 49

22 9.4 SDRAM Interfce After Reset After power-up when the ADSP-TS201S processor's reset pin is desserted, the SDRAM-lines re in the following stte: Pin Stte Description SDCKE 1 SDRAM Clock enbled ~MSSD[3:0] 1 Commnd decoder disbled ~RAS 1 Deselected ~CAS 1 Deselected ~SDWE 1 Deselected [H:L]DQM 1 SDRAM dt buffers disbled SDA10 1 Access ll bnks simultneously Tble 11. ADSP-TS201 Processor SDRAM Pin Description After Reset The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 22 of 49

23 10 DMA Trnsfers Direct Memory Access (DMA) is mechnism for trnsferring dt without core involvement. Trnsfers cn be between internl nd externl memory, or between externl memory nd n externl peripherl Internl Memory nd SDRAM The TigerSHARC processor DMA controller cn be used to trnsfer dt from the processor s internl memory to externl SDRAM. Similrly, the SDRAM cn be used s the source, nd the internl memory s the destintion Externl Device nd SDRAM (FLY-BY) ADSP-TS201S SDCKE controlled by host ccess SCLK Core DMA int. CLK int. RD int. WR int. Reset int. ACK int. MSSDx Externl Port Buffers busy disbled A25:0 Address Multiplexer SDCKE ~RAS ~CAS ~SDWE HLDQM SDA10 ~MSSDx A14 A13 A1:10 A12 CKE ~RAS ~CAS ~WE [H:L]DQM A10 ~CS BA0 BA1 A0:9 A12 CLK SDRAM Dely buffer DQ63:0 Inctive ~HBR ~HBG ~IORD ~IOWR ~IOEN ~DMAR0 I/O Device Figure 7. Signl Chin: Fly-by DMA nd SDRAM Fly-by trnsctions re used by the DMA controller to trnsfer dt between n externl I/O device nd externl SDRAM memory. The fly-by trnsction type cn be SDRAM memory to I/O (fly-by red) or I/O to SDRAM memory (fly-by write). A fly-by trnsction is issued by DMA chnnel tht is progrmmed to execute fly-by. The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 23 of 49

24 In fly-by trnsctions, the SDRAM memory is controlled using the pproprite SDRAM controller signls (~MSSDx, ~RAS, ~CAS, nd ~SDWE), nd the I/O device is controlled with the ~IORD, ~IOWR, nd ~IOEN pins. The ~IOWR signl is used during fly-by red trnsctions (SDRAM memory red nd I/O write). During fly-by write trnsctions (SDRAM memory write nd I/O red), the signls ~IORD nd ~IOEN re driven. To trnsfer dt, the I/O-device sserts the ~DMAR0 pin only DMA chnnel 0 cn be used for fly-by trnsctions. Ech ssertion (flling edge) of the ~DMAR0 signl represents one trnsction. The ~IORD, ~IOWR, nd ~IOEN pins re output by the current TigerSHARC processor's bus mster nd is used to control the I/O-device. For more detils on the TigerSHARC processor's DMA controller nd fly-by mode, refer to the Direct Memory Access nd SDRAM Interfce chpters of the ADSP-TS201 TigerSHARC Processor Hrdwre Reference [1]. The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 24 of 49

25 11 SDRAM Interfce in Host Mode Figure 8 shows possible signl chin between the ADSP-TS201S processor, SDRAM, nd host processor. ADSP-TS201S SDCKE controlled by host ccess SCLK Core DMA int. CLK int. RD int. WR int. Reset int. ACK int. MSSDx Externl Port Buffers busy disbled A25:0 D63:0 SDCKE ~RAS ~CAS ~SDWE HLDQM SDA10 ~MSSDx A14 A13 CKE ~RAS ~CAS ~WE [H:L]DQM A10 ~CS BA0 BA1 A0:9 A12 CLK SDRAM Dely buffer DQ63:0 Inctive ~HBR ~HBG ~IORD ~IOWR ~IOEN ~DMAR0 I/O Device Figure 8. Signl Chin: Host to ADSP-TS201S Processor Host ccesses re initited when the host sserts ~HBR, relinquishinging the externl bus to the TigerSHARC processor. Therefter, the TigerSHARC processor responds to this request by sserting ~HBG, grnting the bus to the host. The host becomes bus mster nd cn now ccess the TigerSHARC processor's internl resources through its multiprocessor memory spce. Note tht during ~HBG low, the SDRAM is in self-refresh mode. This limits the host device to not being ble to ccess the SDRAM using the TigerSHARC processor s SDRAM controller (fly-by mode). Thus, during host trnsctions, the SDRAM cn only be ccessed by host using its own SDRAM controller. However, workround for this my be possible if the host follows the given sequence: The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 25 of 49

26 1. Initilly, the TigerSHARC processor is current bus mster. To gin control of the bus, the host sserts ~HBR nd wits for the TigerSHARC processor to grnt the bus (~HBG) 2. The host becomes bus mster nd is now ble to ccess the internl resources of the TigerSHARC processor. 3. The host sets up DMA trnsfer, prepring the TigerSHARC processor to trnsfer dt to SDRAM upon host requests (DMA request line ~DMAR0). 4. The host relinquishes the bus (de-sserts ~HBR), which brings the SDRAM out of self-refresh mode 5. Finlly, the host strts toggling ~DMAR0, indicting to the TigerSHARC processor to strt trnsmitting dt to the SDRAM. The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 26 of 49

27 12 Multiprocessing This section covers the rbitrtion logic used to gurntee multiprocessing systems Commnd Decoding The ADSP-TS201S processor cn be connected to multiprocessor cluster of up to eight processors. Only one TigerSHARC processor cn drive the bus t time. To build glueless hrdwre, the interfce works in slve mode, s well, to detect these commnds: MRS, REF, nd SREF. The following pins re necessry for detection: Pin Type Description SDCKE I/O/T SDRAM Clock Enble ~MSSD[3:0] I/O/T Memory Select SDRAM (commnd input) ~RAS I/O/T Row Address Select (commnd input) ~CAS I/O/T Column Address Select (commnd input) ~SDWE I/O/T SDRAM Write Enble (commnd input) I=input, O=output, T=three-stte Tble 12. Multiprocessing Commnd Decoding 12.2 MRS Decoding In TigerSHARC multiprocessor systems where SDRAM is used, the Mode Register Set sequence is only issued by the processor with ID=000. Therefore, processor with ID=000 must be present in every multiprocessor system. The MRS sequence is only issued once before ccessing the SDRAM for the first time. It is lso importnt to note tht the set-up vlue initilized in the SDRCON register must be identicl for ll processors in the cluster REF Decoding This detection helps to synchronize ll eight refresh counters. The slve s refresh counter is decremented ech time the interfce detects refresh. This gurntees periodic refresh, nd similr to the MRS sequence, requires the exct sme settings of SDRCON registers SREF Decoding This detection helps to synchronize the self-refresh bse. When host requests the bus, the system mster plces the SDRAM into self-refresh mode. The slve processors recognize the SREF, freezing the refresh counters until self-refresh mode is exited Bus Trnsition Cycle The bus trnsition (turn-over cycle) is issued when bus mstership chnges between the different TigerSHARC processors shring the cluster bus. This lso implies mstership trnsition between the SDRAM controllers. Since the new bus mster unble to determine which row in the SDRAM is currently open, the current bus mster issues prechrge-ll commnd (PREA) utomticlly before the bus is The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 27 of 49

28 relinquished to the new bus mster. This wy, the new bus mster cn sfely strt ccessing the SDRAM by simply issuing n ctivtion commnd (ACT). Figure 9 shows this sequence: SCLK BR0 BR1 DSP ID 0 Requests the Bus nd it wits for Bus Mster to finish current trnsction DSP ID 1 Requests the Bus nd it becomes Bus Mster DSP ID 0 is now Bus Mster nd strts ccessing SDRAM (ACT) CMD ACT NOP WR NOP WR NOP BST PREA ACT NOP WR NOP DSP ID 1 Relinquishes the Bus fter issuing PREA Figure 9. Bus Trnsition Cycle During SDRAM Accesses The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 28 of 49

29 13 SDRAM nd Booting 13.1 Loder Kernel Dt must be loded in SDRAM before runtime. This requires n initilized SDRAM before downloding the dt during the boot scenrio. The VisulDSP++ loder utility provides this cpbility. Three stndrd loder executbles re vilble for booting, depending upon the boot mode (EPROM, link ports, or host processor). Note tht independently from the selected boot mode, the SDRAM Control register (SDRCON) must be initilized before the user s ppliction strts writing dt to it. This must be done during the first 256-loder kernel words; otherwise, the dt plced in the SDRAM will be corrupted. The steps re: 1. ~RESET must be de-sserted, ~BMS is smpled 2. Kernel (256 x 32 bit) is trnsmitted vi DMA into the processor (0x00-0xFF) (~BMS or ~HBG continuously sserted) 3. Interrupt genertion strts kernel execution, SDRAM nd controller is initilized (~MSSDx sserted for SDRAM setup) 4. User s dt is loded into the processor/sdram (~BMS, ~HBG nd ~MSSDx re toggling requesting the bus) 5. Kernel is now overwritten with user s code (~BMS or ~HBG continuously sserted) 6. Processor strts code execution t strt ddress 0x Booting Modes The boot mode is selected t the end of reset by smpling the ~BMS pin. At this stge, four options for beginning opertion cn be selected: Mode ~BMS DMA chnnel EPROM 0 (Defult) Hrdwired DMA Chnnel 0 Link Port 1 Link Port DMA Chnnels 8-11 Host 1 AutoDMA Chnnels 0-1 No boot 1 - If ~BMS is smpled low during reset, EPROM boot is selected. However, if ~BMS is smpled high during reset, the processor goes into n IDLE stte, witing for host or link boot. Refer to [6] ADSP- TS201S TigerSHARC Processor Boot Loder Kernels Opertion (EE-200), which describes ech mode of opertion in more detil. The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 29 of 49

30 14 SDRAM Interfce Throughput This section investigtes the SDRAM controller s performnce during dt trnsfers, where the SDRAM is used s source or destintion. The following settings re used: Silicon = ADSP-TS201S Rev 0.0 SCLK = 100 MHz (externl port nd SDRAM clock) CCLK = 500 MHz (core clock) SOCCLK = 250 MHz (SOC bus clock) SYSCON = 0x389067, for 64-bit bus configurtion SDRCON = 0x5983, where Pge Boundry = 256 words, Refresh rte = 3700 cycles, t RAS = 5 cycles, t RP = 2 cycle, CL = 2 cycles, The following digrms correspond to the different types of core/iop ccesses to SDRAM. Additionlly, list of instructions nd SDRAM commnds executed during ech memory ccess is included. Note tht the externl bus is configured to 64 bits wide. Therefore, every dt word (e.g., DA1, DA2, or DB1.) red/written from/to the SDRAM will be 64 bits. The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 30 of 49

31 14.1 Sequentil Reds Without Interruption As shown below, uninterrupted sequentil reds hve throughput of 1 word per cycle fter the first word is red. SCLK 4 Qud-word Sequentil Uninterrupted on Pge Reds trcd CL CMD ACT NOP RD NOP RD NOP RD NOP RD NOP Burst ADDR Row Col Col Col Col DATA DA1 DA2 DB1 DB2 DC1 DC2 DD1 DD2 SDA10 Nr. Cycles Core Controller Dt 1 xr3:0=q[j1+=j4];; ACT 2 int. ACK NOP 3 int. ACK RD 4 int. ACK NOP 5 xr7:4=q[j1+=j4];; RD DA1 6 int. ACK NOP DA2 7 xr11:8=q[j1+=j4];; RD DB1 8 int. ACK NOP DB2 9 xr15:12=q[j1+=j4];; RD DC1 10 int. ACK NOP DC2 11 int. ACK DD1 12 int. ACK DD2 The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 31 of 49

32 14.2 Non Sequentil Reds Without Interruption Similr to uninterrupted sequentil reds, non-sequentil reds lso give 1-word/cycle throughput. SCLK 4 Qud-word Non-sequentil Uninterrupted on Pge Reds trcd CL CMD ACT NOP RD NOP RD NOP RD NOP RD NOP Burst ADDR Row Col Col Col Col DATA DA1 DA2 DB1 DB2 DC1 DC2 DD1 DD2 SDA10 Nr. Cycles Core Controller Dt 1 xr3:0=q[j1+=j4];; ACT 2 int. ACK NOP 3 int. ACK RD 4 int. ACK NOP 5 xr7:4=q[j1+=j4];; RD DA1 6 int. ACK NOP DA2 7 xr11:8=q[j1+=j4];; RD DB1 8 int. ACK NOP DB2 9 xr15:12=q[j1+=j4];; RD DC1 10 int. ACK NOP DC2 11 int. ACK DD1 12 int. ACK DD2 The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 32 of 49

33 14.3 Sequentil Reds with Minimum Interruption In this cse, n dditionl core ccess is performed during core/iop red from SDRAM. As shown below, the SDRAM ccess does not get interrupted, nd it opertes similrly to uninterrupted reds (i.e., 1 word/cycle). Note tht higher number of core ccesses during red from SDRAM my cuse throughput decrese, depending upon system speed nd core ctivity. SCLK 5 Qud-word Sequentil Interrupted on Pge Reds trcd CL CMD ACT NOP RD NOP RD NOP RD NOP RD NOP RD NOP Burst ADDR Row Col Col Col Col Col DATA DA1 DA2 DB1 DB2 DC1 DC2 DD1 DD2 DE1 SDA10 Nr. Cycles Core Controller Dt 1 xr3:0=q[j1+=j4];; ACT 2 int. ACK NOP 3 int. ACK RD 4 int. ACK NOP 5 xr7:4=q[j1+=j4];; RD DA1 6 xr0 = r1 + r2;; NOP DA2 7 xr11:8=q[j1+=j4];; RD DB1 8 int. ACK NOP DB2 9 xr15:12=q[j1+=j4];; NOP DC1 10 int. ACK NOP DC2 The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 33 of 49

34 14.4 Sequentil Writes Without Interruption As shown below, uninterrupted sequentil writes hve throughput of 1 word per cycle. 4 Qud-word Sequentil Uninterrupted on Pge Writes SCLK trcd CMD ACT NOP WR NOP WR NOP WR NOP WR NOP Burst ADDR Row Col Col Col Col DATA DA1 DA2 DB1 DB2 DC1 DC2 DD1 DD2 SDA10 Nr. Cycles Core Controller Dt 1 q[j1+=j4]=xr3:0;; ACT 2 int. ACK NOP 3 int. ACK WR DA1 4 int. ACK NOP DA2 5 q[j1+=j4]=xr7:4;; WR DB1 6 int. ACK NOP DB2 7 q[j1+=j4]=xr11:8;; WR DC1 8 int. ACK NOP DC2 9 q[j1+=j4]=xr15:12;; WR DD1 10 int. ACK NOP DD2 The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 34 of 49

35 14.5 Non Sequentil Writes Without Interruption Similr to uninterrupted sequentil writes, non-sequentil writes lso give 1 word/cycle throughput. SCLK trcd 4 Qud-word Non-sequentil Uninterrupted on Pge Writes CMD ACT NOP WR NOP WR NOP WR NOP WR NOP Burst ADDR Row Col Col Col Col DATA DA1 DA2 DB1 DB2 DC1 DC2 DD1 DD2 SDA10 Nr. Cycles Core Controller Dt 1 q[j1+=j4]=xr3:0;; ACT 2 int. ACK NOP 3 int. ACK WR DA1 4 int. ACK NOP DA2 5 q[j1+=j4]=xr7:4;; WR DB1 6 int. ACK NOP DB2 7 q[j1+=j4]=xr11:8;; WR DC1 8 int. ACK NOP DC2 9 q[j1+=j4]=xr15:12;; WR DD1 10 int. ACK NOP DD2 The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 35 of 49

36 14.6 Sequentil Writes with Minimum Interruption In this cse, n dditionl core ccess is performed during core/iop write to SDRAM. As shown below, the SDRAM ccess does not get interrupted, nd it opertes similrly to uninterrupted writes (i.e., 1 word/cycle). Note tht higher number of core ccesses during write to SDRAM my cuse throughput decrese, depending upon system speed nd core ctivity. SCLK trcd 4 Qud-word Sequentil Interrupted on Pge Writes CMD ACT NOP WR NOP WR NOP WR NOP WR NOP Burst ADDR Row Col Col Col Col DATA DA1 DA2 DB1 DB2 DC1 DC2 DD1 DD2 SDA10 Nr. Cycles Core Controller Dt 1 q[j1+=j4]=xr3:0;; ACT 2 int. ACK NOP 3 int. ACK WR DA1 4 int. ACK NOP DA2 5 q[j1+=j4]=xr7:4;; WR DB1 6 xr0 = r1 + r2;; NOP DB2 7 q[j1+=j4]=xr11:8;; WR DC1 8 int. ACK NOP DC2 9 q[j1+=j4]=xr15:12;; WR DD1 10 int. ACK NOP DD2 The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 36 of 49

37 14.7 Reds Between Pge/Bnk Core/IOP reds from SDRAM interrupted by off-bnk/pge ccesses. Crossing bnk/pge boundries impcts performnce, giving 1 word per 6 cycles throughput. Sequentil Reds between Pges or Bnks SCLK CL trp trcd CL CMD RD NOP BST PREA NOP ACT NOP RD NOP RD NOP Burst Burst ADDR Col Row Col Col DATA DA1 DA2 DB1 DB2 DC1 DC2 SDA10 Nr. Cycles Core Controller Dt 1 xr3:0=q[j1+=260];; ACT 2 int. ACK NOP 3 int. ACK RD 4 int. ACK NOP 5 int. ACK BST DA1 6 int. ACK PREA DA2 7 int. ACK NOP 8 xr7:4=q[j1+=j4];; ACT 9 int. ACK NOP 10 int. ACK RD 11 int. ACK; NOP 12 xr11:8=q[j1+=j4];; RD DB1 13 int. ACK; NOP DB2 14 xr15:12=q[j1+=j4];; RD DC1 15 int. ACK; NOP DC2 The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 37 of 49

38 14.8 Writes Between Pge/Bnk Core/IOP writes to SDRAM interrupted by off-bnk/pge ccesses. Similr to red ccesses, lthough smller, crossing bnk/pge boundries gretly impct performnce, giving 1 word per 6 cycles throughput. Sequentil Writes between Pges or Bnks SCLK trp trcd CMD WR NOP BST PREA NOP ACT NOP WR NOP Burst Burst ADDR Col Row Col DATA DA1 DA2 DB1 DB2 SDA10 Nr. Cycles Core Controller Dt 1 q[j1+=260]=xr3:0;; ACT 2 int. ACK NOP 3 int. ACK WR DA1 4 int. ACK NOP DA2 5 int. ACK BST 6 int. ACK PREA 7 int. ACK NOP 8 q[j1+=j4]=xr7:4;; ACT 9 int. ACK NOP 10 int. ACK WR DB1 11 int. ACK NOP DB2 The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 38 of 49

39 14.9 Minimum Red-to-Write Intervl The following digrm shows n SDRAM red-to-write trnsction. As shown below, the trnsition from one ccess to nother introduces overhed cycles (fixed to CL vlue), resulting performnce loss of 1 word per 2 cycles. SCLK On Pge Red to Write Trnsction trcd CL CMD ACT NOP RD NOP BST NOP NOP WR NOP Burst CL Burst ADDR Row Col Col DATA DA1 DA2 DB1 DB2 SDA10 Nr. Cycles Core Controller Dt 1 xr3:0=q[j1+=j4];; ACT 2 int. ACK NOP 3 int. ACK RD 4 int. ACK NOP 5 int. ACK BST DA1 6 int. ACK NOP DA2 7 int. ACK NOP 8 q[j1+=j4]=xr7:4;; WR DB1 9 int. ACK NOP DB2 The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 39 of 49

40 14.10 Minimum Write-to-Red Intervl The following digrm shows n SDRAM write-to-red trnsction. Similr to red-to-write trnsitions, some cycles of overhed re introduced, resulting in loss of performnce of 1 word per 4 cycles. SCLK On Pge Write to Red Trnsction trcd CL CMD ACT NOP WR NOP BST RD NOP Burst Burst BST ADDR Row Col Col DATA DA1 DA2 DB1 DB2 SDA10 Nr. Cycles Core Controller Dt 1 q[j1+=j4]=xr3:0;; ACT 2 int. ACK NOP 3 int. ACK WR DA1 4 int. ACK NOP DA2 5 int. ACK BST 6 xr7:4=q[j1+=j4];; RD 7 int. ACK NOP 8 int. ACK BST DB1 9 int. ACK NOP DB2 The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 40 of 49

41 14.11 Chined DMA Trnsfers Higher throughput cn be chieved by using chined DMAs. However, s shown below, performnce difference cn be seen between chined DMA writes nd reds to nd from SDRAM. Loding the TCB for chined red DMA requires dditionl core cycles. Chined DMA Reds SCLK CL CL trcd CL CMD RD NOP RD NOP BST 2 NOPS 9 PREA ACT NOP NOPs RD NOP RD NOP ADDR Col Loding of TCB Row Col DATA DA1 DA2 DB1 DB2 DC1... SDA10 Chined DMA Writes SCLK trcd CMD ACT NOP WR NOP WR NOP WR NOP WR NOP WR NOP Burst ADDR Row Col Col Col Col Col DATA DA1 DA2 DB1 DB2 DC1 DC2 DD1 DD2 DE1 DE2 SDA10 The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 41 of 49

42 14.12 Auto-Refresh The refresh counter triggers refresh requests when expired. The following digrm shows the refresh sequence. All bnks re prechrged (SDA10 is sserted high) right fter the internl counter issues the refresh. A REF commnd strts n internl row refresh with CAS before RAS. During refresh, other commnds cnnot be executed. The rtio between ppliction time nd refresh time is given by: t RC = 15,625 µs/row, (e.g., 16 cycles/3700 cycles x 100 = 0.43%) This mens tht the refresh sequence requires 0.43 % of the whole performnce t 100 MHz. Auto-refresh with 15,625 µs/row provideds the best performnce rtio. This rtio cn be modified ccordingly to the system needs by chnging the refresh rte progrmmed in SDRCON. Auto Refresh 100 MHz CL=2, tras=5, trp=2 SCLK CMD BST NOP NOP PRE NOP REF NOP NOP ACT NOP Refresh counter expired CL trp trc = tras + trp continue norml opertion SDA10 The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 42 of 49

43 14.13 Self-Refresh nd Host Accesses The following digrms show rndom host ccess during red from SDRAM: Host Bus Request during SDRAM Reds - Host Entry SCLK ~HBR Host requests the bus to the DSP ~HBG Host is grnted the bus SDCKE Burst CL trp CMD RD NOP RD NOP BST 2xNOP PREA NOP SREF ADDR Col Col BST issued to grnt the host ccess Enter Self-refresh mode SDA10 Host Bus Grnt during SDRAM Reds - Host Exit SCLK ~HBR Host relinquishes the bus ~HBG SDCKE CMD SREF SREF NOP NOP NOP ACT NOP Open bnk nd continue with norml opertion RD ADDR Exit Self-refresh mode txsr = trc = tras + trp Row Col SDA10 After detecting host request, the current burst opertion of the SDRAM controller is interrupted nd frozen. The TigerSHARC processor enters self-refresh mode, in response to host bus request (~HBR), The ADSP-TS20x TigerSHARC Processor On-chip SDRAM Controller (EE-201) Pge 43 of 49