5 Regular 4-Sided Composition

Transcription

1 Xilinx-Lv User Guide 5 Regulr 4-Sided Composition This tutoril shows how regulr circuits with 4-sided elements cn be described in Lv. The type of regulr circuits tht re discussed in this tutoril re those where dt flows in two or more directions, including directions perpendiculr to ech other. Two clsses of circuits tht hve these dt flow chrcterics re systolic rrys nd rithmetic opertors. We will demonstrte the fetures of Lv for composing regulr circuits with 4- sided elements using the exmple of constnt dder/subtrctor design. Before describing this design, we first introduce the model of 4-sided elements used by the stndrd Lv combintors. Becuse 4-sided elements re connected together in 2-dimensionl rry, they re referred to here s 4-sided tiles Sided Tiles Lv includes set of combintors tht interpret the inputs nd outputs of circuit blocks ccording to two-dimensionl model. The reltionship between this two-dimensionl model nd the input nd output types of the circuit is shown in Figure 5.. A circuit is considered four sided tile if it hs type which tkes two element tuple s its input nd returns two element tuple. Figure 5. Mpping of inputs nd outputs to the sides of 4-sided circuit element. The type of the 4- sided tile is (,b) -> (c,d). d b c A four sided tile is divided into the input signl nd output signl portions by the gry digonl line. The inputs re represented by tuple (, b) in which the signl is connected to the bottom of the tile nd the b signl is connected to the left of the tile. These signls cn be of ny type nd so cn consist of more thn one wire. The outputs re represented by tuple (c, d) in which the c signl is connected to the right hnd side of the tile nd the d signl is connected to the top of the tile. This model is not pplicble to ll 35

2 4-Sided Tiles circuits with 4-sided tiles, but Lv is not limited to this model. A user cn crete ny model they wish to suit their pplictions by creting their own combintors. To combine nd plce two 4-sided tiles verticlly, Lv provides the below combintor. Figure 5.2 shows the result of the composition: r `below` s Figure 5.2 Connecting two 4-sided tiles together with the below opertor. g e s f x b r c The circuit r hs the type (,b) -> (c, x) nd the circuit s hs the type (x,e) -> (f, g) nd the composite circuit hs the type (, (b, e)) -> ((c, f), g) where x is the type of the intermedite signl tht r nd s communicte long. To combine two 4-sided tiles horizontlly, Lv provides the beside combintor. The composition r `beside` s plces s to the right of r. Lv provides prmetrized combintors to replicte nd compose four sided tiles in row nd columns. The row combintor replictes nd composes tile horizontlly from left to right nd tkes prmeter tht determines number of times tile is to be replicted. The col combintor replictes nd composes tile verticlly from bottom to top. The resulting type of pplying the col combintor to the tile in Figure 5. is (, [b]) -> ([c], d) nd the resulting type of pplying the row combintor is ([], b) -> (c, [d]). The row nd col combintors cn be used together to form 2-dimensionl rry of 4-sided tiles. The use of these opertors is demonstrted in the next section by the constnt dder/subtrctor design. 36

3 Constnt Adder/Subtrctor Design 5.2 Constnt Adder/Subtrctor Design This section demonstrtes the use of 4-sided tile combintors by providing the steps required to describe constnt dder/subtrctor design in Lv. Figure 5.3 shows constnt dder/subtrctor implementtion tht uses circuit blocks specific to the Xilinx Virtex rchitecture. The repeting element is 4-sided tile tht implements -bit constnt dder/subtrctor. This dds or subtrct one of four constnt bits to the input bit. This is combined using ripple-crry rchitecture to implement n n-bit dder/subtrctor. The input s selects between the dd mode when low, nd the subtrct mode when high. The constnts re selected by the signls m nd m. The min steps required to describe this circuit re to firstly describe the repeting element, nd then secondly compose them whilst distributing the inputs nd outputs ccordingly. Figure 5.3 Constnt dder/subtrctor design. The repeting element is 4-sided tile tht is composed in column. The Virtex dedicted crry chin components re used to optimise the performnce nd resource usge of the design. The input s selects between the dd mode when low, nd the subtrct mode when high. Four constnts re stored in the LUTs; they re selected using the signls m nd m. cout n muxcy xorcy sum n muxcy xorcy sum muxcy xorcy sum s m m 37

4 Constnt Adder/Subtrctor Design The muxcy nd xorcy circuit blocks re dedicted resources provided in the Virtex slice. They re connected in the configurtion shown in Figure 5.3 nd provide n efficient wy to build ripple-crry rithmetic circuits. To construct full dder in single slice, the LUT is configured s n XOR gte. We wish to provide some dditionl functionlity within the LUT; subtrct mode nd 4 constnts. Figure 5.4 shows wy in which this cn be chieved. Figure 5.4 Constnt dder/subtrctor LUT. The constnts c-c3 re encoded in the tble by prtilly pplying them to the LUT initilistion function. m m c c c2 o c3 s The finl XOR provides the dd functionlity, the preceding XOR inverts the constnt opernd when in subtrct mode nd the multiplexors select between the four constnts. The contents of the 4-input LUT cn be provided, s before, using n initilising function. The constnts cn be then be encoded by prtil ppliction. The gry re denotes the prt of the circuit tht is trnsformed to constnt 2-input function by prtil ppliction. The initilising function is written in Lv s follows: ddsubconst4func c c c2 c3 s m m = (((muxfn m (muxfn m c c) (muxfn m c2 c3)) == s) == ) It is used to initilise the LUT, prtil pplying the constnts c, c, c2 nd c3, s follows: (ddsubconst4func c c c2 c3) The type of the constnts c, c, c2 nd c3 is Bool. 38

5 Exercises The repeting tile fits within one hlf of Virtex slice nd so cn composed using nmed wires s follows: onebitaddsubconst4 :: Bit -> Bit -> Bit -> (Bit, (Bit, Bool, Bool, Bool, Bool)) -> (Bit, Bit) onebitaddsubconst4 s m m (cin, (, c, c, c2, c3)) = (sum, cout) where prt_sum = (ddsubconst4func c c c2 c3) (, s, m, m) sum = xorcy (prt_sum, cin) cout = muxcy (prt_sum, (, cin)) Since the inputs c, m nd m fn-out cross ech of the tiles then they re not included in the 4-sided composition. They therefore re prtilly pplied to give 2-element tuple, the correct type for 4-sided composition. The crry input cin is the lower input, nd the opernd input nd the constnts c-c3 re the left inputs. To compose the tiles into column of size n we use the col combintor. Since the type of the left input is (Bit, Bit, Bit, Bit, Bit) the col combintor results in the type (Bit, [(Bit, Bit, Bit, Bit, Bit)]) -> ([Bit], Bit). It is convient to represent ech of the left multi-bit inputs s lists. In this cse, we need function to give the type [(Bit, Bit, Bit, Bit, Bit)]. As for the exmple in lst tutoril we cn use zip function. We need five element zip function nd since it is not in the stndrd librry, we need to define it ourselves: zip5 :: [] -> [b] -> [c] -> [d] -> [e] -> [(, b, c, d, e)] zip5 [] [] [] [] [] = [] zip5 (:s) (b:bs) (c:cs) (d:ds) (e:es) = (, b, c, d, e) : zip5 s bs cs ds es Now, the composition of the column cn be completed s follows: ddsubconst4 :: Int -> Bit -> Bit -> [Bool] -> [Bool] -> [Bool] -> [Bool] -> (Bit, [Bit]) -> ([Bit], Bit) ddsubconst4 n m m c c c2 c3 (s, ) = col n (onebitaddsubconst4 s m m) (s, (zip5 c c c2 c3)) 5.3 Exercises. Describe the circuit onebitaddsubconst4 using combintors. 2. Using onebitaddsubconst4 nd the row combintor, design circuit to implement the function: sum = + k s + k s + + k m s m where k i = { c, c, c 2, c 3 } nd s i = {, } 39

6 4 Exercises