Engineer To Engineer Note

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1 Engineer To Engineer Note EE-169 Technicl Notes on using Anlog Devices' DSP components nd development tools Contct our technicl support by phone: (800) ANALOG-D or e-mil: Or visit our on-line resources nd Estimting Power For The ADSP-TS101S Contributed by Greg F. Februry 24, 2003 Introduction This EE note will discuss power consumption estimtion bsed on chrcterized mesurements for the ADSP-TS101S digitl signl processor. The motivtion for this document is to ssist bord designers by providing dt s well s recommendtions tht will llow the designer to estimte their power budget for their power supply nd therml relief designs. The ADSP-TS101S is n ultr-high-performnce, sttic supersclr, 32-bit processor from the TigerSHARC DSP fmily of Anlog Devices. The DSP opertes t core clock frequency of 300 with the core operting t 1.2V (V DD ) nd the I/O operting t 3.3V (V DD_IO ). The dt presented in this EE note is ctul mesured power consumption for silicon revision 0.2 of the ADSP-TS101S. Power Consumption Totl power consumption hs two components, one due to internl circuitry nd one due to the switching of externl output drivers. The following sections will show how to derive both of these power numbers. Internl Power Consumption Estimtion The internl power consumption (on the V DD supply) is dependent on the instruction execution sequence nd the dt opernds involved. Anlog Devices provides current consumption numbers for discrete ctivity levels. System ppliction code cn be mpped to these discrete numbers to estimte internl power consumption for n ADSP-TS101S processor for given ppliction. Tble 1 below shows the current consumption for the DSP t different levels of ctivity. From these internl ctivity levels (nd from n understnding of the progrm flow using profiling or some other mens), you cn clculte weighted-verge of power consumption for ech ADSP-TS101S processor in system. Prmeter Test Conditions I DD (A) I DDMAX I DDTYP I DDCTRL I DDDMA I DDIDLE I DDIDLELP Tble 1: Internl Power Vectors Internl Power Vector Definitions The following power vector definitions pply to the internl verge power vectors shown bove in Tble 1: I DDMAX --- V DD supply current for mximum ctivity. Mximum ctivity is SIMD qud 16-bit fixed-point Copyright 2003, Anlog Devices, Inc. All rights reserved. Anlog Devices ssumes no responsibility for customer product design or the use or ppliction of customers products or for ny infringements of ptents or rights of others which my result from Anlog Devices ssistnce. All trdemrks nd logos re property of their respective holders. Informtion furnished by Anlog Devices Applictions nd Development Tools Engineers is believed to be ccurte nd relible, however no responsibility is ssumed by Anlog Devices regrding the technicl ccurcy nd topiclity of the content provided in ll Anlog Devices Engineer-to- Engineer Notes.

2 multiply nd n dd in prllel with two qud-word dt fetches. The dt fetched nd operted on re rndom. This vector includes DMA ctivity s described below in the I DDDMA definition. I DDTYP --- V DD supply current for typicl ctivity. Typicl ctivity is SIMD qud 16-bit fixed-point compute opertion in prllel with two qud-word dt fetches. The dt fetched nd operted on re rndom. This vector includes DMA ctivity s described below in the I DDDMA definition. I DDCTRL --- V DD supply current for control ctivity. Control ctivity is continuous decision-mking nd predicted brnches. The brnch prediction is delibertely set to be incorrect 50% of the time for equl distribution. This vector includes DMA ctivity s described below in the I DDDMA definition. I DDDMA --- V DD supply current for DMA ctivity. DMA ctivity is single externl port DMA from externl to internl memory, qud-word trnsfers of 32 words totl. The DMA is chined to itself (in order to run continuously), nd the DMA does not use interrupts. After setup, the core is not involved, executing the IDLE instruction only. I DDIDLE --- V DD supply current for idle ctivity. Idle ctivity is the core executing the IDLE instruction only with no DMA or interrupts. I DDIDLELP --- V DD supply current for idle low power. Idle Low Power ctivity is the core executing the IDLE(LP) instruction only with no DMA or interrupts. The verge current consumption for n ADSP- TS101S for specific ppliction is clculted ccording to the following formul, where % is the percentge of the overll time tht the ppliction spends in tht stte: (% Mximum Activity Level x I DDMAX ) (% Typicl Activity Level x I DDTYP ) (% Control Activity Level x I DDCTRL ) (% DMA Activity Level x I DDDMA ) (% Idle Activity Level x I DDIDLE ) + (% Idle Low Power Activity Level x I DDIDLELP) = Totl Current for V DD = I DD Eqution 1: Internl Current (I DD ) Clcultion Therefore, the estimted verge internl power consumption (P DD ) cn be clculted s P DD = I DD x V DD Eqution 2: Internl Power (P DD ) Estimtion Clcultion For exmple, fter profiling the ppliction code the entire system ctivity is determined s - 30% Mximum Activity Level - 30% Typicl Activity Level - 20% DMA Activity Level - 20% Idle Activity Level Exmple 1: Internl System Activity Level Exmple From the percentges of this exmple, one cn estimte vlue for the current consumption of single processor s (30% x A) (30% x A) (20% x A) + (20% x A) = A = I DD Exmple 2: Internl Current Estimtion Exmple Therefore, the verge internl power estimtion for the processor cn be clculted from exmple 2 bove s P DD = A x 1.20V = 3W Exmple 3: Internl Power Estimtion Exmple Externl Power Consumption Estimtion The externl power consumption (on V DD_IO ) is consumed by the switching of the output pins nd is system dependent. For ech unique group of pins, the mgnitude of power consumed depends on the following: The number of output pins tht switch during ech cycle, O The lod cpcitnce of the output pins, C Their voltge swing, V DD_IO The mximum frequency t which the pins cn switch, f Estimting Power For The ADSP-TS101S (EE-169) Pge 2 of 5

3 The lod cpcitnce should include the input cpcitnce of ech connected device s well s the DSP's own input cpcitnce (C IN ). For dditionl ccurcy, trce cpcitnce should be included if possible. The switching frequency includes driving the lod high nd then bck low. Address nd dt pins cn drive high nd low t mximum frequency of ½ SCLK (50). Eqution 3 below shows how to clculte the verge externl current (I DD_IO ) given the bove prmeters: I DD_IO = O x C x V DD_IO x f Eqution 3: Externl Current (I DD_IO ) Clcultion Therefore, the estimted verge externl power consumption (P DD_IO ) cn be clculted s P DD_IO = I DD_IO x V DD_IO Eqution 4: Externl Power (P DD_IO ) Clcultion For exmple, estimte P DD_IO for the externl port pins with the following ssumptions: The exmple system consists of four ADSP- TS101S processors with one bnk of shred externl memory (64-bit), where C IN = 5pF per TigerSHARC DSP. Two 1M 32 SDRAM chips re used, ech with lod of 5 pf per pin (trce cpcitnce is neglected for this exmple). Continuous burst of qud-word (128-bit) writes occur every cycle t rte of SCLK, with 50% of the dt pins switching (this represents rndom dt). The externl ddress increments sequentilly on trnsction boundry (every qudword). For sequentil ddressing, the number of ddress bits switching per cycle pproches 2-bits. The control pins switch for refresh cycles nd pge boundry crossings. SCLK = 100Mhz (bus cycle time). The I DD_IO eqution is clculted for ech clss of pins tht cn drive s shown in Tble 2. Pin Type # of Pins % Switching Dt pF Addr pF Ctrl pF x C x V DD_IO x f = I DD_IO 3.3V V V 250 KHz Tble 2: Externl Current (I DD_IO ) Clcultion Exmple A A A From the dt tbulted in Tble 2 bove, the externl verge current consumed by the DSP cn be clculted by summing ll of the dt from the right-most column: I DD_IO = A A A Exmple 4: Totl Averge Estimted Current Clcultion Using the result from Exmple 4, the estimted verge externl power cn be clculted s P DD_IO = A x 3.3V Exmple 5: Totl Averge Estimted Power Clcultion Therefore, from this exmple system n estimted totl of W hs been clculted s the verge externl power consumption for our system. Power Supply Design From the previous two sections we hve shown how to estimte the verge current nd power consumption vlues for the internl nd externl power domins for given system. When designing power supply, the designer must ensure tht the power supply is cpble of hndling worst-cse sustinble power consumption. Therefore, gurd-bnded vlues for the mximum internl (P DD ) nd externl (P DD_IO ) power requirements should be used. Estimting Power For The ADSP-TS101S (EE-169) Pge 3 of 5

4 This will ensure tht the power supply design will provide sufficient voltge t reltively high efficiency (typiclly greter thn 90%) to ech of the two voltge domins (V DD nd V DD_IO ) during sustined periods of mximum ctivity. This is due to the fct tht the power required during sustined mximum operting condition my be greter thn wht cn be supplied by bypss nd/or bulk cpcitnce. For the core voltge (V DD ), the power supply design must be cpble of supplying the mximum sustinble power consumption under worst-cse conditions. This specific vlue is I DDMAX (from Tble 1), V DD = 1.26V, 85 C, nd 300 (from the dt sheet). For the I/O domin (V DD_IO ), the power supply design must be cpble of supplying gurd-bnded conservtive power consumption estimte for I/O ctivity (V DD_IO = 3.45V, from the dt sheet). This is to ensure sufficient overhed in the power supply design during sustined periods of high ctivity on the I/O domin. Another criticl specifiction when selecting power supply (tht cn properly supply your system within norml operting specifictions nd t mximum efficiency) is the mximum di/dt required by the processor. This number is simply the worst-cse chnge in current required by the processor over short time intervl. This specifiction corresponds with the response time of your power supply. We cn clculte the vlue for di/dt mx s n externl interrupt, due to the length of the processor s instruction pipeline. Therml Relief Design The overll system power estimtion cn lso be used to estimte the requirements for therml relief design. Eqution 5 below gives vlue for the totl verge estimted power. Note tht this eqution yields totl estimted verge power consumption for single ADSP-TS101S in given system. Gurd-bnding this vlue is recommended for therml relief design tht will llow the system to operte within specified therml prmeters. P TOTAL = V DD x I DD + V DD_IO x I DD_IO Eqution 5: Totl Estimted Averge Power Note tht gurd-bnded vlues tken t worstcse conditions (V DD = 1.26V, f = 300, temp = 85 C), re used when considering design for therml relief. Therefore, for the complete system exmple, (which is comprised of cluster of four ADSP- TS101S processors nd shred bnk of externl memory comprised of two 1M x 32 SDRAM chips), we cn estimte the totl system power budget s P TOTAL = P DD (verge) + P DD_IO (verge) Eqution 6: Totl System Power Clcultion di/dt MAX = (I DDMAX I DDIDLE ) / (8 x t CCLK ) = (1.5460A A) / (8 x 3.3ns) = A/µs Exmple 6: Mximum di/dt Clcultion Where t CCLK represents the core clock period of the DSP while operting t frequency of 300, nd the vlue 8 represents the minimum number of cycles to exit n idle instruction vi Estimting Power For The ADSP-TS101S (EE-169) Pge 4 of 5

5 Compenstion Curves The following section of this EE note shows I DDMAX compenstion curves versus the minimum nd mximum llowble vlues for processor core voltge, operting frequency, nd operting temperture. These curves cn be used to extrpolte dt (from Tble 1) to estimte more precise vlues for system, depending upon the specific opertionl prmeters of the system. Figure 1 shows grph for the mximum internl current (I DDMAX ) versus V DD operting rnge tolernces. The dt for this grph ws obtined while operting the processor t its mximum operting frequency nd t nominl operting temperture, 300 nd 25 C, respectively. Iddmx Current vs. Voltge (@ 25C, 300) Iddmx Current vs. Temperture (@ 1.20V, 300) Temp (C) Figure 2: I DDMAX Current vs. Temperture Figure 3 shows grph for the mximum internl current (I DDMAX ) versus the specified operting frequency rnge. The dt for this grph ws obtined while operting the processor t its nominl temperture nd voltge, 25 C nd 1.20V, respectively Voltge (V) Figure 1: I DDMAX Current vs. Voltge Figure 2 shows grph for the mximum internl current (I DDMAX ) versus the specified temperture operting rnge. The dt for this grph ws obtined while operting the processor t its mximum operting frequency nd t nominl V DD, 300 nd 1.20V, respectively Frequency () Iddmx Current vs. Frequency (@25C, 1.20V Vdd) Figure 3: I DDMAX Current vs. Frequency Document History Version Feb 24, 2003 by Greg F. Sep 23, 2002 by Greg F. Description Updted Dt For 300 Upgrde Initil Relese Estimting Power For The ADSP-TS101S (EE-169) Pge 5 of 5