System Level Design with IBM PowerPC Models

Transcription

1 September 2005 System Level Design with IBM PowerPC Models A view of system level design SLE-m3

2 The System-Level Challenges Verification escapes cost design success There is a 45% chance of committing a logical/functional error when designing an IC/ASIC Source: Collett International Research 2003 IC/ASIC Design Closure Study Can no longer verify large systems at detail level Functionality convergence challenges validation Multipurpose devices - video phone, MP3 etc Functional validation and test is very complex Multiple IP blocks bring interface problems Integration, interconnect and interoperability issues Software dominance of most designs Need early executable hardware specification Desire to have physical and power information earlier in the development cycle 2

3 Traditional Simplified Flow Weak link between specification and implementation Specification(s) Limited ability to address complexity, assess full range of tradeoffs Application RTOS BSP (drivers) Co-Verification HDL - Design Debug Verification Software Hardware 3

4 There is a Need for Something New Consistent verification from concept to implementation Paper Specification System Model More abstract system model Faster to create and simulate More what if s Application RTOS BSP (drivers) HDL - Design Debug Verification Software Hardware 4

5 An Evolution of the Traditional Flow Paper Specification High Level Model System High Level Model Executable Specification Software Virtual Prototype Hardware High Level Model Consistent Verification Requirements follow-up Application RTOS BSP (drivers) Co-Verification HDL - Design Debug Verification Software Hardware 5

6 System Level Tasks and Stages Functional Requirements Algorithmic Level Explore Functional the feasibility design and of verification, requirements Functional design and verification, exploration of the functional requirement list Uncommitted Systems Partition HW System and SW Exploration - Define the Level architecture System executable specification, architecture exploration, Finalize the specification HW/SW partitioning, mapping of functional list on HW/SW resources System Level Design Create Hardware a first Transaction prototype of Level the HW Create a verification infrastructure Hardware virtual prototyping, high level verification environment, architecture refinement, performance verification Implement Register the hardware Transfer at Level register level Hardware Committed Gates 6

7 Advantages of System Level Design Functional behavior validated early in the process speeds the flow to working silicon Fast execution allows architectural exploration to find the best design alternatives and encourages more testing to eliminate functional bugs The system level model serves as a rapid, updateable early prototype to support concurrent software development 7

8 A view of system level design UML xtuml Executer & Compiler RTOS Compilers/Debuggers C Software Code Flow Applications Middleware Manual Design / / Interface Automation C Compiler / / linker Host linker / Target Code RTOS TLM Models TLM TLM Virtual Prototype Virtual Prototype for SW for SW C Algorithm Algorithmic C Synthesis Architecture Hardware IP Logic Design IP Library Flow Verification System Assembly Simulation Environment Performance Performance Metrics Metrics Power Metrics Power Metrics Physical Design Golden Golden Verification Model Verification Model Verified Verified Implementation Implementation Manual Design 8

9 Merged MGC - IBM SLD PowerPC Platform Embedded Systems xtuml Nucleus BridgePoint BEAM C/C ++ /SystemC (Co)Simulation HDL & C-Based C Design HDL Designer Catapult C H2C Model Express Platform Express SoC Virtual Design Creation DesignAnalyst HDL Seamless Perspecta Digital Simulation TOS A B V C D V A V M Modelsim Testbenches: SystemC/SystemVerilog/C/C++/PSL SystemVerilog/C/C++/PSL Verilog/VHDL MGC IBM IBM ChipBench SOC Virtual Design Creation Floorplanning Power Analysis Voltage Islands Implementation 9

10 Modeling Abstraction / Languages Behavioral Specification Architectural Exploration UML C/C++ Transaction-level Verification Cycle Accurate Verification SystemC System Verilog Verification 10

11 xtuml for Initial System Modeling Graphical UML Entry Use functional requirements specification as input Build platform-independent executable models of the Application & Test Suite UML Build & Compile C Code Generate 100% C/C++ Code from the model Future? Model Debug Model Verifier C Algorithm TLM Models Reference external models such as C/C++ algorithms suitable for Catapult C Future: xtuml to TLM Compiler could build Software + Hardware platform for performance analysis & architecture validation 11

12 Algorithmic C Synthesis Use TLM Performance Analysis to Refine Block Constraints Use ANSI C++ : Focus on the Functional Intent Explore the design space to find the optimum micro-architecture Constraints TLM Models TLM C Algorithm Algorithmic C Synthesis Generate TLM models (un-timed, timed & CA) Simulation Environment Synthesize & Generate testbench infrastructure Links to Simulation Environments 12

13 Transaction Level Modeling & Simulation Use Interface Generation Tools to simplify new TLM creation Assemble Structural System Design from existing IP and new user-created models Validate and analyze system function and performance Generate additional TLMs from xtuml or C++ algorithms Processor cores for software execution Manual Design / / Interface Automation TLM Models IP IP Library TLM System Assembly OSCI TLM and SPIRIT standards increase IP library availability Host/Target Code TLM Simulation Environment TLM simulation speed 100k -> 2M IPS Virtual Prototype Virtual Prototype for SW for SW Performance Performance Metrics Metrics Power Metrics Power Metrics Simulation Environment common between TLM and 13

14 With the Introduction of Synthesis, Automation and Re-Use Algorithmic C Synthesis Manual Design High Level Models Auto TLM I/F IP Library 14

15 The Value of High Level Modeling is Made Accessible Architects Software Team High Level Models Verification Team Design Team 15

16 To Provide a Complete System-level Design Process Behavioral / Functional Modeling Capture design as as executable specification Validate functionality Performance analysis includes timing & power Both s/w and h/w dependent effects Generate S/W Code (& (& TLMs) Structure design Validate architecture Analyze performance Architectural Design Application S/W Validation Compile & Link Refine block timing & power Synthesize Micro-Architecture Implementation Application Testing S/W <-> H/W integration testing is done at TLM & Verification 16

17 The Vision of System-Level Design Architectural Analysis With functional, performance and power models Early Software Development With rapid adaptable virtual prototypes Higher Quality Design With progressive refinement to implementation Better Verification With Transaction Based methodologies Continuous refinement Bi-directional flows 17

18 Key Productivity Directions Model system or function at the highest appropriate level xtuml for system behavior TLMs for architecture C++ for algorithms Automation & Re-Use xtuml to embedded C code C++ algorithm to SystemC TLM Automated SystemC TLM interface generation xtuml to TLM TLM Model Interoperability Catapult C, Perspecta, Questa, virtual prototypes C++ algorithm to Embedded PowerPC aware platform 18

19 A View of System Level Design Technologies & Methodologies Conclusion

20 Transaction Level Modeling Algorithmic TLM A Generic CPU (B, C and ctrl) A Specific CPU - ISS (B, C and ctrl) A C D TLM Channel TLM API TLM API Bus TLM API TLM API B D Transactions Mem D Mem This is a methodology, also known as TLM, that defines new abstraction levels above the register. It is itself made of several stages, which gradually abstract from hardware implementation constraints but still with a structured view of the design. Its goal is to reduce the number of events and the amount of data that has to be treated during simulation. This modeling method is built as a set of interfaces that define how models communicates. 20

21 System Designer Hardware Designer MATLAB SPW C/C++ Manual Methods Architectural Synthesis Typical Design Flow Algorithm Functional Description Floating Point Model Fixed Point Model Micro-architecture Definition Design Flow vs. Catapult C Flow + NEW Catapult C Design Flow Algorithm Functional Description Floating Point Model Fixed Point C++ Model + Catapult C Constraints Synthesis Synthesis Place & Route Hardware ASIC/FPGA Logic Analyzer Vendor Precision or DC ASIC or FPGA Vendor Area/Timing Optimization Synthesis Place & Route Hardware ASIC/FPGA Logic Analyzer Safer design flow Shorter time to More efficient methodology Design optimized to system requirements through incremental refinement 21

22 Catapult C Synthesis Algorithm to Architectural Architectural Constraints Constraints Technology Technology Files Files Develop Develop Algorithms Algorithms using using ANSI ANSI C++ C++ No No proprietary proprietary extension extension Focus Focus on on the the functional functional intent intent Synthesize Synthesize with with Catapult Catapult C Explore Explore the the design design space space Find Find the the optimal optimal architecture architecture Generate Generate High High Speed Speed Models Models Verilog, Verilog, VHDL, VHDL, SystemC SystemC Accelerate Accelerate system system level level verification verification Generate Generate Target Target Optimized Optimized Faster Faster and and better better than than hand-coded hand-coded For For ASIC, ASIC, FPGA FPGA or or FPGA FPGA prototyping prototyping of of ASICs ASICs Automatically Automatically Verify Verify the the Generation Generation of of testbench testbench infrastructure infrastructure Seamlessly Seamlessly reuse reuse original original C++ C++ test test vectors vectors Untimed Untimed TLM TLM Timed Timed TLM TLM Cycle Cycle TLM TLM 22

23 System-Level Design Perspecta Modeling components Processor & IP libraries Model integration tools System Architecture Assemble and modify design Performance analysis Throughput, bandwidth Design validation Functional and performance goals HW/SW co-design Full system integration Verification Hardware & software functional test my Algorithm switch( m_state ) { case RES_WAIT : if( rsp_fifo._get( rsp ) ) { send_resp( rsp ); } break; Model Express Component Libraries Perspecta MEM MEM CPU System Level Assembly Co-Proc Bridge Software Debugging Environment Peri 1 Peri 2 System Analysis 23

24 Power Analysis in Perspecta Provides a mechanism to dynamically record and display power consumption across the whole system Suitable for comparison of different architectural options Includes software dependent effects Accuracy is driven by power characterization data available to the modeler Can be data book level or better Only limited by level of the TLM in question 24

25 Component Power Modeling Within the functional model Associate known power profile with each distinct model state Use an API to set the new mode dependent state Allocate energy value for particular events Also records the duration Modeling power requires Addition of handful of API calls inside existing model High-level power characterization of the blocks being modeled IDLE mode Processing Mode Data Transmit Mode 64b 400ns 32nJ I/O 20uW 500uW 300uW 64b * (0.5nJ/b write energy) = 32nJ 16 word burst = 5clks(init) + 15x1clks(beat) = 20 20clks * 20ns period = 400ns 25

26 System Power Allocation Power consumption elements CPU Based on clock frequency Memory accesses Read / write set by range Memory controller DMA engine Other processing units (accelerators) I/O elements Including bus bridges Advanced interconnects Form-based (or custom power models) Power enabled TLM models 26

27 Seamless: Verify Hardware and Software at the Same Time with the Same Data Drops in to existing environment Customer s Simulator Seamless Bus Model + Memories Bus Monitors Common environment eliminates ambiguity description replaces the need for stub code Embedded software provides hardware testbench Customer s Embedded Code Code profiling 27

28 Profiler Views Software Profile Software Gantt Bus Delay Bus Load Power Memory Heat Map 28

29 Progressive Refinement to Component Library Assemble Transaction Level Models Create new elements Simulate to validate functionality, performance & power Substitute IP models Synthesize algorithms Seamless Add specific blocks Floorplan, Power Islands & Implement 29

30 System-Level Software BridgePoint Executable, Translatable UML (xtuml) Application Models in xtuml: Platform-independent Executable Capture subject-matter expertise Enable large-scale reuse Integrate with legacy code Early verification before: HW/SW partitioning Processor selection Target language selection RTOS selection Target model compiler is available Model Compilers for xtuml: Application-independent Provide complete code generation Generate optimized code Delivered in source for customization Verify independent of application models Cause and Effect Model Construction Model Debugging Model Compilation my Code switch( m_state ) { case RES_WAIT : if( rsp_fifo._get( rsp ) ) { send_resp( rsp ); } break; Model Execution and Verification BridgePoint 30

31 BridgePoint Flow for System Specification Use functional requirements specification as input Build platform-independent executable models of: Application Test Suite Verify application behavior on host: Application models C Algorithms Legacy SW, commercial middleware, RTOS Buy or build model compiler for target Mark models as hardware and software 31

32 System-Level Engineering ESL Embedded Software Advance Validation Synthesis Simulation With a unique breadth of expertise in the key domains that make up System Level Design and ESL today, Mentor Graphics is well positioned to lead in it s evolution. A strong partnership between design automation solutions, system IP suppliers and design teams defines the direction of next generation systems. 32

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