Deterministic BIST ABSTRACT. II. DBIST Schemes Based On Reseeding of PRPG (LFSR) I. INTRODUCTION

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1 Deterministic BIST Amiri Amir Mohammad Ecole Polytechnique, Montreal, December 2004 ABSTRACT This paper studies some of the various techniques of DBIST. Normal BIST structures use a PRPG (LFSR) to randomly generate patterns that are applied to CUT. Deterministic BIST schemes combines random and deterministic pattern intending to improve FC in scan-based BIST architectures. Deterministic patterns are applied to CUT as to detect the random resistant faults. The deterministic patterns generated by ATPG are either encoded into initial values (seeds) stored externally in memory and re-generated using the same LFSR used for random pattern generation, or can be internally generated by modifying few bits of some of the useless random patterns generated by the LFSR using additional combinational logic blocks (BFF and its extensions) requiring no storage. I. INTRODUCTION A particular test method is characterized by the FC it can achieve. Normal BIST uses a PRPG (LFSR) to randomly generate patterns that are applied to CUT. This method suffers from generation of enormous number of patterns before a certain desired FC is achieved. In many cases random pattern generation cannot achieve the desired FC. On the other hand, deterministic pattern generation becomes more complex and time consuming as size of circuits increase. Deterministic BIST is a mixed mode test that combines random and deterministic pattern generation aiming to improve FC in scan-based BIST architectures. The method starts applying random patterns to circuit under test (CUT) followed by deterministic patterns to detect the random-resistant faults. The random-resistant faults are identified by fault simulation and new deterministic patterns are generated by an external ATPG. [1][2][3][4][6][9]. There are two main ways of applying the ATPG-generated deterministic patterns. They can either be stored in an external memory as n-bit encoded bit-words and applied to CUT when in deterministic mode [1][2][3][6], or can be dynamically mapped onto useless random patterns generated by the PRPG using extra logic, avoiding the area overhead for storage [4][9]. Both methods use the same PRPG already used for random pattern generation to create deterministic patterns. If the MP-LFSR used applies random patterns in parallel, then the size of LFSR needs to be the same as the size of scan register. In such a case, to embed the deterministic part, the LFSR can be broken into two parts namely for random and deterministic patterns generation. The deterministic patterns requires less number of bits in LFSR as it depends on the number of specified bits that can be optimized by techniques of compaction. The optimization in first method of application can be made by reducing the number of encoded words to be stored, hence optimizing the encoding schemes [1][2][3][6]. On the other hand, the second method may be optimized if the required logic block that dynamically calculates the deterministic patterns is implemented with minimum of logic [4][9]. This paper discusses several proposed DBIST schemes that are based on both methods of application described in above. Section II talks about three schemes that are based on reseeding of the LFSR (external storage). Section III explores two DBIST schemes achieved by the logic blocks BFF and SMF that map the deterministic patterns onto random patterns. Section VI will briefly talk about other potential schemes of DBIST not discussed in this paper. Concluding remarks will be made in section V. II. DBIST Schemes Based On Reseeding of PRPG (LFSR) The test patterns in BIST architecture are generated by an LFSR where the feedback connection is governed by the polynomial P (x). A k-bit LFSR with a primitive polynomial P (x) generates 2 k distinct random patterns from its initial value. An LFSR can have more than one primitive polynomial (MP-LFSR). Depending on the current configuration and the initial value, an LFSR with m primitive polynomials can generate m different sequences of the 2 k distinct patterns. Reseeding refers to initializing the LFSR with some initial value such that the generated patterns out of the LFSR following the seed are the desired patterns. In this section, three similar approaches to generate deterministic patterns based on reseeding of the MP-LFSR are introduced. A. General DBIST Scheme: The DBIST scheme in figure 1 stores the seeds into an external memory. The ATPG-generated test cubes (test patterns) are encoded into n-bit words with q bits to identify one out of 2 q different feedback polynomials of degree k that should configure the MP-LFSR, and n-q bits as initial value of the MP-LFSR [1][3][6][4]. Figure 1: General DBIST based on Reseeding of MP-LFSR To generate a test vector, the seed value is loaded into the LFSR while the feedback configuration of the LFSR is made according to the Polynomial identifier. The LFSR feeds the m-bit scan register that applies the generated patterns to the CUT. Initialized with a seed, the Multiple Polynomial LFSR generates output sequences that are serially shifted into scan register [1][2]. The m-bit pattern loaded in the m-bit scan register is consistent with the encoded test cube. That is, both the test cube and the test pattern in scan register have the same value in corresponding bit locations. For instance, an encoded test cube C = xx00xxx1x0 and the output of the MP-LFSR ( ) corresponding to C s seed after m-clocks are consistent [1][3].

2 Encoding Of Test Cubes: The seeds stored in memory could be of the same size as the test patterns or less. Size of the seeds depends on the maximum number of care-bits (bits that are specified or fixed to 0 or 1 ) in the test cube C. To encode a deterministic pattern with specified bits (care-bits) and don t-care bits into an n-bit word, only the specified bits are considered [1][2][6]. The seeds are encoded such that by initializing the MP- LFSR, the output bit a i is consistent with the test pattern bit c i. An m-bit test cube is encoded into an n-bit word in the following manner: Consider a k-bit MP-LFSR and an m-bit test cube C. let S(C) and s(c) denote the set of indexes of the specified bits and the number of specified bits in C, respectively. For instance for C = x1xx0xx11x, S(C) = {1,2,5,8} and s(c) = 4. The output sequence of the LFSR can be completely determined by the feedback polynomial and the initial seed value. The output sequence of LFSR is consistent with the test cube C iff c i = a i = (a(0).m i ) 1 = (a(0).m i-k+1 ) k (1) holds for all i elements of S(C). M in (1) is the companion matrix corresponding to the feedback polynomial of LFSR with coefficients p 0 -p k-1 given by The subscript k in (1) indicates the k th position in the set of seed variables a(0). Equations (1) provide a system of s(c) nonlinear equations in terms of seed variables a 0,,a k-1 and polynomial coefficients p 0,,p k-1. Hence, two different approaches can be used to reduce the number of variables: fixing the coefficients (i.e. fixing the polynomial) and then calculating the seed variables (reseeding) or fixing the seed variables and finding the polynomial. Option 1 results in linear equations of variables a 0,,a k-1 whereas the equations obtained using the second option are still non-linear p 0,,p k-1. If, in option 1, a chosen polynomial of a MP-LFSR does not have any solution in terms of seed variable, the next polynomial is chosen. The fact that the computational effort required for reseeding is considerably less than that of calculating the polynomial makes option 1 a suitable technique. The following example shows the encoding process [1][3]. Example: Given P (x) = x4 + x3 + 1; C = x 1xx 0xx 11x and hence S(C) = {1,2,5,8} and s(c) = 4. The coefficients are: p 0 = 1 p 1 = 0 p 2 = 0 p 3 = 1. For each index i element of S(C), we calculate a(0)m i according to the following table: Table 1: Mi values calculated for each index i k (M i-k+1 ) k c i a(0) k 1 1 M 1 1 a0 2 2 M 2 1 a1 5 3 M a2 8 4 M a3 With coefficients in above, M 3 and M 5 for k = 4 are found as: Applying equation (1) the seed variables are calculated as: Therefore, a 10-bit test cube was encoded into 4-bit seed. The 4- bit test cubes concatenated with q-bit id for 2 q polynomials are stored in memory. Another way to solve the system of linear equations is to write linear equations in the form of a i = a i-k p 0 + a i-k+1 p a i-1 p k-1 for (i k). Solving these equations for the seed variables gives the seed values [2]. Reducing the number of bits n of the overall encoded test cubes (seed + id) saves area. Researchers have come up with variations of reseeding BIST as to minimize the storage required for encoded test cubes. Some of these proposals are briefly studied in the following section. B. Implicit Encoding (Re-ordering of test cubes): This scheme takes advantage of the reordering of the test cubes such that they can be generated periodically with no polynomial identification bits. If each polynomial of the MP-LFSR generates a group of test cubes, then these test cubes can be encoded and grouped such that the LFSR generates periodic sequence of outputs corresponding to periodic sequence of polynomials. This way there is no need to explicitly identifying a polynomial for a particular test cube saving the bits normally used to identify one out of many feedback polynomials [1]. The schematic for this scheme is shown in figure 2. Figure 2: Implicit Encoding DBIST with a mod-p counter A modulo-p counter can synchronize this periodic operation where p is the period of the sequence of polynomials (i.e. p feedback polynomials). Due to uneven partitioning of the test cubes generated by each polynomial, dummy random patterns should be encoded to balance the arrangement, which results in increased test application time. Under this scheme for N test cubes, the storage required for storing seeds in this case would be (s max )*(N + m) bits where m is the number of added dummy patterns. The computational effort increases as each test cube is analyzed against every polynomial of the MP-LFSR for pattern assignment to polynomials. If two polynomials generate some common patterns, these patterns need to be split to fit the periodic operation. For instance, P 1 (X) generates p1, p2, p3 and 2

3 P 2 (x) generates p2, p3, p4, p5. The common patterns need to be split in two such that the periodicity of the overall operation is maintained. This requires analysis of each pattern against polynomials P1 and P2. As an example of periodic operation, consider a set of test cubes T = {C 1, C 2, C 3, C 4 } and a set of applicable feedback polynomial P(C) for each test cube in T such that P (C 1 ) = {p 1, p 4 }, P (C 2 ) = P (C 3 ) = {p 1, p 2, p 3, p 4 } and P (C 4 ) = {p 2, p 3 } where P (C i ) contains all the polynomials that can generate C i. From above, we see that only 2 polynomials can generate all four test cubes. That is p 1 can generate C 1, C 2 and p 2 can generate C 3, C 4. Then to generate sequence C 1, C 2, C 3, C 4, the sequence of polynomials (p 1, p 1, p 2, p 2 ) is needed. Reordering this sequence we get (p 1, p 2, p 1, p 2 ) with minimum period of 2. This period cannot be reduced further as P (C 1 ) and P (C 4 ) are disjoint [1]. The issue in re-ordering process is to achieve a re-ordering of the polynomials such that all the test cubes are covered, and so by having a sequence of polynomials with minimum period. In other words, attaching to each polynomial of MP-LFSR a list of test cubes that can be generated by this polynomial. The list of test cubes should be a small irreducible lists. The longer the list of test cubes to polynomial, the longer the period. One algorithm to reduce the lists of test cubes for polynomials is by repetitively reducing the largest list by removing the test cube C for a polynomial Pi such that C can also be generated by the largest number of polynomials in the set of polynomials P [1]. TestCube Compaction techniques: Reducing the number of test cubes in a test set improves the time of test application and the efficiency of the encoding. The compaction of test cubes are done in two steps simplification and merging respectively. Simplification refers to removing test cubes that are subsets of other test cubes in a test set. A test cube p1 is contained in another test cube p2 if p1 is subset of p2 and p2 contains all the specified bit values of p1. For instance, if p1 = xx1xx0x and p2 = 0x1xx01, then p1 can be dropped from the list as it is contained in p2. Therefore, using simplification the number of test cubes in the set of test is reduced. Merging of two or more test cubes into one is done by means of consistency. A group of test cubes in the test set T can be merged together if they are consistent and the number of specified bits in the resulting test cube does not exceed the currently maximum number of specified bits in test set. That is if s max (C i ) is the maximum number of specified bits in all the test cubes in a test set T, all the test cubes in set T has number of specified bits less or equal to s max (C i ). This maximum number defines the size of the MP- LFSR. While merging a set of two or more consistent test cubes, the number of resulting specified bits in the resulting set should not exceed s max (C i ) as it will require an LFSR of larger size than the original needed. If merging a set of consistent test cubes results in s(ci)>s max (C i ), partitioning technique can be used to merge smaller groups of consistent test patterns, respecting the boundary for maximum number specified bits allowed [1]. The following example shows how several testcubes are compacted into one. Example: Let T = {C1, C2, C3, C4. C5, C6} such that C1 = x1xx0x11xx, C2 = xxx10xx1xx, C3 = 0x1xxxx0xx, C4 = xxx00xxxxx, C5 = xx1xxxx0xx, C6 = x101x1xxx0. To compact the set T, first we use simplification. Therefore, C5 can be dropped as it is contained in C3. Next, the s max is computed to be 5. Therefore, no merging is allowed such that s(resulting pattern) > 5. C1, C2 and C6 are consistent and candidate for merging. However, w = merg(c1, C2, C6) results is s(w) = 7 > 5. Therefore, we need to check partitions or combinations of merg(c1, C2), merg(c2, C6), merg(c1, C6). Only w1 = merg(c1, C2) results in s(w1) = 5 s max. Similarly, w2 = merg(c3, C4) results in s(w2) = 5 s max. Therefore the resulting compacted or reduced set is T = {w1, w2, C6} = { x1x10x11xx, 0x100xx0xx, x101x1xxx0 } [1]. Similar to merging, concatenating two or more test cubes such that s(ci) s max is met, can be used to compact or reduce the number of test cubes as to get less encoding. Using concatenation, a test set T can be decomposed into subsets T i s composed of two or more test cubes elements of T concatenated such that the resulting number of care bits does not exceed the maximum number care-bits in original set T [2]. Therefore, only 3 encoding needed as opposed to 4. C. Implicit Encoding (Reordering Of Testcubes + next-bit) Another improved scheme in terms of area of storage can be obtained based on multiple seeds per polynomial and seed grouping. Only a single bit (next-bit) can be used to switch between polynomials. Using this scheme the maximum storage required for storing seeds is (s max + 1) x N for N test cubes which is less than (s max + q) x N as for the original case. This method can be implemented by adding a q-bit counter for 2 q polynomials that switches states by a single bit corresponding to seeds of a particular polynomial [6]. The number of seeds per polynomials does not have to be balanced, as the case in section B, and no addition of dummy patterns are required. Figure 3: Implicit Encoding DBIST with a next-bit III. DBIST Scheme Using Internal Patterns A. Bit Flipping BIST (BFF): BFF is a mixed-mode BIST that takes advantage of the useless random patterns to generate deterministic patterns needed to increase FC to the desired level. BFF maps the deterministic patterns generated by an ATPG for random resistant faults onto redundant patterns generated by the LFSR as to cover the undetected faults [4]. Shown in figure 4, BFF function is a block of combinational logic driven by contents of the LFSR at specific states of LFSR. 3

4 Figure 4: BFF DBIST Schematic The output of the BFF block is combined with the current bit out of LFSR through an XOR gate and the resulting bit is flipped. There are chances that the humming distance between some random patterns and the deterministic patterns are small enough to achieve efficient mapping. The mapping process involves selecting candidate random and deterministic patterns, and finding an optimized BFF function with minimum hardware overhead to map the selected deterministic pattern onto the selected random pattern. Candidate patterns are chosen such that the associated cost is minimum. The cost is evaluated based on humming distance between the two patterns and the resulting number of minterms in the BFF block [4]. A candidate random pattern P ran is composed of two sets of bits namely on-set and off-set. On-set consists of set of bits in P ran that are modifiable, whereas off-set refers to set of bits in P ran that are consistent with the corresponding deterministic pattern, and therefore need to be fixed. An n-bit LFSR with primitive polynomial P(x) cycles through 2 n 1 different states. Each state of the LFSR corresponds to a particular bit of random pattern in the scan register. Hence, P ran is a function of many LFSR states. Modifying a random pattern implies modifying some states of the LFSR. When the LFSR reaches state s i where b 0 has to be modified, the BFF function is activated and b 0 is flipped by the XOR operation implied by the output of the BFF. Thus, on-set can be expressed in terms of states of LFSR where the BFF has to be activated to modify the bit being fed into scan register [4]. The BFF function is constructed iteratively in R iterations beginning with BFF 0 and ending with BFF R. In each iteration r such for 0 r R new deterministic patterns are contained in BFF while old deterministic patterns from previous iterations are preserved. Similarly, at each iteration r, some additional faults are covered and the new hard-to-detect sets of faults (candidates for next iteration) are identified. The process continues until the desired FC is reached and the final BFF R is determined. The final BFF function covers all the faults. It should be noted that modifying certain states of LFSR might also randomly change some other random patterns that neither were candidates for mapping, nor fixed in previous iterations. This may end up detecting some of the previously undetected faults without any hardware overhead. However, sometimes some of these incidentally created patterns are to be reverted. Including another XOR gate at the end can do the reversing of such patterns to their original pattern [4][6]. From the flow chart in figure 5 we see that a particular iteration for finding a BFF function consists of many operations. Fix 0 contains the states of LFSR whose random patterns detect some faults. This process can best be described by a simple example. Figure 5: BFF iteration flow chart Example [4]: Given 3-bit LFSR, 5-bit Scan-Register, set if faults F = {f1, f2, f3, f4, f5}, Test Length 5, and a primitive P (x) such that the states figure 6.a are generated. a) b) Figure 5: States of P(x) and the random patterns for test length of 5. Assuming f1, f2, f3 are detected by patterns 11xxx, and 0xx1x, the candidate random patterns from the list in figure 5.b covering these faults are P2 and P3. Therefore, we transform P2, P3 into P 1 and P 2 such that P 1 = 11xxx and P 2 = 0xx1x. Before going through the iterations, we need to fix states at which these patterns are generated as to preserve these patterns. Therefore, Fix 1 = {s5, s6} and Fix 2 = {s3, s6} and therefore: FIX 0 = {s3, s5, s6}. Now going through iterations, we fix BFF 0 = Ø and FIX 0 = {s3, s5, s6}. Assume that using fault simulation, faults f4 and f5 can be detected if we can generate a deterministic pattern with specified bits such: P d = 11 x 01. Hence, we need to map P d onto a random pattern P r to be chosen from list of random patterns such that the fixed patterns are not affected. The on-set and offset for all the patterns with respect to deterministic pattern P d = 11 x 01 are shown below: Figure 6: The on-set and off-set for all the patterns The candidates for mapping P d in the list are P1, P2, and P4. Note that P3 and P5 cannot be mapped as their on-set contain states that are common with FIX 0. The choice for P1, P2 and P4 is based on the cost (number of minterms) that each will introduce to BFF, and the minimum humming distance between P ri and P d. P1 has the minimum humming distance (i.e. only one bit to be changed, to become Pd). Also, P1 introduces only one 4

5 minterm in the BFF 1. Choosing P1 as the eligible candidate, we proceed to find BFF. New BFF = Union {BFF 0, on-set (P d, P 1 )} = { s0 } New FIX = FIX 1 = Union {FIX 0, on-set (P d, P 1 ), off-set (P d, P 1 )} = {s0, s1, s3, s4, s5, s6} Finally we need to minimize the BFF function to be assigned to an XOR gate. To do so, we minimize the logic without using the fixed bits in the process. That is, we cannot consider other 1 s in corresponding to the Fix set in the K-map to minimize BFF further as they were fixed in previous iteration. The k-map minimization and resulting logic is shown in figure 7. SMF is different from BFF in the sense that the SMF block is function of the state variables of LFSR, the bit counter, and the pattern counter as opposed to LFSR states only as in the case of BBF. The advantages over BFF are the reduced area (reduced LFSR and smaller SMF logic block) and more degree of freedom in the synthesis process. Similar to BFF, the SMF function is found iteratively going through a sequence of operations (synthesis process) before a final SMF covering all the faults or reaching the maximum FC can be found. The fix-set, on-set, offset and the SMF function are all functions of LFSR states, bit counter bits, and pattern counter bits [6]. The following example taken from [6] further clarifies the SMF method. Example: Given a 2-bit LFSR with P (x) such that the patterns in below generated for a test length of m = 6, scan register of length n = 5 bits, and suppose the deterministic patterns P d1 = and P d2 = need to be generated. The state sequences and corresponding patterns are shown in table 3. Table 3: State Sequence for SMF scheme a) k-map minimization b) Logic block Figure 7: BFF logic found Having mapped P d onto P 1, the LFSR will generate the following patterns: Table 2: Patterns with BFF The new set of patterns includes the fixed bits and the deterministic pattern as well as the incidentally modified random pattern Also, note that the new pattern set, is different from the old one. Hence, it is seen that BFF BIST can be used to achieve full coverage. The area is reduced, as the size of LFSR is significantly reduced and no external memory for storing test cubes are needed. B. Improved BFF BIST (SMF): Sequence Modifying Function (SMF) scheme is an extension of the BFF. It is meant to improve the area overhead in BFF. SMF uses the idea of autocorrelation between the random patterns [6]. Similar to BFF, the deterministic pattern maps onto a random pattern chosen based on minimum humming distance between the two and the minimum cost in terms of minterms in SMF. Looking at the set of random patterns in above, we see that a minimum of two bits for each deterministic pattern needs to be modified. However, as P d1 and P d2 are similar to each other, only two product terms can be obtained. P d1 mapped onto P 1 because they have a minimum humming distance. Therefore: On 1 (P d1, P 1 ) = { , } Off 1 (P d1, P 1 ) = { , , } After logic minimization similar to BFF, we find SMF 1 = {xx0 xxx x1}. SMF 1 covers all terms of On 1 (P d1, P 1 ) but none of Off 1 (P d1, P 1 ). The fix-set is found as: Fix 1 = Union { On 1 (Pd1, P1), Off 1 (P d1, P 1 ) }. Fix 1 contains states that are to be protected from being modified. The specified bits in each state variable have to be minimum to allow further mapping for next iterations. This minimization is done through iterative fault simulation. To map, P d2, which is similar to P d1, a repeated version of P 1 can be chosen. First lets see the effects of mapping P d1 on state sequences. Table 4: State Sequence corresponding to SMF 1 Figure 8: SMF BIST structure For similar patterns that are all a variation of a specific initial pattern called master pattern P m in few bit positions, the LFSR can be shortened to produce the master pattern repetitively and then the required bit modification can take place. Such patterns are mostly used in cluster testing for logic gates [6]. For instance the sequence of patterns with P m = 1111 may look like: 1111, 0111, 1011, 1101, and The states in bold in table 4, are the affected state variables with SMF1. The pattern bits corresponding to these states are flipped. The bits in blue under the pattern column are the bits that have been flipped (modified from their original value coming out of LFSR). For P d2, the repeated version of P 1, which is P 4, is chosen, as only one bit has to be flipped. Looking at the original 5

6 state sequence list, at least two-bit flipping was needed for P d2. However, after SMF1 p1 is as which requires only 1-bit modification to map P d2 = Therefore, we find On 2 (P d2,p 1 ) = { }, Off 2 (P d2,p 1 ) = { , , , } and FIX 2 = Union { Fix1, Off 2 (P d2, P 1 ), On 2 (P d2, P 1 ) }. After similar logic minimization such that all terms of On 2 (P d2, P 1 ) is covered but none of Fix 1 and Off 2 (P d2, P 1 ), the SMF function is found as: SMF 2 = {xx0 xxx x1, xx0 xx1 xx} = b 0. (p 0 + t 0 ) Figure 9: SMF logic found Table 5: State Sequence corresponding to SMF 2 Those bits in green are the bits that are modified as a result of SMF 2. Table 6: Patterns with SMF 1 and SMF 2 The resulting changes on random patterns are seen in table 6. The bits in blue were affected by SMF1 and those in green were affected by SMF2. Experiment results on benchmark circuits with different scan register lengths show that internal generation methods are implemented with less area compared to Reseeding methods while achieving high FC [4][9]. C. SMF with Multiple Scan: An improvement of the single scan register SMF can be obtained by breaking on long scan register into multiple ones. This helps reduce time of test application due to less clock cycles needed to test the reduced number of flipflops in the scan-path [10]. The synthesis process for SMF with multiple scan follows the same steps as SMF, except at logic minimization. A pattern out of LFSR feeds multiple scan-registers. A deterministic pattern can be mapped onto a random pattern corresponding to a particular scan-register. Therefore, each scan register has its own FIX-, On-, and Off-set. To implement the logic, pathidentification words concatenated to each state variable as to distinguish between the scan paths, and hence the individual FIX-, On-, and Off-set from each scan register can be combined together into FIX*-, On*-, and Off*- sets and the SMF becomes SMF* which contains elements of On-*set. Figure 10: SMF with Multiple Scan The logic minimization is performed on SMF*. For instance: SMF* = {11x.x0xx} indicates that the second scan register should not have a flipped bit in state 11x of LFSR, because that bit in scan register 2 has probably been fixed in earlier iterations [10]. The reader is encouraged to seek further info in [10]. Another variation of DBIST scheme includes the features of DBIST explained in this paper with the features of test point insertion (TPI) where random and deterministic testability of the system is improved [8]. IV. Conclusion In this paper, various methods of implementing deterministic BIST scheme that is aimed to improve testability of the circuits were studied. Section II discussed three methods of implementing a DBIST scheme based on reseeding of the PRPG. All three methods achieve high FC with different area overheads. The DBIST schemes based on pattern mapping using internal logic blocks (BFF and SMF) were studied in section III. BFF and SMF methods improves hardware overhead in comparison with reseeding methods as no storage of encoded patterns are required. Other variations of DBIST implementation, not discussed in details in this paper, include schemes such as SMF with multiple and full scan designs, and SMF with TPI. All mixed mode DBIST schemes intend to improve FC while keeping the area overhead and time of test application at minimum. REFERENCES [1] Venkataraman, S.; Rajski, J.; Hellebrand, S.; Tarnick,S.; An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback ShiftRegisters ; Computer-Aided Design, ICCAD-93. Digest of Technical Papers., 1993 IEEE/ACM International Conference on, 7-11 Nov. 1993; Pages: [2] Hellebrand, S.; Reeb, B.; Tarnick, S.; Wunderlich,H.-J.; Pattern generation for a deterministic BIST scheme ; Computer-Aided Design, ICCAD-95. Digest of Technical Papers., 1995 IEEE/ACM International Conference on, 5-9 Nov. 1995; Pages: [3] Hellebrand, S.; Tarnick, S.; Rajski, J.; Courtois, B.; Generation Of Vector Pattterns Through Reseeding Of Muetiple-Polynomial Linear Feedback Shift Register ; Test Conference, Proceedings., International, Sept ; Pages:120. [4] Wunderlich, H.-J.; Kiefer, G.; Bit-Flipping BIST ; Computer- Aided Design, ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on, Nov ; Pages: [5] Kiefer, G.; Vranken, H.; Marinissen, E.J.; Wunderlich, H.-J.; Application of deterministic logic BIST on industrial circuits ; Test Conference, Proceedings. International, 3-5 Oct ; Pages: [6] Hellebrand, S.; Rajski, J.; Tarnick, S.; Venkataraman, S.; Courtois,B.; Built-in test for circuits with scan based on 6

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