SSoCC'01 4/3/01. Specific BIST Architectures. Gert Jervan Embedded Systems Laboratory (ESLAB) Linköping University
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1 Specific BIST Architectures Gert Jervan Embedded Systems Laboratory (ESLAB) Linköping University General Concepts Test-per-scan architectures Multiple scan chains Test-per-clock architectures BIST conclusions Overview Specific BIST Architectures -2- Gert Jervan, LiU/ESLAB 1
2 High Complexity: Bandwidth External Bandwidth max bits of data/time from ATE to IC Bandwidth Gap IntBandwASIC (Capacity*IntFreq) ExtBandwASIC (IO*ExtFreq) 80 Internal Bandwidth max bits of data/time from on-chip test resource to embedded core Y1995 Y1998 Y2001 Source: SIA Roadmap Specific BIST Architectures -3- High Complexity: Bandwidth External Test Data Volume can be extremely high (function of chip complexity) Requires deep tester memory for scan I/O pins Slow test throughput with long scan chains, especially for core-based designs External Test Super Tester Pattern Generation Precision Timing Diagnostics Power Management Test Control Very high pin count Deep memory Slow throughput Memory Logic Specific BIST Architectures -4- Mixed- Signal I/Os & Interconnects Gert Jervan, LiU/ESLAB 2
3 High Complexity: Bandwidth Solution: Dedicated Built-In H/W for embedded test functions Repartition tester into embedded test and external test functions Include low H/W cost and high data volume embedded test External Test Standard Digital Tester Limited Speed/ Accuracy Low Cost-per- Pin Embedded Test (Built-in) Pattern Generation Result Compression Precision Timing Diagnostics Power Management Test Control Support for Board-level Test System-Level Test Memory Logic Mixed- Signal I/Os & Interconnects Chip, Board or System Source: LogicVision Specific BIST Architectures -5- Built-in Self-Test (BIST) BIST Control Unit Test Pattern Generation (TPG) Circuitry Under Test CUT Test Response Analysis (TRA) TPG & TRA are usually implemented as linear feedback shift registers (LFSR) 3 widespread schemes: test-per-scan multiple scan paths test-per-clock Specific BIST Architectures -6- Gert Jervan, LiU/ESLAB 3
4 Test-per-scan scheme CT Pattern Counter Circuit under test CUT Bit Counter Source Sink TEND BCU TPG Scan path TRA Specific BIST Architectures -7- Multiple scan paths Test pattern generator BIST Control Test response analysator Scan Path Scan Path Scan Path CUT Specific BIST Architectures -8- Gert Jervan, LiU/ESLAB 4
5 Advantages of test-per-scan Fits easily into any commercial design flow which supports scan design The BIST hardware is kept apart from the mission logic, low impact on system performance BIST control is simple Can be extended to multiple scan paths and partial scan Hardware overhead is smaller than in test-per-clock scheme Specific BIST Architectures -9- Disadvantages of test-per-scan Serial pattern generation causes long test times There are many faults and defects which require a two-pattern test and are not detected by a scan test (delay faults) The function of the CUT may not be tested at system speed Specific BIST Architectures -10- Gert Jervan, LiU/ESLAB 5
6 Test-per-clock ho h1 hn Xo X1 Xn LFSR CUT LFSR Specific BIST Architectures -11- Test-per-clock Using special registers, working in four modes System mode (D-type ) Pattern generation mode Response evaluation mode Shift mode Several proposals: BILBO, CSTP, Specific BIST Architectures -12- Gert Jervan, LiU/ESLAB 6
7 Advantages of test-per-clock Short test times: a new test pattern is generated in each clock cycle High speed test can be implemented at the system frequency without any clock delays for shifting Two pattern tests may be generated by appropriate test registers Specific BIST Architectures -13- Disadvantages of test-per-clock The test registers are larger than a scan path combined with a serial pattern generator Integrating test registers into the data path has a stronger impact on system performance than integrating a scan path In most cases the BIST controller of a testper-clock scheme is more complex than the BIST control of a test-per-scan scheme Specific BIST Architectures -14- Gert Jervan, LiU/ESLAB 7
8 First approaches A Centralized and Separate Board-Level BIST Architecture (CSBL) Built-In Evaluation and Self-Test (BEST) No Scan for testing a sequential circuit! Specific BIST Architectures -15- Random-Test Socket P R P G PIs Sin S R S G CUT POs Sout S I S A M I S R Distributed and separate test hardware (not a true BIST) No boundary scan Scan path (LSSD) CUT architecture BIST Controller Specific BIST Architectures -16- Gert Jervan, LiU/ESLAB 8
9 LSSD On-Chip Self-Test (LOCT) POs On-chip monitor (OCM) SISR Sink Source SRSG Boundary scan register Circuit under test CUT Boundary scan register Centralized and separate BIST architecture Boundary scan Scan path (LSSD) CUT architecture On-chip BIST controller PIs Specific BIST Architectures -17- STUMPS Self-Testing Using MISR and parallel SRSG (STUMPS) Centralized and separate BIST architecture Multiple scan paths (STUMPS channels) No boundary scan Mentor Graphics Specific BIST Architectures -18- Gert Jervan, LiU/ESLAB 9
10 STUMPS Scan paths are driven in parallel by a PRPG Signature is generated in parallel from each scan path using a MISR Significant reduction in test time Specific BIST Architectures -19- Mentor Graphics Specific BIST Architectures -20- Gert Jervan, LiU/ESLAB 10
11 Mentor Graphics Specific BIST Architectures -21- Close your books! You have seen: Distributed and separate BIST architecture Centralized and separate BIST architecture (with BS and without) How should look like Centralized and embedded BIST architecture with boundary scan?? Distributed and embedded BIST architecture with boundary scan?? Specific BIST Architectures -22- Gert Jervan, LiU/ESLAB 11
12 Pseudo-random pattern resistance 100% Target FC On previous approaches some form of LFSR was used Generated vectors are therefore pseudorandom and have linear dependencies Reduced uniquenes in case of scan How to cover pseudorandom resistant faults? Specific BIST Architectures -23- Pseudo-random pattern resistance Fault Coverage Time Possible solution: Combining pseudorandom test with deterministic test Multiple seed Bit flipping Hybrid BIST OR To use different (non LFSR based) approach Specific BIST Architectures -24- Gert Jervan, LiU/ESLAB 12
13 Non-LFSR based architecture Simultaneous Self-Test (SST) Distributed and embedded with scan No BS, no LFSR s Each storage cell in the CUT is modified to be a self-test storage cell Has 3 op modes (normal, scan, test) Problems with testing external logic and characterizing the quality of process Specific BIST Architectures -25- F F F F CSTP Circular Self-Test Path (CSTP) F F Combinational Network F F Self-test cell design Register based Partial self-test Only 2 modes (system and test) Low overhead, no controller Low FC Specific BIST Architectures -26- Gert Jervan, LiU/ESLAB 13
14 BILBO BILBO - Built-In Logic-Block Observation TPG and SA combined into a single device 4 modes: normal, TPG, SA, shift mode Can deal with partitioned version of the CUT CUT 2 BILBO 1 CUT 1 BILBO 2 Sin Sout Specific BIST Architectures -27- BILBO TPG SAR Combinational Network Specific BIST Architectures -28- Gert Jervan, LiU/ESLAB 14
15 Test scheduling Related Issues Minimizing test time Minimizing the control effort Control in case of distributed and embedded BIST architecture Partial BIST Specific BIST Architectures -29- Conclusions: Why BIST? Reduces DFT cycle time Without BIST Design time Test-program prep time With BIST Reduces program runtime Reduces ATE memory requirements Enables at-speed test Specific BIST Architectures -30- Gert Jervan, LiU/ESLAB 15
16 BIST v External ATE Resons for BIST Portable, therefore reusable throughout life life cycle cycle of of the the product Reduces cost cost of of external ATE ATE Simplifies test-program development At-speed test test possible Solves SoC SoC test test problems (access, IP IP protection Source of of burn-in test test Remote diagnostics possible Extendible to to mixed-signal/analog Resons for external ATE External ATE ATE can can do do more more testing BIST increases real real estate BIST may may impact performance MIST requires extra extra pins pins BIST has has no no re-use value BIST increases design time time BIST may may increase yield yield loss loss Specific BIST Architectures -31- BIST: conclusions Major motivating factors At-speed test Limited access (embedded cores, embedded memory) IP protection Device-level BIST Memory BIST accepted LBIST becomes more accepted Board-level BIST Solutions available, require Major players LogicVision (logicbist, membist, membist-xt) Mentor Graphics (MBISTarchitect, LBISTarchitect) Specific BIST Architectures -32- Gert Jervan, LiU/ESLAB 16
17 Thank YOU for your attention Gert Jervan Embedded Systems Laboratory (ESLAB) Linköping University Gert Jervan, LiU/ESLAB 17
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