Design for Testability

Transcription

1 Design for Testability Sungho Kang Yonsei University

2 Outline Introduction Testability Measure Design for Testability Ad-Hoc Testable Design Conclusion 2

3 Merging Design and Test Design and Test become closer 3

4 Design and Test Design process 4

5 Testability Measures Testability Inherent property of the circuit based on the circuit topology Probability that a fault is detected by a random vector Function of controllability and observability Controllability Ability to establish a specific signal value at each node in the circuit by setting values on the circuit inputs Observability Ability to determine the signal value at any node in a circuit by controlling primary inputs and observing its outputs Objective Estimate testability Provide guidance for redesign Provide guidance in search process of test generation Measures should be computationally simple 5

6 What Designers Want to Know Will this device require an inordinate amount of time, level of effort, and/or test length in order to provide acceptable testing? Require general information about design What are the problem areas in the design where a modification can ease the testing problem? Require detailed information Testability measures might be useful Detailed information may be useful to the above question 6

7 SCOAP Sandia Controllability and Observability Analysis Program Compute relative complexity to control and observe Combinational Node Primary input or a combinational standard cell output node Sequential Node Output node of a sequential standard cell 7

8 SCOAP 6 Numbers for Each Node, N CC0(N): combinational 0-controllability minimum # of combinational nodes to set node N to 0 CC1(N): combinational 1-controllability minimum # of combinational nodes to set node N to 1 SC0(N): sequential 0-controllability minimum # of sequential nodes to justify 0 to node N SC1(N): sequential 1-controllability minimum # of sequential nodes to justify 1 to node N CO(N): combinational observability # of combinational nodes between N and PO and minimum # of combinational nodes to propagate a signal value on N to PO SO(N): sequential observability # of sequential nodes between N and PO and minimum # of sequential nodes to propagate a signal value on N to PO 8

9 SCOAP Initial Values for PIs and POs PI PO CC0(X) 1 CC1(X) 1 SC0(X) 0 SC1(X) 0 CO(X) 0 SO(X) 0 Buffers and Inverters Buffers Inverters CC0(Y) CC0(X)+1 CC1(X)+1 CC1(Y) CC1(X)+1 CC0(X)+1 SC0(Y) SC0(X) SC1(X) SC1(Y) SC1(X) SC0(X) CO(X) CO(Y)+1 CO(Y)+1 SO(X) SO(Y) SO(Y) 9

10 SCOAP Y = AND (X1, X2) CC0(Y) = min[cc0(x1), CC0(X2)] + 1 CC1(Y) = CC1(X1) + CC1(X2) + 1 SC0(Y) = min[sc0(x1), SC0(X2)] SC1(Y) = SC1(X1) + SC1(X2) CO(X1) = CO(Y) + CC1(X2) + 1 SO(X1) = SO(Y) + SC1(X2) 10

11 SCOAP Fanout CC1(Y) = CC1(X) CC1(Z) = CC1(X) CO(X) = min [CO(Y), CO(Z)] 11

12 SCOAP Example CC0(A) = CC1(A) = CC0(B) = CC1(B) = CC0(C) = CC1(C) = 1 CC0(D) = min [CC0(A), CC0(B)] + 1 = 2 CC1(D) = CC1(A) + CC1(B) + 1 = 3 CC0(E) = CC0(D) + CC0(C) + 1 = 4 CC1(E) = min [CC1(C), CC1(D)] + 1 = 2 CO(E) = 0 CO(D) = CO(E) + CC0(C) + 1 = 2 CO(C) = CO(E) + CC0(D) + 1 = 3 CO(A) = CO(D) + CC1(B) + 1 = 4 CO(B) = CO(D) + CC1(A) + 1 = 4 12

13 SCOAP Tree Good estimate Problem in reconvergent fanout Optimistic Error Want 3/ Pessimistic Error Want 2/2 13

14 Limitations of Testability Measures All testability measure have similar simplifying assumptions so that all results are estimates Involves the restricted information source (only circuit topology) Faults which are difficult to test cause problems Testability data provide a relatively poor indication of whether or not an individual fault will be detected by a given test 14

15 Design for Testability Difficulty in ATPG Not effective for large sequential circuits Advantages Test generation is easy High quality testing Disadvantages Area overhead Timing overhead 15

16 Classification of DFT Ad-Hoc Design Initialization Adding extra test points Circuit partitioning Structured Design Scan design Scan Path Level Sensitive Scan Design Random Access Scan Boundary Scan Built-in Self Test 16

17 Ad Hoc Techniques Techniques which can be applied to a given product, but are not directed at solving the general problem Cost is lower than that of structured approaches (Scan, BIST, etc.) The job of doing test generation and fault simulation are usually not as simple or as straightforward 17

18 Test Points Employ test points to enhance controllability and observability Large demand on extra I/O pins Example 18

19 Test Points Multiplexing monitor points OP1 0 OP2 1 MUX Z OPN 2 n -1 (N=2^n) 1 2 n X1 X2 Xn 19

20 Test Points Use demultiplexer and latch register to implement control points 1 2 R CP1 CP2 Z DEMUX N CPn 1 2 n X1 X2 Xn n (N=2 ) 20

21 Test Points Time sharing I/O ports normal functional signals observat -ion test points n n M U X S n primary outputs normal primary inputs n D E M U X S n R n normal functiona l inputs Select Select (a) (b) 21

22 Test Points Candidates for control points Control, address, and data bus lines on bus structured designs Enable/hold inputs to microprocessors Enable and read/write inputs to memory devices Clock and preset/clear inputs to memory devices Data select lines to multiplexers and demultiplexers Control lines on tristate devices Candidates for observation points Stem lines associated with signals having lots of fanouts Global feedback paths Redundant signal lines Outputs of logic devices having many inputs Outputs from state devices Address, control, and data buses 22

23 Initialization Design circuits to be easily initializable Initialization Process bringing a sequential circuit into a known state at some known time Circuits requiring some clever initialization sequence should be avoided Flip-flop with explicit clear Use explicit clear to all FFs 23

24 Oscillators and Clocks Disable internal oscillators and clocks during test Example A = 0 and B : Test input 24

25 Partitioning Partitioning shift registers into smaller units X1 X2 C DIN CK DOUT R1 DIN CK R2 DOUT Y1 Y2 CP/data inhibit CP/tester data X1 CP/data inhibit CP/tester data X2 C DIN CK R1 DOUT OP DIN CK R2 DOUT CP/clock inhibit CP/test clock Y1 Y2 25

26 Partitioning Split large counters 26

27 Partitioning B Partitioning large circuits into small subcircuits to reduce test generation cost Example T1=0 T2=0 : Normal Mode T1=0 T2=1 : Test C1 T1=1 T2=0 : Test C2 A m A D C1 F T1 T2 B A' D p q (a) 1 0 s E S M U X C2 G C n C C1 C2 S M U X 1 0 C' E F 0 1 MUX S S 1 0 MUX G F' G' (b) 27

28 Avoid Use of Redundant Logic If a redundant fault occurs, it may invalidate some test for non-redundant faults Such faults cause difficulty in calculating fault coverage Much test generation time can be spent 28

29 Avoid Global Feedback Paths Provide logic to break global feedback paths Asynchronous circuits other than latches should be avoided when possible Avoid combinational feedback loop 29

30 Avoid Gated Clock Make sure EN settles before CLK changes Or redesign the circuit as follows 30

31 Bypass Counters 31

32 Avoid Internal Pulse Generator All internal pulse or clock generators should be isolated during test 32

33 Avoid Cross-coupled NAND/NOR Add logic to make each cross-coupled NAND/ NOR gate behave as a transparent buffer during test 33

34 Avoid Bus Floating Make sure each tristate bus has one pullup register, pulldown register or bus holder 34

35 Avoid Potential Bus Contention Make sure only one tristate gate is selected at a time 35

36 Easily Testable Circuits Aimed at developing design techniques that start with a functional specification and results that are easy to test Properties Small test sets No redundancy Tests can be found without much extra work Tests can be easily generated Faults should be locatable to the desire degree 36