Chapter 5 Combinational ATPG

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1 Chapter 5 Combinationa ATPG

2 2 Outine Introduction to ATPG ATPG for Combinationa Circuits Advanced ATPG Techniques

3 3 Input and Output of an ATPG ATPG (Automatic Test Pattern Generation) Generate a set of vectors for a set of target fauts Netist Faut ist ATPG Program Test vectors Backtrack statistics Aborted fauts Redundant fauts Undetected fauts

Components of An ATPG System if fauts remaining new

if fauts remaining Agorithmic pattern generator (ATPG)

fauts Find a fauts captured by current vectors Generate

4 Components of An ATPG System if fauts remaining new vector generated Random pattern generator Faut simuator if fauts remaining Agorithmic pattern generator (ATPG) Simuation-based test generator To detect easiy detectabe fauts Find a fauts captured by current vectors Generate vectors for undetected fauts or prove them to be undetectabe 4

5 5 Revisiting Faut Coverage Faut efficiency (ATPG efficiency) Percentage of fauts being successfuy processed by a ATPG Proving a faut undetectabe testing the faut Undetectabe fauts can cause performance, power, reiabiity probems, etc. Fauts may be masked by undetectabe fauts. Faut coverage= # of detected fauts Tota # of fauts # of detected fauts Faut efficiency= Tota # of fauts- # of undetectabe fauts

6 Fuy V.S. Partiay Specified Patterns A fuy specified test pattern (every PI is either 0 or ) 0 0 0/ stuck-at 0/ A partiay specified test pattern (certain PI s coud be unknown) x x /0 stuck-at 0 /0 Appications of partiay specified test patterns Test compaction Finding pattern of best test power, deay, etc.

7 7 Test Compaction To reduce the number of test vectors as ong as we keep the same detectabe faut coverage. Test compaction is important for randomy generated patterns. Even for vectors generated by an ATPG, since the order of processing fauts wi decide which vectors are discovered first.

8 An Exampe of Different Vectors Detecting the Same Fauts Assume we know the vectors and their detectabe fauts If we start from f, we find v to detect (f, f3, f5). And then continue with f2. We find v2 to detect it. And for the remaining f4, we find v3 for detection. In tota, we need 3 vectors. f f2 f3 f4 f5 v x x x v2 x x x v3 x x x v4 x x x 8

9 An Exampe of Different Vectors Detecting the Same Fauts (cont.) With the same assumption If we order the fauts as f4, f2, f5, f3, f. For f4, we find v3 to cover (f3, f4, f5) And for f2, we find v2 or v4 to cover (f, f2) In tota, we ony need 2 vectors. f f2 f3 f4 f5 v x x x v2 x x x v3 x x x v4 x x x 9

10 0 Test Compaction Methods Use faut dictionary Find essentia vectors No other vector can test fauts covered ony by essentia vectors. Find minimum vectors to cover a rest fauts A NP-compete probem. Try different orders of input vectors in a faut simuator.

11 Other Test Compaction Methods Static compaction After a set of vectors has been generated Use D-intersection For exampe, t=0x t2=0x t3=0x0 t4=x0 after compaction: t3=00 t24=00 Dynamic compaction Process generated vectors on-the-fy After generate a test for a faut, choose a secondary target faut to be tested and try to test the second faut by don t cares (X) not assigned by the first faut.

12 2 Combinationa ATPG Test Generation (TG) Methods Exhaustive methods Booean Equation Structura Anaysis Impication Graph Miestone Structura ATPG Agorithms D-agorithm [Roth 967] 9-Vaued D-agorithm [Cha 978] PODEM [Goe 98] FAN [Fujiwara 983] Other advanced techniques

13 Exhaustive Test Generation Expore a possibe input combinations to find input patterns detecting fauts Compexity ~ O(n 2 no_pi ) Generate tests for the stuck-at 0 faut, a. a b a stuck-at 0 f c Inputs f fa

14 Booean Equation Method f = ab+ac, fa = ac a Ta = the set of a tests for faut a b = {(a,b,c) f fa=} = {(a,b,c) f*fa +f *fa=} c = {(a,b,c) (ab+ac)(ac)' + (ab+ac)'(ac) = } = {(a,b,c) abc'=} = { (0) }. a stuck-at 0 f The compexity is high with the computation of fauty function.

15 5 Booean Difference Method f fa= == (a=0) (f(a=0) f(a=)) for a stuck-at, or (a=) (f(a=0) f(a=)) for a stuck-at 0 Define Booean difference df/da=f(a=0) f(a=) Meaning any change at a can be observed at the outputs of f().

16 Exampe of Booean Difference with Faut at PIs a b a stuck-at 0 X f= ab + ac c df/da = f(a=0) f(a=) = 0 (b+c) = (b+c) Test-set for a s-a-0 = {(a,b,c) a (b+c)=} = {(x), (x)}. Faut activation requirement Faut sensitization requirement

17 7 Booean Difference for Interna Signas Cacuation Step : convert the function F into a new one G that takes the signa w as an extra primary input Step 2: df(x,, x n )/dw = dg (x,, x n, w)/dw w x x n... w F Free w x x n... x G

18 Exampe of Booean Difference with Interna Faut a b h stuck-at 0 X f= ab + ac c G(i.e., F with h foating ) = h + ac dg/dh = G(h=0) G(h=) = (ac ) = (a +c ) Test-set for h s-a- is { (a,b,c) h (a'+c')= } = { (a,b,c) (a'+b') (a'+c')= } = { (0xx), (x00) }. Test-set for h s-a-0 is {(a,b,c) h (a'+c')=} = {(0)}. For faut activation For faut sensitization 8

19 9 Chain Rue A B f C D G(f(A, B), C, D) {A,B} and {C,D} have no variabes in common f = AB and G = f + CD à dg/df = (C + D ) and df/da = B à dg/da = (dg/df) (df/da) = (C +D ) B An Input vector v sensitizes a faut effect from A to G iff v sensitizes the effect from A to f and from f to G

20 20 Test Generation Based on Structura Anaysis Important agorithms D-agorithm [Roth 967] 9-Vaued D-agorithm [Cha 978] PODEM [Goe 98] FAN [Fujiwara 983] Key techniques Find inputs to () activate, and (2) propagate the faut through sensitized paths to POs Branch and bounds

21 Structura Test Generation ATPG traverse circuit structures by the foowing process: More targets Pattern found? End No Yes Seect targets Make decisions Yes Correct resuts? No Deete previous decisions Which path to propagate faut? Which ine to assign vaue? How to activate faut? How to propagate faut? More decisions If no more decision to be deeted, seect new targets. 2

22 22 Common Concepts for Structura Test Generation Faut activation Set the fauty signa to either 0 or A ine justification probem Faut propagation Seect propagation paths to POs Inputs to the gates on the propagation paths are set to non-controing vaues if the inputs are not on the path. Side inputs are set to non-controing vaues. Mutipe ine justification probems Line justification Find inputs that force certain signas to be 0 or.

23 Exampes of Faut Activation and Propagation for Stuck-at Fauts Faut activated by inverting the signa vaue: d=. Faut propagation Faut propagated to f by e=0. Line justification To assign d=, we need (a b)=( ). To assign e=0, we need c=0. a b d stuck-at 0 X d= for faut activation f c e=0 for faut propagation 23

24 24 What are the Decision Points? On faut propagation We seect propagation paths to POs. Invove decisions on which paths to choose. On ine justification Given a signa to justify, we need to make a decision on which inputs to set. For exampe, to set the output of an OR gate to, we need to choose which input to set to. Backtrack If we make a wrong decision (guess), we return and erase the decision (, and make another one). A decisions are recorded.

25 25 Branch-and-Bound Search Test Generation is a branch-and-bound search Every decision point is a branching point If a set of decisions ead to a confict (or bound), a backtrack is taken to expore other decisions A test is found when () faut effect is propagated to a PO (2) a interna ines are justified Since the search is exhaustive, it wi find a test if one exists No test is found after a possibe decisions are tried Target faut is undetectabe

26 26 An Iustration of Branch and Bounds Assume a, b, and c are interna signas a 0 0 b 0 c Soution space with a=0, b=0 Soution space with a=0, b=, c=0 Soution space with a=0, b=, c= Soution space with a=

27 Decision on Faut Propagation Path d a b c G G5 f G6 f2 e G3 G4 Decision tree before we start: Faut activation G5 G5 or G6 G6 G=0 à {a=, b=, c=} à G3=0 Faut propagation through G5 or G6 Decision through G5: à d= à The resuting test is (X) Decision through G6: à G4= à e=0 à The resuting test is (x0) 27

28 Decisions On Line Justification a b c d e f h k Faut activationà set h to 0 Faut propagation à e=, f=à o=0 Faut propagation à q=, r= To justify q= à = or k= Decision: = à c=, d= à m=0, n=0 à r=0 à inconsistency at r à backtrack! Decision: k= à a=, b= p m n o To justify r= à m= or n= (àc=0 or d=0) à Done! q r Decision point s n= k= a=, b= r= q= backtrack m= = c=, d= à m=0, n=0 à r=0 c=0 (Success) 28

29 29 Impications Impications Computation of the vaues that can be uniquey determined Loca impication: propagation of vaues from one ine to its immediate successors or predecessors Goba impication: the propagation invoving a arger area of the circuit and re-convergent fanout Maximum Impication Principe Perform as many impications as possibe It heps to either reduce the number of probems that need decisions or to reach an inconsistency sooner

30 30 An Exampe of Impication to Infuence Decisions d a b c G2 G G5 f G6 f2 G3 G4 e Faut activation G=0 à {a=, b=, c=} à {G3=0, G2=0} à G5=0 Faut propagation through G6 ony Decision through G6: à G4= à e=0 à test pattern is (x0)

31 3 Miestone Structura Test Generation Methods D-agorithm [Roth 967] 9-Vaued D-agorithm [Cha 978] PODEM [Goe 98] FAN [Fujiwara 983] Other advanced techniques

32 The D-Agebra Aow the representation of the good and fauty behavior at the same time. Formay define/generate decision points in faut activation and propagation Introduce the symbo D in addition to 0,, x D = /0 (D º 0/) represents a signa which has vaue in faut-free circuit and 0 in the fauty circuit. D D D D D D D D D D D D D D D D D 0 0 D D Forward impication conditions for NOT, AND, OR in D-agebra 32

33 33 A Quick Overview of D- Agorithm A structura agorithm Use 5-vaue ogic (0,, X, D, D ) Try to activate and propagate faut to outputs first with interna justification. Then appy branch and bounds on ine justification probems.

34 34 Faut Activation Specify the minima input conditions which must be appied to a ogic eement to produce an error signa at its output. Stuck-at fauts at an AND output: Stuck-at-0 faut: D Stuck-at- faut: 0xD and x0d More compex faut mode, e.g., bridging fauts, gate type errors, can aso be modeed.

35 35 Faut Activation of Compex Faut Modes Appy the concept of Booean equation method List the set of input patterns for function F. F is the (oca) representation function of the faut site. () faut-free output=0 {F=0} (2) faut-free output= {F=} (3) fauty output=0 {F f =0} (4) fauty output= {F f =} {F=0} {F f =} or {F=} {F f =0} Exampe: 2-input AND gate output stuck-at {F=0}={00, 0, 0}, {F f =}={00, 0, 0, }, {F=}={}, {F f =0}={} {F=0} {F f =} = {00, 0, 0} {F=} {F f =0} = {}

36 36 Exampe of Compex Faut Modes Assume the faut is to change an AND gate to an OR gate {F=0}={00, 0, 0}, {F f =}={0, 0, }, {F=}={}, {F f =0}={00} {F=0} {F f =} = {0, 0} {F=} {F f =0} = {} Appy 0, we produce a 0/ (D ) at the output Appy 0, we aso produce a (D ) 0/.

37 37 D-frontiers and J-fontiers Two most important data structures in the D- agorithm. Both store a ist of gates. D-frontiers Where to choose the propagation paths. D-frontiers shoud not be empty during the search of test patterns. J-frontiers Where to perform ine justifications. J-frontiers wi be empty after a test pattern is found.

38 38 D-frontiers D-frontiers are the gates whose output vaue is X, whie one or more inputs are D or D. d a b c G D G5 X f G6 X f2 e G3 G4 Faut activation G=0 à { a=, b=, c= } à { G3=0 } Faut propagation can be done through either G5 or G6 D-frontiers={G5, G6}

39 J-frontiers J-frontier: is the set of gates whose output vaue is known (i.e., 0 or ), but is not impied by its input vaues. a b c d e f h Faut activationà set h to 0 Faut propagation à e=, f=à o=0 Faut propagation à q=, r= k p m n o We need to justify both q= and r=: J-frontiers={q, r}. q r s 39

40 40 D-drive Function The D-drive seects a gate in the D-frontier and attempts to propagate the D and/or D from its input(s) to its output by setting side-inputs to non-controing vaues. D D X To drive D to the output, we need to set the side-input to. D For more compex functions, we can use the truth tabe of 5-vaue ogics.

41 4 Impication in D-Agorithm Invove D and D in the impication. Basic principes are guided by the truth tabe of each ogic gate (compex ce). Exampes are given in the foowing pages.

42 42 Loca Impications considering D/D (Forward) Before After 0 x x 0 x 0 x 0 x a J-frontier={...,a } 0 0 a J-frontier={... } D' D x D-frontier={...,a } a D' D 0 D-frontier={... } a

43 43 Loca Impications considering D/D (Backward) Before After x x x x x J-frontier={... } a 0 x x a 0 J-frontier={...,a } x x

44 44 Backward oca Impication by Prime Cubes Prime Cubes A simpified form of truth tabe. Circe groups of 0 or in the Karnaugh map. a b f Prime cubes of AND b a a b f 0 x 0 x 0 0

45 45 Backward Impication for Compex Ces Find the prime cubes of the function f(a,b,c) = a c + b b 0 a 0 0 c a b c f 0 x 0 x x 0 x 0 x 0 0 In this exampe, if we want to justify f=0 and we know c=, then we aso obtain the backward impication of ab=x0

46 46 Checking Consistency Consistency check for 5-V ogic We might assign different requirements from different decisions. We have to make sure every signa have compatibe assignment in the circuit. 0 X D D 0 0 f 0 F F f F F X 0 X D D D F F D D F D F F D F D

47 47 Terminating Conditions for D- Agorithm Success: () Faut effect at an output (D-frontier may not be empty) (2) J-frontier is empty Faiure: () D-frontier is empty and faut is not at POs (2) No decision eft but J-frontier is not empty

48 Propagation Phase of the D- Agorithm Choose signas to activate faut No D-frontier eft Perform impication, and check consistency (D-drive) Seect a D-frontier and Propagate the faut Backtrack (remove impied signas) no Backtrack Consistent? (remove impied signas) Fai no yes Is there a D or D at PO? yes Line justification (next page) 48

49 Line Justification Phase Test generated no Any un-justified ine? J-frontier not empty yes Seect an un-justified ine, and choose inputs for the gate (record decisions) No aternative decisions Perform impication, and check consistency update J-frontier No decision eft, but J-frontier not empty Line justification faied Backtrack (remove ast decisions and impied signas recover J-frontiers) Consistent? no yes 49

50 50 D-Agorithm Exampe I2 I I4 I3 0 G G2 G3 0 sa D 0 G4 G5 G6 G7 D G9 D Faut activationà set G2 to 0 à I2=, I3=, D-Frontier={G5, G6}, J- Frontier={} Faut propagation à seect G5 à I=à G=0 à G4=, D-Frontier={G6, G9}, J-Frontier={} Faut propagation à seect G9 à G6=, G7=à I4=0, G3=0 à I4= (Contradictory) à propagation fais, backtrack to seect another D- frontier from {G6}.

51 5 D-Agorithm Exampe (Cont.) I2 G4 G 0 I G5 D sa G2 G9 D G6 D I4 G3 0 G7 I3 Faut propagation à seect G6 à I4=, G3=0, G7= D

52 9-Vaue D-Agorithm Logic vaues (faut-free / fauty) {0/0, 0/, 0/u, /0, /, /u, u/0, u/, u/u}, where 0/u={0,D'}, /u={d,}, u/0={0,d}, u/={d',}, u/u={0,,d,d'}. Advantage: Automaticay considers mutipe-path sensitization, thus reducing the amount of search in D-agorithm The speed-up is NOT very significant in practice because most fauts are detected through singe-path sensitization

53 Exampe: 9-Vaue D-Agorithm a b c 0/u 0/ u/ u/ g D d /u e u/ f u/ d' 0/u e' u/0 f' u/0 h i j u/ k u/ u/ m u/ D /u à / n D Faut activationà set a to 0/u à h=/u, D- Frontier={g} Faut propagationà seect g à b=u/, c=u/ àd-frontier={i, k, m} Faut propagationà seect i à d=/u à D- frontier={k, m, n} Faut propagationà seect n à h=; j, k,, m=u/ àj-frontier={j, k,, m} Justify j à e =u/0 à e=u/ (consistent) Simiary f=u/

54 54 Seecting Inputs for 9-Vaue D- Agorithm To derive the input test vector, we choose the vaues consistent with both faut-free and fauty circuits. A = (0/u)={0, D } à 0 B = (/u)={, D} à C = (/u)={, D} à D = (u/)={, D } à E = (u/)={, D } à F = (u/)={, D } à The fina vector (A,B,C,D,E,F) = (0,,,,, )

55 55 Probems with the D-Agorithm Assignment of vaues is aowed for interna signas Large search space Backtracking coud occur at each gate TG is done through indirect signa assignment for FA, FP, and LJ, that eventuay maps into assignments at PI s The decision points are at interna ines The worst-case number of backtracks is exponentia in terms of the number of decision points (e.g., at east 2 k for k decision nodes) D-agorithm wi continue even when D-frontier is empty Inefficient for arge circuits and some specia casses of circuits Exampe: ECAT (error-correction-and-transation) circuits.

56 56 ECAT Circuits A B H sa0 P C E F G J K L N M Q R Primitive D-cube: A = B =, H = D To propagate through P to output R One possibe choice is N = Q =, but this is impossibe. D-agorithm wi exhaustivey enumerate a interna signas to confirm that N = Q = is impossibe.

57 57 The Decision Tree A B H sa0 P C E F G J K L N M Q R J=,K=0 C=,E= Q = L=,M= F=,G=0 N = J=0,K= L=0,M=0 C=0,E=0 F=0,G= Justification impossibe

58 58 PODEM: Path-Oriented DEcision Making The test generation is done through a sequence of direct assignments at PI s Decision points are at PIs, thus the number of backtracking might be fewer Aso a structura agorithm Aso use 5-vaue ogic and D-frontiers. Aso a branch and bounds agorithm. In PODEM, to activate and propagate fauts, a series of objective ine justifications are seected (simiar to D- agorithm), but then each objective is backtraced to PIs and a forward simuation is used to perform impications and confirm consistency.

59 59 Search Space of PODEM Compete Search Space A binary tree with 2 n eaf nodes, where n is the number of PI s For exampe, {a, b, c, d} are PIs in the foowing binary tree a 0 b 0 b 0 0 c c 0 0 c 0 c d d d d d d d d F F F S F S F F

60 PODEM: Recursive Agorithm PODEM () begin If(error at PO) return(success); If(D-Frontier is empty) return(failure); /* terminating conditions*/ (k, v k ) = Objective(); /* choose a ine, k, to be justified */ (j, v j ) = Backtrace(k, v k ); /* choose the PI, j, to be assigned */ Impy (j, v j ); /* make a decision */ If ( PODEM() == SUCCESS ) return (SUCCESS); Impy (j, v j ); /* reverse vj */ If ( PODEM() == SUCCESS ) return(success); Impy (j, x); /* we have wrong objectives */ return (FAILURE); end 60

61 6 An Exampe PI Assignments in PODEM Assume we have four PIs: a, b, c, d. Decision: a=0 Decision: b=0 à fais Reverse decision: b= Decision: c=0 à fais Reverse decision: c= Decision: d=0 à fais Decision: d= à fais Backtrack: d=x Backtrack: c=x Backtrack: b=x Reverse decision: a= a 0 b b 0 Faiure c 0 Faiure d 0 Faiure Faiure

62 62 Objective() and Backtrace() Objective() Guide decisions to activate and propagate fauts. Lead to sets of ine justification probems. A signa-vaue pair (w, v w ) Backtrace() Guide decisions to ine justification. Backtrace maps a objective into a PI assignment that is ikey to contribute to the achievement of the objective Traverses the circuit back from the objective signa to PI s Invoves finding an a-x path from objective site to a PI, i.e., every signa in this path has vaue x A PI signa-vaue pair (j, v j ) No signa vaue is actuay assigned during backtrace!

63 63 Objective() Routine Objective() { /* The target faut is w s-a-v */ } if (the vaue of w is x) obj = (w, v ); ese { seect a gate (G) from the D-frontier; seect an input (j) of G with vaue x; c = controing vaue of G; obj = (j, c ); } return (obj); faut activation faut propagation

64 64 Backtrace() Routine Backtrace(w, v w ) { /* Maps objective into a PI assignment */ G = w; v = v w ; whie (G is a gate output) { /* not reached PI yet */ inv = inversion of G; /* inv= for INV, NAND, NOR*/ seect an input (j) of G with vaue x; G = j; /* new objective node */ v = v inv; /* new objective vaue */ } return (G, v); /* G is a PI */ }

65 65 Backtrace Exampe Objective to achieved: (F, ) a b X X X X X F= Backtrace find a=0; Forward simuate a=0 a b 0 X X F= F is sti x after we set a=0

66 66 Backtrace Exampe (Cont.) Objective to achieved: (F, ) a b 0 X X F= Backtrace find b=; Forward simuate b= a b 0 0 F= F=

67 67 Terminating Conditions Success: Faut effect seen at an output. Faiure: D-frontier is empty and faut is not at any POs.

68 Exampe: PODEM a b c 0 0/ g D d e 0 f X 0 d' e' f' X h i j 0 k X m X D n X Faut activationà set a to 0 à h=, D-Frontier={g} Faut propagationà seect g à b=, c= àdfrontier={i, k, m} Faut propagationà seect i à d= à D-frontier={k, m, n} Faut propagationà seect n à objective =(k, ) Backtraceà e=0 à e = à j=0 Empty D-frontier and faut not at PO Backtrack to e= à e =0 à j=, k=d

69 Exampe: PODEM (Cont.) a b c 0 0/ g D d e f 0 d' e' 0 f' 0 h i j k D m D D n D D-frontier={m, n} Faut propagationà seect n à objective =(m, ) Backtraceà f=0 à f = à =0 Empty D-frontier and faut not at PO Backtrack to f= à f =0 à =, m=d à n=d, success!!

70 70 Another PODEM Exampe: ECAT Faut activationà set H to à A=, B=, D- Frontier={P} A B C E F G H J K L M sa0 N Q P R Faut propagationà seect P à objective =(N, ) Backtraceà C= Backtraceà E= à J=0, L= Backtraceà F= Backtraceà G= à K=0, M= à N=0, Q= à P=D à R=D Note that there is no backtracking in this exampe.

71 7 Characteristics of PODEM A compete agorithm ike D-agorithm Wi find the test pattern if it exists Use of backtrace() and forward simuation No J-frontier, since there are no vaues that require justification No consistency check, as conficts can never occur No backward impication Backtracking is impicity done by simuation rather than by an expicit and time-consuming save/restore process Experimenta resuts show that PODEM is generay faster than the D-agorithm

72 The Seection Strategy in PODEM In Objective() and Backtrace() Seections are done arbitrariy in origina PODEM The agorithm wi be more efficient if certain guidance used in the seection of objectives and backtrace paths Seection Principe Principe : among severa unsoved probems, attack the hardest one Ex: to justify a at an AND-gate output Principe 2: among severa soutions for soving a probem, try the easiest one Ex: to justify a at OR-gate output The key is to quantitativey define hard and easy.

73 Controabiity As Guidance of Backtrace We usuay use controabiity to guide the seection. More detais wi be provided in Ch 6. Testabiity Anaysis. Objective (g, ) à choose path gàf for backtracing Two unsoved probems e= and f= Choose the harder one: f= (ower probabiity of being ). Objective (g, 0) à choose path gàf for backtracing Two possibe soutions: e=0 or f=0 Choose the easier one: f=0 (higher probabiity of being 0). a=/2 b=/2 e=3/4 g Probabiity of being c=/2 d=/2 f=/4

74 74 FAN Fanout-Oriented Test Generation Techniques to acceerate the test generation process Immediate Impications Unique sensitization Headines Mutipe backtrace

75 75 Immediate Impications A B C H K E J sa L PODEM FAN Initia objective L = 0 Initia objective L = 0 Backtrace to PI: B = 0 Set J = K = E = Impication: H =, K =, J = 0, L = J = à H = 0 à A = B = K = à C = 0 Fai à backtrack.

76 76 Unique Sensitization A B 0 G G2 D G3 D G4 D H C D E F Ony one path to propagate D on signa C to output H. Set a the off-path inputs to non-controing vaues. G =, E =, F =, A = à B = 0 PODEM Initia objective: set G to Backtrace to PI: A = 0 à assigning A = 0 wi ater bock the propagation of D

77 Head ines Output of fanout-free regions with PIs as inputs. Backtrace in FAN stop at headines. Reduce search space. Head ines bound ines A ine that is reachabe from at east one stem is said to be bound 77

78 78 Breadth-First Mutipe Backtrace A must be set to. 0 Both must be set to. 0 0 Set to 0 the input w/ easiest-to-contro to 0 input. PODEM s depth-first search is sometimes inefficient. Breadth-first mutipe backtrace identifies possibe signa conficts earier. Attempts to satisfy a set of objectives simutaneousy

79 79 Why Mutipe Backtrace? Drawback of Singe Backtrace A PI assignment satisfying one objective àmay precude achieving another one, and this eads to backtracking Mutipe Backtrace Starts from a set of objectives (Current_objectives) Maps these mutipe objectives into head-ine assignments that is ikey to Contribute to the set of objectives Or show that objectives cannot be simutaneousy achieved Mutipe objectives may have conficting requirements at a stem 0 0

80 Exampe: Mutipe Backtrace conficting stem A B A A2 0 E Consistent stem C E E2 G 0 H I= J=0 Current_objectives Processed entry Stem_objectives Head_objectives (I,), (J,0) (J,0), (G,0) (G,0), (H,) (H,), (A,), (E,) (A,), (E,), (E2,), (C,) (E,), (E2,), (C,) (E2,), (C,) (C,) Empty à restart from (E,) (E,) (A2,0) empty (I,) (J,0) (G,0) (H,) (A,) (E,) (E2,) (C,) (E,) (A2,0) A A,E A,E A,E A A A A C C C C C 80

81 8 Mutipe Backtrace Agorithm Mbacktrace (Current_objectives) { whie (Current_objectives f ) { remove one entry (k, v k ) from Current_objectives; switch (type of entry) {. HEAD_LINE: add (k, v k ) to Head_objectives; 2. FANOUT_BRANCH: j = stem(k); increment no. of requests at j for v k ; /* count 0s and s */ add j to Stem_objectives; 3. OTHERS: inv = inversion of k; c = controing vaue of k; seect an input (j) of k with vaue x; if ((v k inv) == c) add(j, c) to Current_objectives; ese { for every input (j) of k with vaue x add(j, c ) to Current_objectives; } } } (to next page)

82 82 Mutipe Backtrace (con t) } if(stem_objectives f ) { remove the highest-eve stem (k) from Stem_Objectives; v k = most requested vaue of k; if (k has contradictory requirements and k is not reachabe from target fauts) return (k, v k ) /* recursive ca here */ add (k, v k ) to Current_objectives; return (Mbacktrace(Current_objectives); } ese { remove one objective (k, v k ) from Head_objectives; return (k, v k ); }

83 83 FAN Agorithm FAN() // the target faut is f s.a.v begin if (f = x) then assign (f, v ) if Impy_and_check() = FAILURE then return FAILURE if (error at PO and a bound ines are justified) then begin justify a unjustified head ines return SUCCESS end if (error not at PO and D_frontier = Ø) then return FAILURE /* initiaize objectives */ add every unjustified bound ine to Current_objectives seect one gate (G) from the D-frontier c = controing vaue of G (to next page)

84 84 FAN agorithm (con t) for every input (j) of G with vaue x add (j,c ) to Current_objectives /* mutipe backtrace */ (i,v i ) = Mbacktrace(Current_objectives) Assign(i,v i ) if FAN() = SUCCESS then return SUCCESS Assign(i,v i ) /* reverse decision */ if FAN() = SUCCESS then return SUCCESS Assign(i,x) return FAILURE end

85 85 Advanced Concepts of ATPG Dominator ATPG Learning agorithms State hashing Satisfiabiity-based methods and Impication graphs

86 86 Dominators for Faut Propagation Before After unique D-drive anaysis X D X X X X D X X D X X Unique D-Drive Impication If every gates in D-frontier pass through a dominator (unique D-drive), we can set noncontroing vaues at other side-inputs, and propagate D/D further.

87 87 Learning Methods for ATPG Learning process systematicay sets a signas to 0 and and discover what other signa vaues are impied. Used extensivey in impication. Ex. a=àb=0, even a and b are not impied immediatey by gate reationship. Static earning Start the earning process before ATPG Dynamic earning Start the earning process in between ATPG steps when some signa vaues are known Costy process

88 Modus Toens for Learning Given PàQ is true We can derive ~Qà~P is true Exampe: P and Q are Booean statements ~Q means that Q is not true A D A D B F B 0 F C E C E (B=0) à (F=0) => ~(F=0) à ~(B=0) => (F=) à(b=) (Static Learning) When A= (B=) à (F=) => (F=0) à (B=0) (Dynamic Learning) 88

89 Constructive Diemma for Learning Given () P=>Q and R=>S, and (2) Either P or R is true Exampe: We can derive Either Q or S is true. Both [(a=0) => (i=0)] and [(a=) => (i=0)] are true. Either (a=0) or (a=) hods => (i=0) a=0 a= i=0 0 i=0 89

90 90 Modus Ponens for Learning Given F and F=>G are true We can derive G is true. Exampe: [a=0] and [(a=0) => (f=0)] => (f=0)

91 9 Recursive Learning From known signa vaues, try a possibe decisions (recursivey). If a certain signas have the same vaues among a decisions, they are impied vaues.

92 Exampe of Recursive Learning c d a b e f h g i=0 e2 f2 g2 k j= i=0 For i, try g=0 àe=0, f=0 e=0 For e, try a=0 àa2=0, e2=0 For i, try h=0 à=0 àk= f=0 For e, try b=0 àb2=0, e2=0 For f, try c=0 àc2=0, f2=0 For f, try d=0 àd2=0, f2=0 e2=0 f2=0 g2=0 à=0 àk= 92

93 93 State Hashing (EST) Records and compare E-frontiers E-frontiers are the cut between known signas and unknown parts. Given identica E-frontiers Previous impications can be used Or inconsistency can be deduced from the previous run.

94 State Hashing Exampe C= E=0 F=0 g B=0 h k A= m n Z C=0 E=0 F g B= h k A m n Z Step Input Choice E-frontier B=0 {B=D } 2 C= {C=, B=D } 3 E=0 {g=, m=d} 4 A= {g=, n=d } 5 F=0 {Z=D} Step Input Choice E-frontier C=0 {h=d } 2 B= {m=d} 3 E=0 {g=, m=d} Match found at step 3 Process for detecting B s-a- Test pattern = (CEFBA)=(000) Process for detecting h s-a- Test pattern = (CEFBA)=(000) 94

95 95 Impication Graph ATPG Transate circuits into impication graphs Use transitive cosure graph agorithm to perform ATPG Some decisions and impications are better assigned with graph agorithms. But experiences show that circuit structure is a very important information for ATPG. Satisfiabiity-based agorithms are currenty the fastest impementation for justification and commony appied to verification probems. We have a separate set of sides about SAT.

96 96 Transating Gate to its Equivaent Impication Graph Use NAND as an exampe A two-input NAND can be described competey by the foowing 3 equations. a àc b àc c àab Note that they cover a cubes. Impication graph Each node represents a signa variabe. If there is a directed edge from one node (v) to another (v2), v impy v2. a b c a c b a c b Equivaent impication graph for NAND.

97 Perform Impication on the Graph Assume we have c=0, we add an edge for càc càc == c +c == c Extra impication are found by tracing inked nodes. In this exampe, a àa and b àb, hence a=, b=. a b à a b a b c c 0 0 Truth tabe for impication aàb ==a +b 97

98 Impication Graph Exampes a b d F a b F a b F c e d e c d e c Equivaent Circuit Impication Graph a b F a b F a b F a b F d e c d e c d e c d e c Impication Graph d=0 New paths: a -d-d -a, F -d-d -F, b -d-d -b New conditions: a àa, F àf, b àb Impied ogic vaues: a=, F=, b= Impication Graph F= (i.e., de=0) New paths: b -d-e -b, b -e-d -b New conditions: b àb Impied ogic vaues: b= 98

Lecture outline Graphics and Interaction Scan Converting Polygons and Lines. Inside or outside a polygon? Scan conversion.

Lecture outline Graphics and Interaction Scan Converting Polygons and Lines. Inside or outside a polygon? Scan conversion. Lecture outine 433-324 Graphics and Interaction Scan Converting Poygons and Lines Department of Computer Science and Software Engineering The Introduction Scan conversion Scan-ine agorithm Edge coherence