Practical Statistical Static Timing Analysis with Current Source Models

Transcription

1 Prcticl Sttisticl Sttic Timing Anlysis with Current Source Models Debjit Sinh, ldimir Zolotov, Sheshshyee K. ghunthn 2, Michel H. Wood, Kerim Klfl IBM Systems, Poughkeepsie, USA IBM Thoms J. Wtson eserch, Yorktown Heights, USA IBM Systems, Bnglore, Indi 2 {dsinh, zolotov, woodm, klfl}@us.ibm.com; shesh.rghunthn@in.ibm.com 26 IBM Corportion

2 Driver nd Signl Modeling Dely/Slew/Ceff driver model is too inccurte Current Source Model (CSM) hs better ccurcy Einstimer uses efficient implementtion bsed on dynmic effective cpcitnce P Feldmnn, S Abbspour, D Sinh, et l., Driver wveform computtion for timing nlysis with multiple voltge threshold driver models, DAC 28 Wveforms model is necessry compnion Better ccurcy but higher computtionl cost nd memory footprint Y Eqv Einstimer implements sttisticl timing Delys, slews, ATs, ATs, etc. re modeled with liner or biliner forms Cross-terms model interction of sources of vritions like dependence of vribility on dd t Liner terms Cross-terms t t 2 t n t = t + t + t X t + t, X + L + t, Efficient sttisticl model of wveform is needed 2

3 Sttisticl wveform models Time points re modeled with sttisticl cnonicl form H.Ftemi, S.Nzrin, nd M.Pedrm, Sttisticl logic cell dely nlysis using current-bsed model, DAC26 High memory consumption nd redundncy Time moments re highly correlted Sttisticl wveform model pproximtes vribility with timing shift nd scle Nominl wveform nom (t) defines shpe Cnonicl form of shift cts s sttisticl dely D = d + s + d X d Cnonicl form of scle cts s sttisticl slew S = s + s + s X s. Zolotov, J. Xiong, C. isweswrih, S. Abbspour, D. Hthwy, Compct modeling of vritionl wveforms, ICCAD 27 computes sensitivities by solving CSM differentil equtions, which is rther inefficient. Efficient technique for computing nd propgting sttisticl wveform is needed Support incrementl timing ( t S[ t t D ) t) = nom ] ( Shift D t = t + t + t X t Shift t Scle Scle S t t t 3

4 Sttisticl wveform propgtion ( Prtil CSM ) Sttisticl AT & slew t gte input Compute ATs nd slews for bse corners S = s + s s Solve CSM for ll bse corners to get wveforms t gte output A Compute nd store nominl wveform, sttisticl AT nd slew nom (t) s + s s Construct corner wveforms t interconnect input by shift nd scle to mtch corner ATs nd slews B Construct interconnect models (OMs) for ll bse corners S = s + s s Propgte wveforms for ll bse corners through interconnect Sttisticl AT & slew t next gte input Compute nd store sttisticl AT nd slew 4

5 Study of sttisticl timing models 4 methods of sttisticl timing: No CSM NLDM insted of CSM Full CSM - wveforms for ll bse corners Bse corners wveform re needed for incrementl timing Prtil CSM nominl wveform with sttisticl shift&scle Wveforms t other corners re constructed by mtching delys nd slews of conventionl sttisticl timing mp CSM no wveforms stored Gte is modeled with CSM to get dely & slew Liner rmp is propgted through interconnect A A B D Four 4nm test circuits PO Y 5fF Y PO XO 5fF DFF Q PO 5fF CK 8 PT corners; FF dd =./.6 T= 85C FF dd =./.6 T= -C SS dd =./.6 T= 85C SS dd =./.6 T= -C equired for PT cross-term A Chin of buffers Y A Y 5fF esistive wire: ~3- ff Ctotl, ~2-4 ff Ceff,.3- kohm resistnce] OUT 5

6 Aligned corner wveforms XO isible difference between.5 nd.6 wveforms DFF chin 6

7 Bse corner selection Corner P//T Mx error of dely/slew (%) Averge error of dely/slew (%) XO DFF Chin XO DFF Chin FF/./- 4./.6 4.7/4. 8./2.9 2./ / /2..7/ /-.6 FF/./ /.7 3.8/3.8 9./2.6 2./.26-2./ /.7 2.3/. -.84/-.6 SS/./- 2.3/.5 7.5/ /2.6./.6 -.2/ 2.4/.2 4.7/.8 -.4/-.3 SS/./+85 2./.5 9./ /2.4./.5 / 3.6/.8 5./.6 -.4/-.2 FF/.6/+85.3/.4 7.7/.9 7./.7.9/.5 -.2/. 2./ /-.3 -./-.3 FF/.6/-./.6 6.2/2. 6.7/.6.9/.8 -.2/.2.9/-. -.6/-.4 -./-.4 SS/.6/+85.3/.8 6.3/.9 9.9/3..5/.5.65/.5-3./ /-.7.72/.2 SS/.6/-.8/.9 7.5/.9.7/3.2.4/.5.3/.5-4.3/ / / Accurcy highly depends on selection of bse (nominl) corner No corner with best ccurcy for ll circuits both for delys nd slews Selected corner with best trdeoff ccurcy 7

8 Hold slck error histogrm No CSM SSTA slck error Design D9: 7.6K tests 33K gtes Worst slck is reduced by 7ps Prtil CSM SSTA slck error Slck error (ps)

9 Timing ccurcy, run time, memory footprint Design Num gtes Num tests No CSM AT/Slew Error (%) CSM AT/Slew Error (%) Slck Accur Improvment vs No CSM un time vs No CSM Memory vs no CSM D6 7K 2.K.3/2..2/. 6.9% 6% 3.6% D7 23K 3.5K./.9./.2 4.2% 6% 4.6% D8 3K 6.6K 2.3/3.2.5/. 5.4% 4% 4.% D9 33K 7.6K.6/3.2.3/. 7.% 5% 5% D 7K 34.K.9/3.3.3/..4% 5% 2.5% D.63M 96K.6/2.3/. 5.2% 6% 7.5% Typicl No CSM error in AT.3-.9% (worst 8ps), in Slew 2-3% (worst 7ps) Typicl Prtil CSM error in AT.3%, in slew.-.% Up to 7% slck improvement (7ps) for representtive 25ps clock cycle esonble run time overheds 6% Additionl memory -.5GB per M gtes 9

10 Conclusions Studied implementtions of CSM wveforms in sttisticl timing for 4nm high performnce designs Nïve pproch results in mnifold memory overhed Developed method of propgting sttisticl wveforms Sttisticl shift nd scle technique ws modified for better performnce nd lower memory footprint. Achieved substntil slck ccurcy improvement Up to 7ps, i.e. 7 of 25ps cycle time un time increse does not exceed 6% Memory overhed is bout.gb per M gtes Does not exceed 7.5% Further ccurcy improvement cn be chieved Dynmic selection/construction of nominl corner for shift nd scle representtion