Kyoung Hwan Lim and Taewhan Kim Seoul National University
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1 Kyoung Hwan Lim and Taewhan Kim Seoul National University
2 Table of Contents Introduction Motivational Example The Proposed Algorithm Experimental Results Conclusion
3 In synchronous circuit design, all sequential elements in the design are synchronized by a unified signal clock signal Ideally, clock signal should be reached to all sequential elements at the same time for its synchronicity Practical issues Different wire length Different buffer characteristics Achieving zero skew is still difficult!
4 Multi voltage mode design High voltage Low voltage Mode 1 Mode 2 Whenever the power mode is changed, the delay of clock tree is also changed. How can we simultaneously meet the skew constraint for every power mode?
5 Adjustable Delay Buffer (ADB) We can change its delay dynamically Changing delay value depending on the current power mode simple and easy to use Problems How many ADBs should be used? Where should we place ADBs? What delay value should be for each power mode?
6 Related work Y. S. Su, W. K. Hon, C. C. Yang, S. C Chang, and Y. J Chang, Value assignment of adjustable delay buffers for clock skew minimization in multi voltage mode designs, ICCAD, Only work using ADB for clock tree generation in multi voltage mode designs Optimal ADB adjustment value for given ADB positions Finding ADB positions is still based on heuristics Cannot guarantee minimum number of ADBs
7 Table of Contents Introduction Motivational Example The Proposed Algorithm Experimental Results Conclusion
8 B 1 B 2 B 5 B 7 B 3 B 4 A B C D E F G H I J B 6 Mode Violation!!
9 Avoiding violation Reconstruct clock tree which can adaptively minimize all clock skew under constraint for all power modes Almost impossible Using Adjustable Delay Buffer (ADB) Insert ADB instead of normal buffer Change delay of inserted ADBs depending on power mode ADB insertion should be restricted because of high cost of using ADB
10 B 1 B 2 B 5 +7 B 7 B 3 B 4 A B C D E F G H I J B 6 Mode
11 B 1 B 2 B 5 +7 B 7 B 3 B 4 A B C D E F G H I J B 6 Mode
12 B 1 B 2 B 5 B 3 B 4 +1 A B C D E F G H I J B 6 B 7 Mode
13 Where should we place ADBs? How much delay should be adjusted? B 1 B 2 B 5 B 3 B 4 +1 A B C D E F G H I J B 6 B 7 Mode
14 B 1 B 2 B 5 B 3 B 4 A B C D E F G H I J B 6 B 7 Mode Violation!!
15 B 1 B 2 B 5 +6 B 7 B 3 B 4 A B C D E F G H I J B
16 B 1 B 2 B 5 +6 B 7 B 3 B 4 A B C D E F G H I J B Clock skew of current clock tree at Mode 1 = 18 9 = 9
17 B 1 +7 B 2 B 5 B 7 B 3 B 4 A B C D E F G H I J B
18 B 1 +7 B 2 B 5 B 7 B 3 B 4 A B C D E F G H I J B Clock skew of current clock tree at Mode 1 = = 10
19 B 1 B 2 B 5 (+6/+0) B 7 B 3 B 4 A B C D E F G H I J B 6 Mode Violation!!
20 B 1 B 2 B 3 B 4 A B C D E F G H I J B 6 B 5 B 7 (+7/+0) (+1/+1) Mode Violation!!
21 B 1 B 2 B 3 B 4 (+0/+4) A B C D E F G H I J B 6 B 5 B 7 (+7/+4) (+1/+4) Mode No Violation!!
22 Traditional approach can find optimal delay assignment value for given ADB position However, cannot check whether given ADB position is optimal or not They found ADB positions in greedy manner More comprehensive approach is still needed
23 ADB 1 (+5/+3) B 2 B 5 B 7 ADB 3 B 4 (+0/+8) A B C D E F G H I J B 6 Mode
24 Table of Contents Introduction Motivational Example The Proposed Algorithm Experimental Results Conclusion
25 Problem description Given initial buffered clock tree T, power modes, clock signal arrival time, and clock skew bound B Allocate ADBs and replace buffers in T Assign delay increment value to each ADB for every power mode Clock skew bound constraint should be satisfied Minimize the number of ADBs used
26 ADB 1 +2~+8 +7 ADB 2 ADB 3 ADB 4 A B C D E F G H There exists at least one feasible adjustment value LAT v LAT 2
27 ADB 1 Case 1 +7 ADB 2 ADB ADB 4 A B C D E F G H Case 2
28 +2 ADB 1 +7 ADB 2 ADB 3 ADB 4 A B C D E F G H
29 +2 ADB 1 +7 ADB 2 ADB 3 ADB 4 A B C D E F G H
30 +2 ADB 1 +7 ADB 2 ADB 3 ADB 4 A B C D E F G H We cannot meet the constraints using current tree! Case 3
31 Summary of all cases Case 1: EAT1 LATv B and EAT2 < LATv B ADB2 is essential (cannot remove) α 2 = LAT v LAT 2 Case 2: EAT1 LATv B and EAT2 LATv B ADB2 is useless (remove) Case 3: EAT1 < LATv B Cannot satisfy constraint B Relax the constraints or reconstruct clock tree
32 The flow of algorithm
33 B 1 B 2 B 5 B 7 B 3 B 4 A B C D E F G H I J B 6 Mode
34 ADB 1 ADB 2 ADB 5 ADB 7 ADB 3 ADB 4 ADB 6 A B C D E F G H I J Mode We can remove ADB 6 (Case 2 for all power modes)
35 ADB 1 ADB 2 ADB 5 ADB 7 ADB 3 ADB 4 A B C D E F G H I J B 6 Mode
36 ADB 1 ADB 2 ADB ADB 7 5 ADB 3 ADB 4 (+0/+8) A B C D E F I J Mode We have to retain ADB 3 (Case 1 at power mode 2)
37 ADB 1 ADB 2 ADB ADB 7 5 ADB 3 ADB 4 (+0/+8) A B C D E F I J Mode We have to retain ADB 3 (Case 1 at power mode 2) We can remove ADB 4 (Case 2 for all power modes)
38 ADB 1 ADB 2 ADB 5 ADB 7 A B E F I J Mode We can remove ADB 5 and ADB 7 (Case 2 for all power modes)
39 ADB 1 ADB 2 ADB 5 ADB 7 A B E F I J Mode We can remove ADB 5 and ADB 7 (Case 2 for all power modes)
40 ADB 2 ADB 1 (+5/+3) A B E F Mode We have to retain ADB 1 (Case 1 at power mode 1 and 2)
41 ADB 2 ADB 1 (+5/+3) A B E F Mode We have to retain ADB 1 (Case 1 at power mode 1 and 2) We can remove ADB 2 (Case 2 for all power modes)
42 ADB 1 (+5/+3) B 2 B 5 B 7 ADB 3 B 4 (+0/+8) A B C D E F G H I J B 6 Mode
43 Table of Contents Introduction Motivational Example The Proposed Algorithm Experimental Results Conclusion
44 Experiment setup System with eight 2.5GHz Intel Xeon CPU and 8GB memory 45nm Nangate Open Cell library Input clock tree is generated by using Synopsys IC compiler Three ISCAS 95 benchmarks and three ITC 99 benchmarks partitioned into 6~10 power subdomains which can operates in two voltage levels 0.95V and 1.1V Assumed that each ADB can be adjusted with a granularity of 10ps
45 Benchmarks #FFs #Bufs Worst Skew (ps) s s s Skew Bound B #ADBs [1] #ADBs (CLK- ADB) Red. of #ADB 30 ps % 40 ps % 50 ps % 30 ps % 40 ps % 50 ps % 30 ps % 40 ps % 50 ps % [1] Y. S. Su, W. K. Hon, C. C. Yang, S. C Chang, and Y. J Chang, Value assignment of adjustable delay buffers for clock skew minimization in multi voltage mode designs, ICCAD, 2009
46 Benchmarks #FFs #Bufs Worst Skew (ps) b b b Skew Bound B #ADBs [1] #ADBs (CLK- ADB) Red. of #ADB 30 ps % 40 ps % 50 ps % 30 ps % 40 ps % 50 ps % 30 ps % 40 ps % 50 ps % [1] Y. S. Su, W. K. Hon, C. C. Yang, S. C Chang, and Y. J Chang, Value assignment of adjustable delay buffers for clock skew minimization in multi voltage mode designs, ICCAD, 2009
47 Conclusion This work provides: Optimal algorithm to solve problem of clock skew optimization using ADBs under multi voltage design. Finding a solution with minimum number of ADB allocation while satisfying the clock skew constraint for every power mode. 9.27% further decreased number of ADBs compared to the existing algorithm.
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