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Transcription

1 0;L$+LJK3HUIRUPDQFH ;3URFHVVRU:LWK,QWHJUDWHG'*UDSKLFV Rajeev Jayavant Cyrix Corporation A National Semiconductor Company 8/18/98 1

2 0;L$UFKLWHFWXUDO)HDWXUHV ¾ Next-generation Cayenne Core Dual-issue pipelined FP and MMX TM Optimized instructions for 3D graphics 64 KB unified L1 cache ¾ Integrated graphics subsystem Accelerated 2D/3D operations MPEG2 motion compensation for DVD ¾ Tightly coupled SDRAM interface Very low latency Up to 16 simultaneously open banks 2

3 0;L6\VWHP6ROXWLRQ Memory Frame Buffer Boomer 64 MXi Cache FPU/MMX CX5540 AC97 3 x ports Integer Core 2D/3D Graphics Engine PCI 0+] Fast-PCI RTC SIO Audio Video-In Port KBC ACPI USB IDE PCI LPC/ISA CX5546/47 Scale & Merge MPEGII/DVD ACPI RAMDAC Gamma Correction FET control for power planes Wake up Power Switch LED control Fan Control PCI slots PCI slots PCI slots ISA slots CRT 3

4 0;L3URFHVVRU%ORFN'LDJUDP Cache Unit Integer Unit FPU/MMX Unit MMU Cayenne Core MXi Bus Controller Write Post Queue GART Lookaside Buffer Memory Control Unit Graphics to Memory AGP Compliant Memory Subsystem MXi Bus Graphics Unit Host I/F 64 2D/3D/DVD/VGA PCI Bridge Display Controller PCI Bus Video Companion 4 SDRAM Port

5 %DVLF'3LSHOLQH model coordinates Transform and Lighting screen coordinates Triangle Setup initial params & slopes Rasterization pixels ¾ Cayenne Core handles transform and lighting Floating point intensive ¾ Graphics Unit offloads remainder of pipeline Highly parallel computations Data intensive ¾ Workload split frees CPU bandwidth for application use 5

6 ')3([WHQVLRQV ¾ Two single-precision floating point results per operation ¾ Dual-issue, including floating multiply and add Up to 4x throughput on the inner loops of matrix multiplies and vector dot products ¾ Reciprocal and 1/sqrt operations Perspective projection for transform Vector normalization for lighting calculations Significantly faster than division ¾ Fully pipelined 6

7 0;L*UDSKLFV6XEV\VWHP Rasterizer MXi Bus Host I/F Setup Engine Arbiter Memory Interface SDRAM VGA Display Controller GART Lookaside Buffer Graphics Port Video Port 7

8 *UDSKLFV6HWXS(QJLQH ¾ Microcoded architecture for flexibility Permits optimization for changing APIs Handles 2D and DVD operations in addition to 3D triangle setup Pipelined multiply-accumulate 2KB I-Cache, 2KB Scratchpad RAM ¾ Specialized DMA engine Performs float-to-fixed conversion on incoming data Handles vertex sorting ¾ Maximizes concurrency with x86 core 64 entry command FIFO Direct execution of display lists in memory 8

9 *UDSKLFV5DVWHUL]HU ¾ Triangles, vectors, planar trapezoids ¾ High performance perspective-correct texture mapping 4KB, 4-way set associative texture cache; pipelined Single cycle bilinear, dual-cycle trilinear filtering Level Of Detail per-pixel MIP mapping Dual textures with flexible blending options Many texture formats, including palletized and YUV ¾ 8, 16, and 32-bit Z buffer ¾ Fog table support / simultaneous alpha & fog ¾ Also handles 2D and DVD operations 9

10 5DVWHUL]HU3LSHOLQH From Setup Engine Edge Walk Z Buffer Pixel Blender Texture Mapping 2D Pipeline Z Interpolator A,R,G,B Interpolators U,V,Q Interpolators 8x8 Pattern Z Read Data Lighting, Multitexture Blend Perspective Correct Source Data Z Compare Alpha Test Address Generation Mono Expansion Alpha Blend Texture Cache Format, Writeback Format, Dither Format, Filter Raster Operation 10

11 03(*'9'3OD\EDFN ¾ Consumer quality DVD playback based on Mediamatics TM MVCCA TM architecture ¾ Cayenne Core handles MPEG stream parsing, Huffman decode, and inverse DCT ¾ Graphics Unit handles motion compensation ¾ Display Controller supports planar YUV 420 surfaces ¾ Graphics Companion provides YUV to RGB conversion, scaling, and DVD subpicture support 11

12 0RWLRQ&RPSHQVDWLRQ Past Frame Current Frame being decoded Future Frame Macroblock being decoded Forward vector Backward vector Each 8x8 macroblock in the decoded frame can reference past and future frames, plus an error term The Setup Engine parses motion vectors for an entire frame at a time 12

13 *UDSKLFV3HUIRUPDQFH ¾ Maximize concurrency to deliver sustained frame rates CPU can queue large numbers of display lists Setup Engine can queue 4-5 primitives for rasterizer ¾ Graphics Setup Engine Operates at 1x, 2x, 3x, 4x SDRAM clock Triangle setup is clocks (~1M tri/sec) ¾ Rasterizer Operates at SDRAM clock 3D operations at one pixel per clock for single texture, one pixel per two clocks for dual texture 133 Mpix/sec 3D, ~1 GB/sec 2D peak fill rate 13

14 0;L6WDWLVWLFV&XUUHQW6WDWXV ¾ ~10M transistors ¾ Die size ~100 mm2 (National s own.18 um, 5 layer metal process) ¾ 320 PGA package ¾ Power: 15W typical ¾ Working silicon is in the lab ¾ Production 2Q99, General Samples 1Q99 14