Floating Point CORDIC Based Power Operation

Transcription

1 Floating Point CORDIC Baed Power Operation Kazumi Malhan, Padmaja AVL Electrical and Computer Engineering Department School of Engineering and Computer Science Oakland Univerity, Rocheter, MI Abtract Thi project preent an architecture to calculate floating point power operation baed on hyperbolic cordic. The coding i performed in parameterized method to upport number of different floating point format. In thi paper, the ytem i implemented for IEEE-754 tandard Single preciion and Double preciion floating point format. The IP i created uing AXI4-Full bu interface for board implementation. SD card interface alo developed to upport reading input from and writing reult to SD card. The paper dicue methodology, implementation, accuracy of hardware, reource uage, and poible improvement. I. INTRODUCTION The goal of thi project i to create power operation digital circuit that i baed on hyperbolic cordic. Since we have ued fixed point for mot of the implementation in cla, floating point format i choen for thi project. The project wa developed inide out, meaning developing the core center piece (extended hyperbolic cordic) firt, then wrapping with top level file of power operation, and o on. The hardware wa created in parameterized fahion to upport different floating point format. Until FIFO interface, all development wa done uing Vivado. After creating power operation IP with AXI4- full interface, development hift to SDK for oftware ide. SD card interface wa developed to pa large number of input combination to IP, which i topic outide of the cla. The motivation behind thi particular project wa to how deep undertanding of deign and implementation of data path, to how the effectivene of parameterized vhdl coding, and to demontrate the powerful combination of oftware and hardware programing. The deign deciion were baed to maximize the uefulne of digital circuit. Thi report explain the deign proce of each component, how the hyperbolic cordic and power algorithm are implemented, experimental etup, analyi of reult and accuracy, reource uage, and poible improvement. II. METHODOLOGY A. Floating Point Number Sytem There are three tandard type in IEEE floating point arithmetic: ingle preciion, double preciion and extended preciion. Single preciion number require a 32-bit word with 8 exponential bit and 23 fractional bit. The +/- refer to the ign of the number, a zero bit being ued to repreent a poitive ign. The repreentation for zero require a pecial zero bit tring for the exponent field a well a a zero bit tring for the fraction, i.e. All the line of Table above except the firt and the lat refer to the normalized number, i.e. all the floating point number which are not pecial in ome way. Note epecially the relationhip between the exponent bit tring aa2a3 a8 and the actual exponent E, i.e. the power of 2 which the bit tring i intended to repreent. We ee that the exponent repreentation doe not ue any of ign-and-modulu, 2' complement or ' complement, but rather omething called biaed repreentation: the bit tring which i tored i imply the binary repreentation of E In thi cae, the number 27 which i added to the deired exponent E i called the exponent bia. For example, the number = (. ) 2 * 2 i tored a Here the exponent bit tring i the binary repreentation for + 27 and the fraction bit tring i the binary repreentation for (the fractional part of.). The range of exponent field bit tring for normalized number i to (the decimal number through 254), repreenting actual exponent from E min = 26 to E max = 27. The mallet normalized number which can be tored i repreented a Meaning (. ) 2 * 2-26, i.e. 2-26, which i approximately.2 * - 38, while the larget normalized number i repreented a Meaning (. )2 * 2 27, i.e. ( ) * 2 27, which i approximately 3.4 * 38. For many application, ingle preciion number are quite adequate. However, double preciion i a commonly ued alternative. In thi cae each floating point number i tored in a 64-bit double word with exponential bit and 52 fractional bit.

2 The idea are all the ame; only the field width and exponent bia are different. Clearly, a number like / with an infinite binary expanion i tored more accurately in double preciion than in ingle, ince b,.., b52 can be tored intead of jut b,.,b23. There i a third IEEE floating point format called extended preciion. Although the tandard doe not require a particular format for thi, the tandard implementation ued on PC' i an 8-bit word, with bit ued for the ign, 5 bit for the exponent and 64 bit for the ignificand. The leading bit of a normalized number i not generally hidden a it i in ingle and double preciion, but i explicitly tored. Otherwie, the format i much the ame a ingle and double preciion. The comparion between ingle preciion and double preciion floating point repreentation i a follow: B. Extended Hyperblic Cordic Hyperbolic cordic i the core of power calculation. The baic hyperbolic cordic ha very limited range of convergence, o negative iteration i implemented to increae the range. The equation and 2 how the hyperbolic cordic algorithm for negative and poitive iteration. To enure the convergence, iteration i = 3k + (4, 3, 4 ) mut to be repeated. For thi paper, negative iteration M = 5, and poitive iteration N = 6 i choen to have reaonable range for power operation. The convergence bound for baic cordic and expended cordic with M = 5 i hown in table. M e x ln(x) Baic [-.82,.82] (, ] 5 [ , ] (, EE ] Table : Convergence bound for the domain x i+ = x i + δ i y i ( 2 i 2 ) i : { y i+ = y i + δ i x i ( 2 i 2 ) () z i+ = z i + δ i θ i, θ = Tanh i ( 2 i 2 ) Delta in the equation i calculated uing following two equation depend on the operation mode (Equation 3). An for thi extended hyperbolic cordic i calculated uing equation 4. With M = 5 and N = 6, An = 5.382* -4. After ufficient number of iteration, hyperbolic cordic converge to certain value (Equation 5, 6). Rotation: δ i = ifz i < ; + otherwie (3) Vectoring: δ i = ifx i y i ; + otherwie A n = ( i= 5 ( 2 i 2 ) 2 )( 6 i= 2 2i ) (4) x n = A n (x cohz + y inhz ) Rotation: { y n = A n (x cohz + y inhz ) z n = x n = A n (x cohz + y inhz ) y Vectoring: { n = z n = z + Tanh i ( y ) x (5) (6) By uing pecial input combination, we are able to obtain exponential operation and natural logarithm. Exponential i calculated uing rotation mode with x = y = /An, z = α, x n = coh α + inh α = e α. Natural logarithm i calculated uing vectoring mode with x = β+, y = β-, z =, z n = tanh - (β-/ β+) = ln(β)/2. Figure : Architecture of extended hyperbolic cordic Negative FSM Cordic FSM Poitive FSM x i+ = x i + δ i y i 2 i i > : { y i+ = y i + δ i x i 2 i z i+ = z i + δ i θ i, θ = Tanh i (2 i ) (2) The cordic deigned for thi project i coded in parameterized fahion to upport any format of floating point. It take total number of bit (N), number of exponent

3 bit (EXP), and number of fractional bit (FR) a a parameter. It i notable that LUT mut contain the precalculated value for tanh that will be ued for operation. Figure how the baic architecture of extended hyperbolic cordic. Top half of the circuit i for negative iteration. The firt multiplexer elect initial input at the beginning, and then take previou output from following iteration. Component hown in red box (adder/ubtractor, hifter) are floating point upported component which Profeor Llamocca ha provided. Other component are ame a if the ytem i deigned for fixed point format. LUT i hard coded inide the ource file. The ytem upport 64, 32, 24, 6 bit floating point number. Appropriate LUT value are elected by uing if (N = XX) generate tatement. The negative finite tate machine (FSM) (figure 2) control the iteration, hift amount, enable ignal, add/ub, and multiplexer elect time. Negative FSM count iteration from -7 to -2 to avoid i-2 operation for different location. After the negative iteration, poitive iteration circuit begin to work. Again, multiplexer i located to elect output from negative iteration for the firt time, then take previou output. Ret of the circuit work imilar to negative iteration. Figure 2: ASM chart of negative FSM S2 E, Ec, clr, _xyz mode E, Ec E, Ec Zi di di S (Rotation Mode) (true) Xi = Zi S4 Reetn = done (Vector Mode) di di The extended hyperbolic cordic i controlled by three eparate FSM. Poitive and negative ASM are how in figure 2 and 3. Both poitive and negative FSM keep track of iteration, and decide the hift amount, ign of add/ub, and enable ignal. The challenge we faced i to develop the method to repeat i = 4 and 3. Thi i achieved by adding code to a counter inide poitive FSM that generate flag during iteration 4 and 3, then implement a regiter to keep track of previou iteration. Alo, we had hard time realizing that poitive iteration tart from, not. The green boxed area in poitive FSM perform thi tak. The cordic FSM i a imple FSM that firt enable negative iteration. When it receive done from negative, FSM tart the poitive. S3 Figure 3: ASM chart of poitive FSM Ec S2 (Rotation Mode) S E, Ec, clr, _xyz mode Reetn = (Vector Mode) E E rt ro Ec Zi di di Ec (true) Xi = Zi S4 done Ec S3 rt ro di di C. Power Operation The power operation can be performed by combining exponential and natural logarithm operation. Since hyperbolic cordic perform above two operation, running it twice will generate the power operation. The following lit outline the brief tep to perform cordic baed power operation. Step to obtain x y. Vectoring mode, provide x = x+, y = x-, z = 2. You get z n = ln(x)/2 3. Multiply ln(x)/2 and 2 (by hifting) 4. Multiply ln(x) and y 5. Rotation mode, provide x = y = /An, z = y. 6. You get x n = e ylnx = x y With implementation of negative iteration, we are able to expand the upporting range of (x,y) input to the power block a hown in figure 4. Figure 4: Range of convergence compared between baic cordic and M=5 Ec Ec

4 For power operation, /An and other few contant need to be hard coded inide the top level of power vhdl file. A repreentaiton of number depend on floating point format, if generate tatement i ued to chooe among poible format. Data path and control unit for power operation i relatively imple once expanded hyperbolic cordic i done. Zn output i connected to hifter which perform the multiply by 2. The multiplier i floating point upported. Figure 5: Data path for power operation D. FIFO Interface To implement the power operation circuit to Zed board and control from proceor, AXI4-bu interface with FIFO wa ued. Therefore, input and output interface were required to pre and pot proce the data for power operation. The interface wa developed for both 32 bit and 64 bit. Since AXI4-full interface tranmit 32 bit at a time, different circuit wa required for two different floating point format. When N = 32, green box circuit i generated, and 2 FSM control the input and output. For N = 64, purple box circuit wa generated. Input create 64 bit number by combining two 32 bit number. The output i divided to two 32 bit number before entering FIFO. Again, eparate two FSM were ued to control operation. Figure 7: FIFO interface for N = 32 and 64 bit Power Operation Input FIFO Output FIFO DI X power DO iempty irden Y ofull owren done FSM for power operation i hown in figure 6. It implement the logic outline a Step to obtain x y in thi ection. Figure 6: ASM chart for Power FSM Reetn = S Vaddub, Ey S2 Vaddub, _xyz Cordic, mode S3 mode vcordic _xyz S4 _xyz S5 _xyz Cordic, mode S6 mode vcordic Eout S7 done E. SD Card Interface The Secure Digital Memory Card (hortly SD card) i the de facto tandard memory card for mobile equipment. The SDC ha a microcontroller in it. The flah memory control (block ize converion, error correction and wear leveling - known a FTL) are completed inide of the memory card. The data i tranferred between the memory card and the hot controller a data block in unit of 52 byte, o that it can be een a a block device like a generic hard dik drive from view point of upper level layer. SD card interface ue FATF file ytem. Fatf i a generic FAT file ytem module for mall embedded ytem. The Fatf module i written in compliance with ANSI C (C89) and completely eparated from the dik I/O layer. Therefore it i independent of the platform. It can be incorporated into mall microcontroller with limited reource. Sytem architecture of different layer of hardware and oftware i SD card IP i created in Xilinx SDK and interfaced with different librarie to upport SD card data tranfer. Our project ue the XSDPS librarie at driver level. Thi driver i ued to initialize read from and write to the SD card.

5 ued two floating point adder during one clock cycle and hence the propagation delay exceeded the clock frequency. The control logic implemented in the application layer uing C language i depicted uing a flow chart below for 32bit floating point number. The ame logic hall be ued for 64bit floating point number except for pecific Hardware interface function: MY_FP_32IP_mWriteMemory() and MY_FP_32IP_mReadMemory(). Start Main() Start SDCARD_Read_Write() Call the function SDCARD_Read_Write() Mount the Sdcard f_mount(); Stop Main() Open the input file SDTet.txt f_open(); Data tranfer: The SD card i put in tranfer tate to read from or write to it and work in polled mode uing ADMA2. The default block ize i 52 byte. File ytem: The xilff library i ued to read/write file to SD. Application file and function are developed independently and it upport read from a file in SD card repeatedly until end of the file and after manipulating the data, write back into SD card file in another format. The application level oftware i written by u. Thi i pictorially repreented a: Main() Ye Create and Open the output file Spad.txt f_open(); Move to beginning of inputfile End of input file No Read one line from inputfile f_get(); Get only 32 character into readbuffer (binary number) DecimalReult = Actual hexa value returned by NumberReturn() Convert thoe 32 character to number and tore into TempReult Call NumberReturn() by ending TempReult Reult i 32 bit hexal value Store one thi into Array No Check until two 32 bit are converted and tored Ye Continue till end of file Call twice MY_FP_32IP_mWriteMemory() Thi will end two input Thi will calculate X Power Y Reult Array = MY_FP_32IP_mReadMemory() Read one 32 digit hexa value from Memory Convert the reultant hex number to tring and tore into a big buffer SourceAddre Call Convert2HexaStr(); Save the content of Final Buffer SourceAddre into output file Call f_write(); Cloe input file and output file STOP SDCARD_Read_Write() Start SDCARD_Read_Write() III. EXPERIMENTAL SETUP For hardware component, tet bench wa created at every tage of development (hyperbolic cordic, power, FIFO interface). Initially, few random value are teted to confirm the each tep of ignal. After the confirmation of baic operation, large number of input are created uing MATLAB and fed to the hardware by reading input from text file. Reult are compared with MATLAB value and plotted. For ytem level imulation, the 32bit and 64bit SD card IP are created uing Vivado and launched into Xilinx SDK for SD card application development and teting. To acce the SD driver librarie there are ome BSP etting to be modified. To enure whether thi library incluion happened correctly, browe to project explorer and check xilff librarie are included and ff.c and correponding FATF file are created and linked automatically. During the implementation, we have encountered timing violation error. The Frequency of AXI bu wa originally MHz which i then reduced to MHz (5MHz didn t work). The root caue of the problem i identified a the long combinational logic and the negative iteration of CORDIC IV. RESULTS A. Hardware Component Simulation To check the reult of hardware architecture, generated reult were compared with MATLAB reult. For extended hyperbolic cordic, relative error of exponential operation and natural logarithm operation were plotted. Figure 7: Relative Error of e x

6 Figure 8: Relative Error of ln(x)/2 t value in ingle preciion i x42 2nd value 2 in ingle preciion i x4 Expected output = ^2, ^2, 2^2 etc. in ingle preciion The error for both operation wa very mall. For exponential, error wa within 2* -3 range, while error for natural logarithm wa within 2* -6 range. For power operation circuit, imulation wa performed large amount of time to validate the reult. A thi circuit contain multiplier and hifter, mall offet at the beginning become relatively viible offet. The example imulation reult i hown in figure 9. The relative error for thi cae wa about 2%. Figure 9: Example imulation reult: 2 = 99.8 Expected function: X power Y (i.e. X Y ) 64 Bit input: (X:,, 2 till 9 and Y: 2) in double preciion One example: t & 2nd value in double preciion i x rd & 4 th value 2 in double preciion i x 4 Expected output = ^2, ^2, 2^2 etc. in double preciion B. Sytem Level Simulation The reource uage of generated power IP (32 bit and 64 bit) are hown below. N LUT Flip Flop 32 bit 4378 (8%) bit 9464 (8%) 895 To tet the power IP uing SD card IP, we have ued different tet file each containing erie of number. The application i written in uch a way that all number in each file are read, proceed and reult are tored into a eparate file in the SD card. Some of them are explained below: Expected function: X power Y (i.e. X Y ) 32 Bit input: (X:,, 2 till 9 and Y: 2) in ingle preciion One example: CONCLUSIONS We have uccefully completed the project and made operational power calculation circuit within the time frame. The project howed how reource intenive to implement arithmetic operation in floating point format. Alo, it demontrated importance of inerting regiter inide large combination circuit to improve clock frequency. The effectivene of parameterized vhdl coding made it poible to try different floating point format with minimum modification. The accuracy of power operation can be improved by modifying number of poitive and negative iteration. Next tep to thi project will be to parameterize both M and N. Overall, it wa atifying to work on thi challenging project and get deep undertanding of both oftware and hardware ide of embedded ytem. REFERENCES [] Mack, J., Belletri, S., and Llamocca, D., "Floating Point CORDICbaed Architecture for Powering Computation", to appear in Proceeding of the th International Conference on ReConFigurable Computing and FPGA (ReConFig'25), Mayan Riviera, Mexico, December 25. [2] X. Hu, R.G. Harber, S.C. Ba, Expanding the range of convergence of the CORDIC algorithm, IEEE Tranaction on Computer, vol. 4, no., pp. 3-2, Jan. 99.