Reconfigurable Computing Systems ( L) Fall 2012 Tiny Register Machine (TRM)
|
|
- Lesley Daniels
- 6 years ago
- Views:
Transcription
1 Reconfigurable Computing Systems ( L) Fall 2012 Tiny Register Machine (TRM) L. Liu Department of Computer Science, ETH Zürich Fall semester,
2 Introduction Jumping up a few levels of abstraction. Architecture: the programmer s view of the computer Defined by instructions (operations) and operand locations Microarchitecture: how to implement an architecture in hardware Application Software O perating System s Architecture M icroarchitecture Logic D igital Circuits Analog Circuits Devices program s device drivers instructions registers datapaths controllers adders m em ories AND gates N O T gates am plifiers filte rs transistors diodes Physics electrons Adapted from Digital Design and Computer Architecture, David Money Harris & Sarah L. Elsevier 2
3 Assembly Language To command a computer, you must understand its language. Instructions: words in a computer s language Instruction set: the vocabulary of a computer s language Instructions indicate the operation to perform and the operands to use. Assembly language: human-readable format of instructions Machine language: computer-readable format (1 s and 0 s) Assembler: a tool to translate assembly code into machine code TRM (Tiny Register Machine) architecture: Designed by Prof. Niklaus Wirth and implemented on Xilinx Spartan-3, Virtex-5 and Spartan-6 by Ling Liu. A RISC processor that only contains the necessary instructions to run an application written in a high-level language. Once you ve learned one architecture, it s easy to learn others. 3
4 Architecture Design Principles Underlying design principles, as articulated by Hennessy and Patterson: 1.Simplicity favors regularity 2.Make the common case fast 3.Smaller is faster 4.Good design demands good compromises 4
5 Design Principle 1 Simplicity favors regularity - Consistent instruction format - Same number of operands, easier to encode and handle in hardware TRM instruction encoding 5
6 Design Principle 2 Make the common case fast - ALU operations are performed on registers and constants - TRM is a reduced instruction set computer (RISC), with a small number of simple instructions. - The main characteristic of RISC architecture is to allow most instructions to be executed in one clock cycle. 6
7 Design Principle 3 Smaller is Faster - TRM includes only a small number of registers - Just as retrieving data from a few books on your table is faster than sorting through 1000 books, retrieving data from 32 registers is faster than retrieving it from 1000 registers or a large memory. 7
8 Design Principle 4 Good design demands good compromises - Multiple instruction formats allow flexibility - ADD, SUB: use 2 register operands - LD, ST: use 2 register operands and a constant - Number of instruction formats kept small - to adhere to design principles 1 and 3 (simplicity favors regularity and smaller is faster). 8
9 TRM Machine Language Computers only understand 1 s and 0 s Machine language: binary representation of instructions 18-bit instructions Three instruction types: Type a: arithmetical and logical operations Type b: load and store instructions Type c: branch instructions (for jumping) 9
10 Type a: Arithmetical and Logical Instructions 1 or 2 register operands: Rs: source registers Rd: destination register n: immediate, zero-extended Other fields: op: the operation code or opcode regsel: bit 10 (1 means source operand comes from Rs register) 10
11 The TRM Registers Name R0~R7 R7 R6 PC C N Z V Register Number 0 ~ Usage Working register Normally used as link register Normally used as stack pointer Program pointer Carry flag (1 bit) Sign flag (1 bit) Zero flag (1 bit) Overflow flag (1 bit) 11
12 can be ignored
13 The Power of the Stored Program 18-bit instructions and 32-bit data stored in memory Sequence of instructions: only difference between two applications (for example, a text editor and a video game) To run a new program: No rewiring required Simply store new program in memory The processor hardware executes the program: fetches (reads) the instructions from instruction memory in sequence performs the specified operation The program counter (PC) keeps track of the current instruction In TRM, programs start at memory address 0x000 13
14 The Stored Program Assembly Code LD R2, [R0+32] ADD R1, R2 SUB R0, 12 SUB R0, R5 Machine Code 0x x08C02 0x0C00C 0x0C405 Stored Program Address Instructions 003 0C C00C C PC Instruction Memory 14
15 Type b: Load and Store Instructions memory base address register (Rs) 7-bit offset (n), zero-extended Bit 10 is always 0 for TRM, 1 for VTRM 15
16 op instruction operation code (binary) 1100 LD Rd, Rs, n If Rs = R7 then Rd := mem[n] else Rd := mem[rs+n] 1101 ST Rd, Rs, n If Rs = R7 then Mem[n] := Rd else Mem[Rs+n] := Rd 1100ddd0nnnnnnnsss 1101ddd0nnnnnnnsss
17 Type c: Branch Instructions Jump conditions (cond) 10/14-bit address offset operand (off) 17
18 Branch Instructions op instruction operation code (binary) 1110 Bc n PC := PC n, on condition c 1111 BL n R7 := PC + 1; PC := PC +1+n 1110ccccnnnnnnnnnn 1111nnnnnnnnnnnnnn 18
19 Branching Allows a program to execute instructions out of sequence. Types of branches: Conditional branches branch if equal (BEQ) branch if not equal (BNE) Unconditional branches BT jump register (BR) jump and link (BL, BLR) 19
20 cond condition meaning Mnemonic 0000 Z Zero / equal BEQ (BZS) 0001 ~Z Non-zero / unequal BNE (BZC) 0010 C Carry / above or equal (unsigned) BAE (BCS) 0011 ~C No carry / below (unsigned) BB (BCC) 0100 N Negative BN (BNS) 0101 ~N Not negative BNN (BNC) 0110 V Overflow BO (BVS) 0111 ~V No overflow BNO (BVC) 1000 ~(~C Z) Carry and no zero / above (unsigned) BA 1001 ~C Z No carry or zero / below or equal (unsigned) BBE 1010 ~(N V) N=V / greater or equal (signed) BGE 1011 N V N V / less (signed) BLT 1100 ~((N V) Z) greater or equal and ~ZF / greater (signed) BGT 1101 (N V) Z less or Z / less or equal (signed) BLE 1110 TRUE Always BT (B) 1111 FALSE Never BF N = bit 31 of result Z = all 32 bits are zero C = carry V = overflow
21 Conditional Branching (*TRM assembly*) MOV R0, 4 (*R0 = 4*) MOV R1, 1 (*R1 = 1*) SUB R0, R1 (*R0 = R0 R1 = 3*) BNE target (*branch is taken*) ADD R1, 3 (*not executed*) target: (*label*) ADD R1, R1 (*R1 = 1+1 = 2*) Labels indicate instruction locations in a program. 21
22 The Branch Not Taken (*TRM assembly*) MOV R0, 4 (*R0 = 4*) MOV R1, 1 (*R1 = 1*) SUB R0, R1 (*R0 = R0 R1 = 3*) BEQ target (*branch is not taken*) ADD R1, 3 (*executed*) target: (*label*) ADD R1, R1 (*R1 = 1+1 = 2*) 22
23 Unconditional Branching / Jumping (BT) (*TRM assembly*) MOV R0, 4 (*R0 = 4*) MOV R1, 1 (*R1 = 1*) BT target (*jump to target*) ROR R1 2 (*not executed*) target: ADD R1, R0 (*R1 = = 5*) 23
24 Review: Instruction Formats 24
25 High-Level Code Constructs if statements if/else statements while loops for loops 25
26 If Statement High-level code IF i = j THEN f := g + h; TRM assembly code (* R0 = f, R1 = g, R2 = h R3 = i, R4 = j*) f := f i; 26
27 If Statement High-level code IF i = j THEN f := g + h; f := f i; TRM assembly code (* R0 = f, R1 = g, R2 = h R3 = i, R4 = j*) SUB R4, R3 BNE L1 ADD R1, R2 MOV R0, R1 L1: SUB R0, R3 Done: BT Done Notice that the assembly tests for the opposite case (i!= j) than the test in the high-level code (i == j). 27
28 If / Else Statement High-level code IF i = j THEN f := g + h; ELSE f := f i; TRM assembly code (* R0 = f, R1 = g, R2 = h R3 = i, R4 = j *) 28
29 If / Else Statement High-level code IF i = j THEN f := g + h; ELSE f := f i; TRM assembly code (* R0 = f, R1 = g, R2 = h R3 = i, R4 = j*) SUB R4, R3 BNE L1 ADD R1, R2 MOV R0, R1 BT Done L1: SUB R0, R3 Done: BT Done 29
30 While Loops High-level code (* determines the power of x such that 2 x = 128*) TRM assembly code (*R0 = pow, R1 = x*) VAR pow, x: INTEGER; BEGIN pow := 1; x := 0; END WHILE pow # 128 DO pow := pow * 2; x := x + 1; END 30
31 While Loops High-level code (* determines the power of x such that 2 x = 128*) VAR pow, x: INTEGER; BEGIN pow := 1; x := 0; END WHILE pow # 128 DO pow := pow * 2; x := x + 1; END TRM assembly code (*R0 = pow, R1 = x*) MOV R0, 1 MOV R1, 0 while: MOV R2, R0 SUB R2, 128 BEQ done ADD R0, R0 ADD R1, 1 BT while done: BT done Notice that the assembly tests for the opposite case (pow == 128) than the test in the high-level code (pow!= 128). 31
32 For Loops The general form of a for loop is: FOR initialization TO condition BY loop operation DO loop body END initialization: executes before the loop begins condition: is tested at the beginning of each iteration loop operation: executes at the end of each iteration loop body: executes each time the condition is met 32
33 For Loops High-level code (* add the numbers from 0 to 9*) VAR sum, i: INTEGER BEGIN sum := 0; TRM assembly code (*R0 = i, R1 = sum*) END FOR i:=0 TO 9 BY 1 DO sum := sum + i; END 33
34 For Loops High-level code (* add the numbers from 0 to 9*) VAR sum, i: INTEGER BEGIN sum := 0; END FOR i:=0 TO 9 BY 1 DO sum := sum + i; END TRM assembly code (*R0 = i, R1 = sum*) MOV R1, 0 MOV R0, 0 for: MOV R2, R0 SUB R2, 10 BEQ done ADD R1, R0 ADD R0, 1 BT for done: BT done Notice that the assembly tests for the opposite case (i == 10) than the test in the high-level code (i!= 10). 34
35 Arrays Useful for accessing large amounts of similar data Array element: accessed by index Array size: number of elements in the array 35
36 Arrays 5-element array Base address = 0x010 (address of the first array element, array[0]) First step in accessing an array: load base address into a register 36
37 Arrays // high-level code int array[5]; array[0] = 5; array[0] = array[0] * 2; array[1] = array[1] * 2; ; TRM assembly code ; Array base address = R0 37
38 Arrays (*high-level code*) VAR array: ARRAY 5 OF INTEGER; array[0] := 5; array[0] := array[0] * 2; array[1] := array[1] * 2; (* TRM assembly code array base address = R0*) MOV R0, 0 (*put 0x00 in R0*) MOV R1, 5 ST R1, [R0] (*array[0] = 5*) LD R1, [R0] (*R1 = array[0]*) ROR R1, 31 BIC R1, 1 (*array[0] = array[0] * 2*) ST R1, [R0] LD R1, [R0+1] (*R1 = array[1]*) ROR R1, 31 BIC R1, 1 ST R1 [R0+1] 38
39 Arrays Using For Loops (*high-level code*) VAR array : ARRAY 1000 OF INTEGER; i: INTEGER; BEGIN FOR i:=0 TO 999 DO array[i] = array[i] * 8; END END (* TRM assembly code R0 = array base address, R3 = i*) 39
40 Arrays Using For Loops (* TRM assembly code R0 = array base address, R3 = i*) MOV R0, 0 (*R0 = 0x00*) MOV R3, 0 (*i = 0*) loop: MOV R2, R3 SUB R2, 1000 BAE done (*if i >= 1000 then done*) MOV R2, R3 ADD R2, R0 LD R1, [R2] (*R0 = array[i]*) ROR R1, 29 BIC R1, 7 ST R1, [R2] ADD R3, 1 (*i = i + 1*) BT loop (*repeat*) done: BT done 40
41 Procedure Calls Definitions Caller: calling procedure (in this case, main) Callee: called procedure (in this case, sum) High-level code VAR y: INTEGER PROCEDURE sum(a, b: INTEGER):INTEGER; BEGIN RETURN (a + b); END BEGIN y := sum(42, 7);... END 41
42 Procedure Calls Procedure calling conventions: Caller: Callee: passes arguments to callee. jumps to the callee performs the procedure returns the result to caller returns to the point of call must not overwrite registers or memory needed by the caller TRM conventions: Call procedure: branch and link (BL) Return from procedure: jump register (BR) Argument values: can be passed via stack or registers Return value: passed via register R0 42
43 Procedure Calls TRM assembly code code --- BR R x019 BL > [Proc.sum] 0x BL: jumps to sum and saves PC+1 in the return address register (R7). In this case, R7 = 0x020 after BL executes. BR R7: jumps to address in R7, in this case 0x
44 Looking Ahead Microarchitecture building TRM processor in hardware! Bring colored pencils 44
Reconfigurable Computing Systems ( L) Fall 2012 Microarchitecture: Single Cycle Implementation of TRM
Reconfigurable Computing Systems (252-2210-00L) Fall 2012 Microarchitecture: Single Cycle Implementation of TRM L. Liu Department of Computer Science, ETH Zürich Fall semester, 2012 1 Introduction Microarchitecture:
More informationArchitecture. Digital Computer Design
Architecture Digital Computer Design Architecture The architecture is the programmer s view of a computer. It is defined by the instruction set (language) and operand locations (registers and memory).
More informationCISC 662 Graduate Computer Architecture. Lecture 4 - ISA MIPS ISA. In a CPU. (vonneumann) Processor Organization
CISC 662 Graduate Computer Architecture Lecture 4 - ISA MIPS ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,
More informationCISC 662 Graduate Computer Architecture. Lecture 4 - ISA
CISC 662 Graduate Computer Architecture Lecture 4 - ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,
More informationCOMPSCI 313 S Computer Organization. 7 MIPS Instruction Set
COMPSCI 313 S2 2018 Computer Organization 7 MIPS Instruction Set Agenda & Reading MIPS instruction set MIPS I-format instructions MIPS R-format instructions 2 7.1 MIPS Instruction Set MIPS Instruction
More information10-1 C D Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e
10-1 C D E A B 10-2 A B A B C (A B) C D A A B (A B) C E D (A B) C D E (A B) C + D E (A B) C 10-3 Opcode Mode Address or operand 10-4 Memory 250 Opcode Mode PC = 250 251 ADRS 252 Next instruction ACC Opcode:
More informationEE 3170 Microcontroller Applications
Lecture Overview EE 3170 Microcontroller Applications Lecture 7 : Instruction Subset & Machine Language: Conditions & Branches in Motorola 68HC11 - Miller 2.2 & 2.3 & 2.4 Based on slides for ECE3170 by
More informationELEC / Computer Architecture and Design Fall 2013 Instruction Set Architecture (Chapter 2)
ELEC 5200-001/6200-001 Computer Architecture and Design Fall 2013 Instruction Set Architecture (Chapter 2) Victor P. Nelson, Professor & Asst. Chair Vishwani D. Agrawal, James J. Danaher Professor Department
More informationInstructions: MIPS ISA. Chapter 2 Instructions: Language of the Computer 1
Instructions: MIPS ISA Chapter 2 Instructions: Language of the Computer 1 PH Chapter 2 Pt A Instructions: MIPS ISA Based on Text: Patterson Henessey Publisher: Morgan Kaufmann Edited by Y.K. Malaiya for
More informationChapter 04: Instruction Sets and the Processor organizations. Lesson 08: Processor Instructions - Part 1
Chapter 04: Instruction Sets and the Processor organizations Lesson 08: Processor Instructions - Part 1 1 Objective Understand the load, store instructions and register transfer instructions Understand
More informationCprE 288 Introduction to Embedded Systems ARM Assembly Programming: Translating C Control Statements and Function Calls
CprE 288 Introduction to Embedded Systems ARM Assembly Programming: Translating C Control Statements and Function Calls Instructors: Dr. Phillip Jones 1 Announcements Final Projects Projects: Mandatory
More informationComputer Organization MIPS ISA
CPE 335 Computer Organization MIPS ISA Dr. Iyad Jafar Adapted from Dr. Gheith Abandah Slides http://www.abandah.com/gheith/courses/cpe335_s08/index.html CPE 232 MIPS ISA 1 (vonneumann) Processor Organization
More informationInstructions: Language of the Computer
CS359: Computer Architecture Instructions: Language of the Computer Yanyan Shen Department of Computer Science and Engineering 1 The Language a Computer Understands Word a computer understands: instruction
More informationCS3350B Computer Architecture
CS3350B Computer Architecture Winter 2015 Lecture 4.1: MIPS ISA: Introduction Marc Moreno Maza www.csd.uwo.ca/courses/cs3350b [Adapted d from lectures on Computer Organization and Design, Patterson & Hennessy,
More informationChapter 3. Instructions:
Chapter 3 1 Instructions: Language of the Machine More primitive than higher level languages e.g., no sophisticated control flow Very restrictive e.g., MIPS Arithmetic Instructions We ll be working with
More informationProgrammable Machines
Programmable Machines Silvina Hanono Wachman Computer Science & Artificial Intelligence Lab M.I.T. Quiz 1: next week Covers L1-L8 Oct 11, 7:30-9:30PM Walker memorial 50-340 L09-1 6.004 So Far Using Combinational
More informationProgrammable Machines
Programmable Machines Silvina Hanono Wachman Computer Science & Artificial Intelligence Lab M.I.T. Quiz 1: next week Covers L1-L8 Oct 11, 7:30-9:30PM Walker memorial 50-340 L09-1 6.004 So Far Using Combinational
More informationChapter 2A Instructions: Language of the Computer
Chapter 2A Instructions: Language of the Computer Copyright 2009 Elsevier, Inc. All rights reserved. Instruction Set The repertoire of instructions of a computer Different computers have different instruction
More informationCprE 288 Introduction to Embedded Systems Course Review for Exam 3. Instructors: Dr. Phillip Jones
CprE 288 Introduction to Embedded Systems Course Review for Exam 3 Instructors: Dr. Phillip Jones 1 Announcements Exam 3: See course website for day/time. Exam 3 location: Our regular classroom Allowed
More information1 5. Addressing Modes COMP2611 Fall 2015 Instruction: Language of the Computer
1 5. Addressing Modes MIPS Addressing Modes 2 Addressing takes care of where to find data instruction We have seen, so far three addressing modes of MIPS (to find data): 1. Immediate addressing: provides
More informationComputer Architecture
CS3350B Computer Architecture Winter 2015 Lecture 4.2: MIPS ISA -- Instruction Representation Marc Moreno Maza www.csd.uwo.ca/courses/cs3350b [Adapted from lectures on Computer Organization and Design,
More informationEC 413 Computer Organization
EC 413 Computer Organization Review I Prof. Michel A. Kinsy Computing: The Art of Abstraction Application Algorithm Programming Language Operating System/Virtual Machine Instruction Set Architecture (ISA)
More informationControl Instructions. Computer Organization Architectures for Embedded Computing. Thursday, 26 September Summary
Control Instructions Computer Organization Architectures for Embedded Computing Thursday, 26 September 2013 Many slides adapted from: Computer Organization and Design, Patterson & Hennessy 4th Edition,
More informationControl Instructions
Control Instructions Tuesday 22 September 15 Many slides adapted from: and Design, Patterson & Hennessy 5th Edition, 2014, MK and from Prof. Mary Jane Irwin, PSU Summary Previous Class Instruction Set
More informationProcessor Status Register(PSR)
ARM Registers Register internal CPU hardware device that stores binary data; can be accessed much more rapidly than a location in RAM ARM has 13 general-purpose registers R0-R12 1 Stack Pointer (SP) R13
More informationMIPS R-format Instructions. Representing Instructions. Hexadecimal. R-format Example. MIPS I-format Example. MIPS I-format Instructions
Representing Instructions Instructions are encoded in binary Called machine code MIPS instructions Encoded as 32-bit instruction words Small number of formats encoding operation code (opcode), register
More informationUnsigned and signed integer numbers
Unsigned and signed integer numbers Binary Unsigned Signed 0000 0 0 0001 1 1 0010 2 2 0011 3 3 0100 4 4 Subtraction sets C flag opposite of carry (ARM specialty)! - if (carry = 0) then C=1 - if (carry
More informationStored Program Concept. Instructions: Characteristics of Instruction Set. Architecture Specification. Example of multiple operands
Stored Program Concept Instructions: Instructions are bits Programs are stored in memory to be read or written just like data Processor Memory memory for data, programs, compilers, editors, etc. Fetch
More informationLecture 2. Instructions: Language of the Computer (Chapter 2 of the textbook)
Lecture 2 Instructions: Language of the Computer (Chapter 2 of the textbook) Instructions: tell computers what to do Chapter 2 Instructions: Language of the Computer 2 Introduction Chapter 2.1 Chapter
More informationTopic Notes: MIPS Instruction Set Architecture
Computer Science 220 Assembly Language & Comp. Architecture Siena College Fall 2011 Topic Notes: MIPS Instruction Set Architecture vonneumann Architecture Modern computers use the vonneumann architecture.
More informationAssembly language Simple, regular instructions building blocks of C, Java & other languages Typically one-to-one mapping to machine language
Assembly Language Readings: 2.1-2.7, 2.9-2.10, 2.14 Green reference card Assembly language Simple, regular instructions building blocks of C, Java & other languages Typically one-to-one mapping to machine
More informationMachine Language Instructions Introduction. Instructions Words of a language understood by machine. Instruction set Vocabulary of the machine
Machine Language Instructions Introduction Instructions Words of a language understood by machine Instruction set Vocabulary of the machine Current goal: to relate a high level language to instruction
More informationENGN1640: Design of Computing Systems Topic 03: Instruction Set Architecture Design
ENGN1640: Design of Computing Systems Topic 03: Instruction Set Architecture Design Professor Sherief Reda http://scale.engin.brown.edu School of Engineering Brown University Spring 2014 Sources: Computer
More informationComputer Science and Engineering 331. Midterm Examination #1. Fall Name: Solutions S.S.#:
Computer Science and Engineering 331 Midterm Examination #1 Fall 2000 Name: Solutions S.S.#: 1 41 2 13 3 18 4 28 Total 100 Instructions: This exam contains 4 questions. It is closed book and notes. Calculators
More informationENGN1640: Design of Computing Systems Topic 03: Instruction Set Architecture Design
ENGN1640: Design of Computing Systems Topic 03: Instruction Set Architecture Design Professor Sherief Reda http://scale.engin.brown.edu School of Engineering Brown University Spring 2016 1 ISA is the HW/SW
More informationCourse Administration
Fall 2017 EE 3613: Computer Organization Chapter 2: Instruction Set Architecture 2/4 Avinash Kodi Department of Electrical Engineering & Computer Science Ohio University, Athens, Ohio 45701 E-mail: kodi@ohio.edu
More informationARM Assembly Language. Programming
Outline: ARM Assembly Language the ARM instruction set writing simple programs examples Programming hands-on: writing simple ARM assembly programs 2005 PEVE IT Unit ARM System Design ARM assembly language
More informationLectures 3-4: MIPS instructions
Lectures 3-4: MIPS instructions Motivation Learn how a processor s native language looks like Discover the most important software-hardware interface MIPS Microprocessor without Interlocked Pipeline Stages
More informationEN164: Design of Computing Systems Topic 03: Instruction Set Architecture Design
EN164: Design of Computing Systems Topic 03: Instruction Set Architecture Design Professor Sherief Reda http://scale.engin.brown.edu Electrical Sciences and Computer Engineering School of Engineering Brown
More informationAssembly language Simple, regular instructions building blocks of C, Java & other languages Typically one-to-one mapping to machine language
Assembly Language Readings: 2.1-2.7, 2.9-2.10, 2.14 Green reference card Assembly language Simple, regular instructions building blocks of C, Java & other languages Typically one-to-one mapping to machine
More informationCourse Administration
Fall 2018 EE 3613: Computer Organization Chapter 2: Instruction Set Architecture Introduction 4/4 Avinash Karanth Department of Electrical Engineering & Computer Science Ohio University, Athens, Ohio 45701
More informationECE232: Hardware Organization and Design. Computer Organization - Previously covered
ECE232: Hardware Organization and Design Part 6: MIPS Instructions II http://www.ecs.umass.edu/ece/ece232/ Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Computer Organization
More informationInstructions: Language of the Computer
Instructions: Language of the Computer Tuesday 22 September 15 Many slides adapted from: and Design, Patterson & Hennessy 5th Edition, 2014, MK and from Prof. Mary Jane Irwin, PSU Summary Previous Class
More informationComparison InstruCtions
Status Flags Now it is time to discuss what status flags are available. These five status flags are kept in a special register called the Program Status Register (PSR). The PSR also contains other important
More informationChapter 2. Instruction Set Architecture (ISA)
Chapter 2 Instruction Set Architecture (ISA) MIPS arithmetic Design Principle: simplicity favors regularity. Why? Of course this complicates some things... C code: A = B + C + D; E = F - A; MIPS code:
More informationThe Assembly Language of the Boz 5
The Assembly Language of the Boz 5 The Boz 5 uses bits 31 27 of the IR as a five bit opcode. Of the possible 32 opcodes, only 26 are implemented. Op-Code Mnemonic Description 00000 HLT Halt the Computer
More informationCENG3420 Lecture 03 Review
CENG3420 Lecture 03 Review Bei Yu byu@cse.cuhk.edu.hk 2017 Spring 1 / 38 CISC vs. RISC Complex Instruction Set Computer (CISC) Lots of instructions of variable size, very memory optimal, typically less
More informationOverview. Introduction to the MIPS ISA. MIPS ISA Overview. Overview (2)
Introduction to the MIPS ISA Overview Remember that the machine only understands very basic instructions (machine instructions) It is the compiler s job to translate your high-level (e.g. C program) into
More informationChapter 2. Instructions:
Chapter 2 1 Instructions: Language of the Machine More primitive than higher level languages e.g., no sophisticated control flow Very restrictive e.g., MIPS Arithmetic Instructions We ll be working with
More informationIntroduction to the MIPS. Lecture for CPSC 5155 Edward Bosworth, Ph.D. Computer Science Department Columbus State University
Introduction to the MIPS Lecture for CPSC 5155 Edward Bosworth, Ph.D. Computer Science Department Columbus State University Introduction to the MIPS The Microprocessor without Interlocked Pipeline Stages
More informationComputer Organization and Structure. Bing-Yu Chen National Taiwan University
Computer Organization and Structure Bing-Yu Chen National Taiwan University Instructions: Language of the Computer Operations and Operands of the Computer Hardware Signed and Unsigned Numbers Representing
More informationChapter 2. Computer Abstractions and Technology. Lesson 4: MIPS (cont )
Chapter 2 Computer Abstractions and Technology Lesson 4: MIPS (cont ) Logical Operations Instructions for bitwise manipulation Operation C Java MIPS Shift left >>> srl Bitwise
More informationMicrocontroller Systems
µcontroller systems 1 / 43 Microcontroller Systems Engineering Science 2nd year A2 Lectures Prof David Murray david.murray@eng.ox.ac.uk www.robots.ox.ac.uk/ dwm/courses/2co Michaelmas 2014 µcontroller
More informationInstructions: MIPS arithmetic. MIPS arithmetic. Chapter 3 : MIPS Downloaded from:
Instructions: Chapter 3 : MIPS Downloaded from: http://www.cs.umr.edu/~bsiever/cs234/ Language of the Machine More primitive than higher level languages e.g., no sophisticated control flow Very restrictive
More informationCOMP MIPS instructions 2 Feb. 8, f = g + h i;
Register names (save, temporary, zero) From what I have said up to now, you will have the impression that you are free to use any of the 32 registers ($0,..., $31) in any instruction. This is not so, however.
More informationChapter 2. Instructions: Language of the Computer. HW#1: 1.3 all, 1.4 all, 1.6.1, , , , , and Due date: one week.
Chapter 2 Instructions: Language of the Computer HW#1: 1.3 all, 1.4 all, 1.6.1, 1.14.4, 1.14.5, 1.14.6, 1.15.1, and 1.15.4 Due date: one week. Practice: 1.5 all, 1.6 all, 1.10 all, 1.11 all, 1.14 all,
More informationComputer Organization and Components
2 Course Structure Computer Organization and Components Module 4: Memory Hierarchy Module 1: Logic Design IS1500, fall 2014 Lecture 4: and F1 DC Ö1 F2 DC Ö2 F7b Lab: dicom F8 Module 2: C and Associate
More informationChapter 2: Instructions:
Chapter 2: Instructions: Language of the Computer Computer Architecture CS-3511-2 1 Instructions: To command a computer s hardware you must speak it s language The computer s language is called instruction
More informationBasic Processor Design
Basic Processor Design Design Instruction Set Design Datapath Design Control Unit This lecture deals with Instruction Set Design. 1001 Instruction Set Terminology Mnemonic (Instruction Name) SUBI Syntax
More informationChapter 3 MIPS Assembly Language. Ó1998 Morgan Kaufmann Publishers 1
Chapter 3 MIPS Assembly Language Ó1998 Morgan Kaufmann Publishers 1 Instructions: Language of the Machine More primitive than higher level languages e.g., no sophisticated control flow Very restrictive
More informationLecture VIII: Branching and Control Statements. Xuan Guo. CSC 3210 Computer Organization and Programming Georgia State University.
Lecture VIII: Branching and Control Statements CSC 3210 Computer Organization and Programming Georgia State University February 5, 2015 This lecture Plan for the lecture: Recap: Filling delay slot Branching
More informationSystems Architecture I
Systems Architecture I Topics Assemblers, Linkers, and Loaders * Alternative Instruction Sets ** *This lecture was derived from material in the text (sec. 3.8-3.9). **This lecture was derived from material
More informationThomas Polzer Institut für Technische Informatik
Thomas Polzer tpolzer@ecs.tuwien.ac.at Institut für Technische Informatik Branch to a labeled instruction if a condition is true Otherwise, continue sequentially beq rs, rt, L1 if (rs == rt) branch to
More informationExam 1 Fun Times. EE319K Fall 2012 Exam 1A Modified Page 1. Date: October 5, Printed Name:
EE319K Fall 2012 Exam 1A Modified Page 1 Exam 1 Fun Times Date: October 5, 2012 Printed Name: Last, First Your signature is your promise that you have not cheated and will not cheat on this exam, nor will
More informationECE 486/586. Computer Architecture. Lecture # 8
ECE 486/586 Computer Architecture Lecture # 8 Spring 2015 Portland State University Lecture Topics Instruction Set Principles MIPS Control flow instructions Dealing with constants IA-32 Fallacies and Pitfalls
More informationEEM870 Embedded System and Experiment Lecture 4: ARM Instruction Sets
EEM870 Embedded System and Experiment Lecture 4 ARM Instruction Sets Wen-Yen Lin, Ph.D. Department of Electrical Engineering Chang Gung University Email wylin@mail.cgu.edu.tw March 2014 Introduction Embedded
More informationChapter 2. Instructions: Language of the Computer. Adapted by Paulo Lopes
Chapter 2 Instructions: Language of the Computer Adapted by Paulo Lopes Instruction Set The repertoire of instructions of a computer Different computers have different instruction sets But with many aspects
More informationAssembly Language. Prof. Dr. Antônio Augusto Fröhlich. Sep 2006
Sep 2006 Prof. Antônio Augusto Fröhlich (http://www.lisha.ufsc.br) 33 Assembly Language Prof. Dr. Antônio Augusto Fröhlich guto@lisha.ufsc.br http://www.lisha.ufsc.br/~guto Sep 2006 Sep 2006 Prof. Antônio
More informationComputer Organization and Structure. Bing-Yu Chen National Taiwan University
Computer Organization and Structure Bing-Yu Chen National Taiwan University Instructions: Language of the Computer Operations and Operands of the Computer Hardware Signed and Unsigned Numbers Representing
More informationExam 1. Date: Oct 4, 2018
Exam 1 Date: Oct 4, 2018 UT EID: Professor: Valvano Printed Name: Last, First Your signature is your promise that you have not cheated and will not cheat on this exam, nor will you help others to cheat
More informationCOMPUTER HARDWARE. Instruction Set Architecture
COMPUTER HARDWARE Instruction Set Architecture Overview Computer architecture Operand addressing Addressing architecture Addressing modes Elementary instructions Data transfer instructions Data manipulation
More informationEEC 581 Computer Architecture Lecture 1 Review MIPS
EEC 581 Computer Architecture Lecture 1 Review MIPS 1 Supercomputing: Suddenly Fancy 2 1 Instructions: Language of the Machine More primitive than higher level languages e.g., no sophisticated control
More informationMath 230 Assembly Programming (AKA Computer Organization) Spring 2008
Math 230 Assembly Programming (AKA Computer Organization) Spring 2008 MIPS Intro II Lect 10 Feb 15, 2008 Adapted from slides developed for: Mary J. Irwin PSU CSE331 Dave Patterson s UCB CS152 M230 L10.1
More informationEE319K Exam 1 Summer 2014 Page 1. Exam 1. Date: July 9, Printed Name:
EE319K Exam 1 Summer 2014 Page 1 Exam 1 Date: July 9, 2014 UT EID: Printed Name: Last, First Your signature is your promise that you have not cheated and will not cheat on this exam, nor will you help
More informationLecture Topics. Branch Condition Options. Branch Conditions ECE 486/586. Computer Architecture. Lecture # 8. Instruction Set Principles.
ECE 486/586 Computer Architecture Lecture # 8 Spring 2015 Portland State University Instruction Set Principles MIPS Control flow instructions Dealing with constants IA-32 Fallacies and Pitfalls Reference:
More informationComputer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: MIPS Instruction Set Architecture
Computer Science 324 Computer Architecture Mount Holyoke College Fall 2009 Topic Notes: MIPS Instruction Set Architecture vonneumann Architecture Modern computers use the vonneumann architecture. Idea:
More informationInstructions: Assembly Language
Chapter 2 Instructions: Assembly Language Reading: The corresponding chapter in the 2nd edition is Chapter 3, in the 3rd edition it is Chapter 2 and Appendix A and in the 4th edition it is Chapter 2 and
More informationECE260: Fundamentals of Computer Engineering
Datapath for a Simplified Processor James Moscola Dept. of Engineering & Computer Science York College of Pennsylvania Based on Computer Organization and Design, 5th Edition by Patterson & Hennessy Introduction
More informationECE232: Hardware Organization and Design
ECE232: Hardware Organization and Design Lecture 4: Logic Operations and Introduction to Conditionals Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Overview Previously examined
More informationTABLE 9-1. Symbolic Convention for Addressing Modes. Register indirect LDA (R1) ACC M[ R1] Refers to Figure 9-4. Addressing mode. Symbolic convention
T-236 Symbolic Convention for Addressing Modes TABLE 9-1 Symbolic Convention for Addressing Modes Refers to Figure 9-4 Addressing mode Symbolic convention Register transfer Effective address Contents of
More informationARM Shift Operations. Shift Type 00 - logical left 01 - logical right 10 - arithmetic right 11 - rotate right. Shift Amount 0-31 bits
ARM Shift Operations A novel feature of ARM is that all data-processing instructions can include an optional shift, whereas most other architectures have separate shift instructions. This is actually very
More informationDesign of Digital Circuits 2017 Srdjan Capkun Onur Mutlu (Guest starring: Frank K. Gürkaynak and Aanjhan Ranganathan)
Microarchitecture Design of Digital Circuits 27 Srdjan Capkun Onur Mutlu (Guest starring: Frank K. Gürkaynak and Aanjhan Ranganathan) http://www.syssec.ethz.ch/education/digitaltechnik_7 Adapted from Digital
More informationElementos de Lógica Digital II
Elementos de Lógica Digital II COMP09 μprocessor Vanderlei Bonato Eduardo Simões 07/11/2010 1 Introduction Architecture: the programmer s view of the computer Defined by instructions (operations) and operand
More informationInstructions: Language of the Computer
CS359: Computer Architecture Instructions: Language of the Computer Yanyan Shen Department of Computer Science and Engineering 1 The Language a Computer Understands Word a computer understands: instruction
More informationEE319K Fall 2013 Exam 1B Modified Page 1. Exam 1. Date: October 3, 2013
EE319K Fall 2013 Exam 1B Modified Page 1 Exam 1 Date: October 3, 2013 UT EID: Printed Name: Last, First Your signature is your promise that you have not cheated and will not cheat on this exam, nor will
More informationChapter 1. Computer Abstractions and Technology. Lesson 3: Understanding Performance
Chapter 1 Computer Abstractions and Technology Lesson 3: Understanding Performance Manufacturing ICs 1.7 Real Stuff: The AMD Opteron X4 Yield: proportion of working dies per wafer Chapter 1 Computer Abstractions
More informationare Softw Instruction Set Architecture Microarchitecture are rdw
Program, Application Software Programming Language Compiler/Interpreter Operating System Instruction Set Architecture Hardware Microarchitecture Digital Logic Devices (transistors, etc.) Solid-State Physics
More informationCS222: MIPS Instruction Set
CS222: MIPS Instruction Set Dr. A. Sahu Dept of Comp. Sc. & Engg. Indian Institute of Technology Guwahati 1 Outline Previous Introduction to MIPS Instruction Set MIPS Arithmetic's Register Vs Memory, Registers
More informationISA and RISCV. CASS 2018 Lavanya Ramapantulu
ISA and RISCV CASS 2018 Lavanya Ramapantulu Program Program =?? Algorithm + Data Structures Niklaus Wirth Program (Abstraction) of processor/hardware that executes 3-Jul-18 CASS18 - ISA and RISCV 2 Program
More informationMIPS (SPIM) Assembler Syntax
MIPS (SPIM) Assembler Syntax Comments begin with # Everything from # to the end of the line is ignored Identifiers are a sequence of alphanumeric characters, underbars (_), and dots () that do not begin
More informationece4750-tinyrv-isa.txt
========================================================================== Tiny RISC-V Instruction Set Architecture ========================================================================== # Author :
More informationFormat. 10 multiple choice 8 points each. 1 short answer 20 points. Same basic principals as the midterm
Final Review Format 10 multiple choice 8 points each Make sure to show your work Can write a description to the side as to why you think your answer is correct for possible partial credit 1 short answer
More informationMIPS PROJECT INSTRUCTION SET and FORMAT
ECE 312: Semester Project MIPS PROJECT INSTRUCTION SET FORMAT This is a description of the required MIPS instruction set, their meanings, syntax, semantics, bit encodings. The syntax given for each instruction
More informationCOMPUTER ORGANIZATION AND DESIGN. 5 th Edition. The Hardware/Software Interface. Chapter 4. The Processor
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle
More informationCOMPUTER ORGANIZATION AND DESIGN. 5 th Edition. The Hardware/Software Interface. Chapter 4. The Processor
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition The Processor - Introduction
More informationStored Program Concept. Instructions: Characteristics of Instruction Set. Architecture Specification. Example of multiple operands
Stored Program Concept nstructions: nstructions are bits Programs are stored in memory to be read or written just like data Processor Memory memory for data, programs, compilers, editors, etc. Fetch &
More informationChapter 4. Instruction Execution. Introduction. CPU Overview. Multiplexers. Chapter 4 The Processor 1. The Processor.
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor The Processor - Introduction
More information(2) Part a) Registers (e.g., R0, R1, themselves). other Registers do not exists at any address in the memory map
(14) Question 1. For each of the following components, decide where to place it within the memory map of the microcontroller. Multiple choice select: RAM, ROM, or other. Select other if the component is
More information(Refer Slide Time: 1:40)
Computer Architecture Prof. Anshul Kumar Department of Computer Science and Engineering, Indian Institute of Technology, Delhi Lecture - 3 Instruction Set Architecture - 1 Today I will start discussion
More informationCS3350B Computer Architecture MIPS Instruction Representation
CS3350B Computer Architecture MIPS Instruction Representation Marc Moreno Maza http://www.csd.uwo.ca/~moreno/cs3350_moreno/index.html Department of Computer Science University of Western Ontario, Canada
More information