Computer Organization and Components

Transcription

1 2 Course Structure Computer Organization and Components Module 4: Memory Hierarchy Module 1: Logic Design IS1500, fall 2014 Lecture 4: and F1 DC Ö1 F2 DC Ö2 F7b Lab: dicom F8 Module 2: C and Associate Professor, KTH Royal Institute of Technology Assistant Research ngineer, University of California, Berkeley F3 C Ö1 F4 C Ö2 F5 C Ö4 C Ö3 Module 5: I/O Systems Lab: nios2time F9 C Ö6 F10a C Ö8 Quiz: processor design** F7a L12 Slides version 10 C Ö10 Lab: nios2int Home lab: threads** Module 6: Parallel Processors and Programs F10b Quiz: parallel ** F11 Lab: nios2io C Ö7 C Ö9 Home lab: C Module 3: Processor Design F6 Home Lab: cache C Ö5 **) Optional preparation for the written exam No oral exam I II 3 4 Abstractions in Computer Systems Computer System Agenda Networked Systems and Systems of Systems Application Software Software I Operating System Hardware/Software Interface Microarchitecture Logic and Building Blocks II Digital Hardware Design Digital Circuits Analog Circuits Devices and Physics Analog Design and Physics I II I II

2 5 The (ISA) and its Surrounding The ISA is the interface between hardware and software Instructions: ncoding and semantics Registers Memory 6 Application Software Operating System The microarchitecture is the implementation For instance, both Intel and AMD implement the x86 ISA, but they have different implementations Microarchitecture Microarchitecture design will be discussed in course module 3: Processor design I II 7 NIOSII MIPS We will only briefly compare with ARM and x86, but they are complex ARMv7 I 8 Complex Computers (CISC) Many special purpose instructions xample: x86 Now almost 900 instructions Typically various encoding lengths (x86, 1-15 bytes) Different number of clock cycles, depending on instruction Intel x86 Reduced Computers (RISC) Few, regular instructions Minimize hardware complexity MIPS is a good example (ARM mostly RISC) Typically fixed instruction lengths (eg, 4 bytes for MIPS) Typically one clock cycle per instruction Photo by Robert Harker Photo by Kyro Personal Computers and Personal Mobile Devices II ach ISA has a set of instructions Two main categories: Many other ISAs mbedded Real-Time Systems I Instructions (1/2) CISC vs RISC Different ISAs MIPS and NIOS2 are very similar MIPS is explained in the course book and the focus on lectures NIOSII is used in the labs Warehouse Scale Computers II I II

3 Instructions (2/2) C code, Code, and Code 9 Registers 10 C Code a = b + c; MIPS Code add $s0, $s1, $s2 MIPS Code 0x The compiler maps (if possible) C variables to registers (small fast memory locations) For instance, a to $s0, b to $s1, and c to $s2 (the register names using $ will be explained on the next slide) The assembly code is in human readable form of the machine code ach assembly instruction is mapped to one or more machine code instructions In MIPS (and NIOS2), each instruction is 32 bits MIPS (and NIOS2) have 32 registers Name Number Use $0 0 constant value of 0 $at 1 assembler temporary $v0-$v1 2-3 function return value $a0-$a3 4-7 function arguments $t0-$t temporary (caller-saved) $s0-$s saved variables (callee-saved) $t8-$t temporary (caller-saved) $k0-$k reserved for OS kernal $gp 28 global pointer $sp 29 stack pointer $fp 30 frame pointer $ra 31 function return address NIOS2 registers are called r0 to r31 MIPS and NIOS2 registers are the same for registers 0 to 23 For the rest, there are slight variations See the NIOS2 manual I II I II Memory Big problem if 32 registers set the limit of the number of variables in a program Solution: memory Word address C f a0 b e aa 33 fa a0 1b 33 Byte address Word 3 Word 2 Word 1 Word 0 Memory Has many more data locations than registers Accessing memory is slower than accessing registers Big- vs little-endian xample: Load Word 2 into a register Big-endian if the MSB is 44 Little-endian if the LSB is 44 I The choice of endianness is arbitrary, but creates problems when communicating between processors with different endianness I II I II

4 Stored Programs with Instruction ncoding Formats 13 R-Type Instructions 14 Stored program concept Code is data Code is stored in memory as any other data, enabling general purpose computing Word address C f a0 b e aa 33 fa a0 1b 33 MIPS programs are typically stored from address Word 3 Word 2 Word 1 Word 0 For MIPS and NIOS2, there are 3 instruction formats: R-Type (register-type) I-Type (immediate-type) J-Type (jump-type) Although both MIPS and NIOS2 have R, I, and J formats, the exact bit encodings are different See the NIOS2 manual In MIPS and NIOS2, each instruction requires exactly one word (32 bits) of space MIPS code must be word-aligned (start at addresses 0,4, 8, C etc) X86 does not require word alignment R-Type (register-type) instructions have three register erands: two sources and one destination For R-Type, is always rs 6 bits source 1 xercise: Create the machine code for add $t2, $s1, $s2 Answer with a C code expression rt source rd destination shamt Only used for shift instructions 0 for other instructions funct 6 bits funct determines the specific R-type instruction Answer: Check the MIPS reference card for codes (10 << 11) (17 << 21) (18 << 16) 32 I II I II I-Type Instructions 15 J-Type Instructions 16 I-Type (immediate-type) instructions have two register erands and one immediate erand J-Type (jump-type) instructions has one 26- bit address erand rs rt imm addr 6 bits 16 bits 6 bits 26 bits Opcode source 1 destination xercise: a) Create the machine code for addi $t0, $s0, -7 Answer with a C code expression b) Same as above, but use 7 and encode using two s complement for some inst (lw, addi), source 2 for others (sw) Immediate value (also negative) Answer: a) (8 << 26) (16<<21) (8<<16) (-7 & 0xffff) b) (8 << 26) (16<<21) (8<<16) (((7 ^ -1)++) & 0xffff) Opcode Address erand I II I II

5 17 Arithmetic/Logical Instructions 18 II MIPS Logical Instructions and $s0, $s1, $s2 or $s0, $s1, $s2 xor $s0, $s1, $s2 nor $s0, $s1, $s2 Instructions AND, OR, XOR, and NOT OR There is no not instruction How can we do not $s1 and store it in $t0? nor $t0, $s1, $0 andi $s0, $s1, 0xAB41 ori $s0, $s1, 0xFF01 xori $s0, $s1, 0x78 MIPS Logical Instructions sll $t0, $s0, 3 srl $t0, $s0, 29 sra $t0, $s0, 29 Instructions AND immediate, OR immediate, and XOR immediate Shift left logical (same as C erator <<) Shift right logical (same as C erator >>) Shift right arithmetic Shifts in the sign bit as the most significant bit Dividing signed numbers I II I II Constants Values 19 Conditional Branches (1/3) beq and bne 20 How can we assign a register a constant value? Max 16-bit (recall the I-Type Form) addi $s0, $0, 2342 How can we give a register a 32-bit constant? Hint: There is an instruction load upper immediate, lui $t, 0xff12 int a = 0x6af022e7 that loads the higher 16 bits to the immediate value, and sets the lower to 0 lui $s0,0x6af0 ori $s0,$s0,0x22e7 Requires 2 instructions Branch if equal (beq) branches if two erands have equal values addi $s0, $0, 4 xori $s1, $s0, 1 sll $t0, $s1, 1 beq $t0, $s0, foo add $s1, $s1, $s0 Foo: add $s5, $s1, $0 What is the value of $s5? Stand for 9, sleep for 10 Answer: 9 Branch if not equal (bne) branches if two erands do not have equal values Set $s0 to 4 XOR immediate results in $s1=5 Shift logic left results in that $t0 is 10 Hence, $t0 and $s0 are not equal, so the branch is not taken and add is executed This results in that $s1 is 9 There is no MOV instruction in MIPS or NIOS, but addi can be used for this (as it is done here) Note: There is a pseudoinstruction called mov (in NIOS) and move (for MIPS) It is implemented using add I II I II

6 21 Conditional Branches (2/3) if-statement, if/else-statement if(i!=j) f = i; else f = i + j; f = f - j if(i==j) f = i; f = f - j How can the C code be translated to MIPS code? Assume mapping, i to $s0, j to $s1, and f to $t0 bne $s0, $s1, L1 add $t0, $s0, $0 L1: sub $t0, $t0, $s1 Note: Tests the posite int sum = 0; for(i=1; i < 101; i = i * 2) sum = sum + i; beq add j else: add L1: sub Help: Instruction set less than (slt) slt $t0,$s0,$s1 sets $t0 to 1 if $s0 is less than $s1, else $t0 sets to 0 addi $s1, $0, addi $s0, $0, addi $t0, $0, lo: slt $t1, $s0, Translated to MIPS code using mapping: i to $s0, sum to $s1 Translate to MIPS code, using previous mapping 22 Conditional Branches (3/3) for-los 0 # sum = 0 1 # i = # $t0 = 101 $t0 # # beq $t1, $0, done # add $s1, $s1, $s0 # sll $s0, $s0, 1 # j lo done: $s0, $s1, else $t0, $s0, $0 L1 $t0, $s0, $s1 if(i<101) $t1=1 else $t1=0 if $t1 == 0, branch sum = sum + i i = i * 2 $t0, $t0, $s1 xample from Harris & Harris, 2013, page 320 I II I II 23 Arrays and Memory Access 24 Summary int ar[5]; ar[0] = ar[0] * 8; ar[1] = ar[1] * 8; Arrays are defined and accessed using [] in C Translated to MIPS code Let the Array address be 0x lui $s0, 0x1000 ori $s0, $s0,0x7000 lw loads a word from the effective address $s0 + 0 The effective address is sum of the base address ($s0) and offset (4 in the second case) lw $t1, 0($s0) sll $t1, $t1, 3 sw $t1, 0($s0) sw stores back a word using the computed effective address lw $t1, 4($s0) sll $t1, $t1, 3 sw $t1, 4($s0) Some key take away points: An instruction set architecture (ISA) defines the software/ hardware interface, whereas a microarchitecture implements an ISA There are many different ISAs, but some of the major ones are x86, ARMv7, and MIPS MIPS/NIOS2 main instruction formats are R-Type, IType, and J-Type Note the byte address Thanks for listening! xample from Harris & Harris, 2013, page 321 I II I II