TABLE 9-1. Symbolic Convention for Addressing Modes. Register indirect LDA (R1) ACC M[ R1] Refers to Figure 9-4. Addressing mode. Symbolic convention
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1 T-236 Symbolic Convention for Addressing Modes TABLE 9-1 Symbolic Convention for Addressing Modes Refers to Figure 9-4 Addressing mode Symbolic convention Register transfer Effective address Contents of ACC Direct LDA ADRS ACC M[ ADRS] Immediate LDA #NBR ACC NBR Indirect LDA [ADRS] ACC M[ M[ ADRS] ] Relative LDA $ADRS ACC M[ ADRS PC] Index LDA ADRS (R1) ACC M[ ADRS R1] Register LDA R1 ACC R1 400 Register indirect LDA (R1) ACC M[ R1] Mano & Kime Upper Saddle River, New Jersey 07458
2 T-237 Typical Data Transfer Instructions TABLE 9-2 Typical Data Transfer Instructions Name Load Store Move Exchange Push Pop Input Output Mnemonic LD ST MOVE XCH PUSH POP IN OUT
3 T-238 Typical Arithmetic Instructions TABLE 9-3 Typical Arithmetic Instructions Name Increment Decrement Add Subtract Multiply Divide Add with carry Subtract with borrow Subtract reverse Negate Mnemonic INC DEC ADD SUB MUL DIV ADDC SUBB SUBR NEG
4 T-239 Typical Logical and Bit Manipulation Instructions TABLE 9-4 Typical Logical and Bit Manipulation Instructions Name Clear Set Complement AND OR Exclusive-OR Clear carry Set carry Complement carry Mnemonic CLR SET NOT AND OR XOR CLRC SETC COMC
5 T-240 Typical Shift Instructions TABLE 9-5 Typical Shift Instructions Name Logical shift right Logical shift left Arithmetic shift right Arithmetic shift left Rotate right Rotate left Rotate right with carry Rotate left with carry Mnemonic SHR SHL SHRA SHLA ROR ROL RORC ROLC
6 T-241 Evaluating Biased Exponents TABLE 9-6 Evaluating Biased Exponents Exponent E in decimal Biased exponent e E 127 Decimal Binary
7 T-242 Typical Program Control Instructions TABLE 9-7 Typical Program Control Instructions Name Branch Jump Skip next instruction Call procedure Return from procedure Compare (by subtraction) Test (by ANDing) Mnemonic BR JMP SKP CALL RET CMP TEST
8 T-243 Conditional Branch Instructions Relating to Status Bits in the PSR TABLE 9-8 Conditional Branch Instructions Relating to Status Bits in the PSR Branch condition Mnemonic Test condition Branch if zero BZ Z 1 Branch if not zero BNZ Z 0 Branch if carry BC C 1 Branch if no carry BNC C 0 Branch if minus BN 1 Branch if plus BNN N 0 Branch if overflow BV V 1 Branch if no overflow BNV V 0
9 T-244 Conditional Branch Instructions for Unsigned Numbers TABLE 9-9 Conditional Branch Instructions for Unsigned Numbers Branch condition Mnemonic Condition Status bits* Branch if higher BH A B C Z 0 Branch if higher or equal BHE A B C 0 Branch if lower BL A B C 1 Branch if lower or equal BLE A B C Z 1 Branch if equal BE A B Z 1 Branch if not equal BNE A B Z 0 *Note that C here is a borrow bit.
10 T-245 Conditional Branch Instructions for Signed Numbers TABLE 9-10 Conditional Branch Instructions for Signed Numbers Branch condition Mnemonic Condition Status bits Branch if greater Branch if greater or equal Branch if less Branch if less or equal BG BGE BL BLE A B ( N V) Z 0 A B N V 0 A B N V 1 A B ( N V) + Z 1 Mano & Kime Upper Saddle River, New Jersey 07458
11 T-246 Example Demonstrating Direct Addressing for a Data Transfer Instruction Memory 250 Opcode Mode PC = ADRS 252 Next instruction ACC Opcode: Mode: ADRS: Operation: Load ACC Direct address 500 ACC Program 800 Data
12 T-247 Example Demonstrating Direct Addressing in a Branch Instruction Memory 300 Opcode Mode PC = ADRS 302 Next instruction ACC Program Opcode: Mode: ADRS: Operation: Branch if ACC = 0 Direct address 500 PC 500 if ACC = 0 PC 302 if ACC Instruction Program
13 T-248 Numerical Example for Addressing Modes PC = Memory Opcode Mode ADRS or NBR = 500 R1 = Next instruction ACC Opcode: Load to ACC
14 T-249 Memory Stack Memory SP = 101 R1 C B A Address
15 T-250 External Interrupt Configuration 1 External interrupts Central processing unit (CPU) End of execution of instruction EI INTACK Enable-interrupt flip-flop Interrupt acknowledge Interrupt vector address IVAD PC To memory stack Mano & Kime Upper Saddle River, New Jersey 07458
10-1 C D Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e
10-1 C D E A B 10-2 A B A B C (A B) C D A A B (A B) C E D (A B) C D E (A B) C + D E (A B) C 10-3 Opcode Mode Address or operand 10-4 Memory 250 Opcode Mode PC = 250 251 ADRS 252 Next instruction ACC Opcode:
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