Lecture 6: Microprogrammed Multi Cycle Implementation. James C. Hoe Department of ECE Carnegie Mellon University

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1 8 447 Lectre 6: icroprogrammed lti Cycle Implementation James C. Hoe Department of ECE Carnegie ellon University S8 L06 S, James C. Hoe, CU/ECE/CALC, 208

2 Yor goal today Hosekeeping nderstand why VAX was possible and reasonable Notices Lab, Part B, de this week HW,de Wed **New Office Hors: ~2 and F :30~2:30** ings P&H Appendi C Start reading the rest of P&H Ch S8 L06 S2, James C. Hoe, CU/ECE/CALC, 208

3 Single Cycle Datapath (IPS) Instrction [25 0] Shift Jmp address [3 0] left PCSrc =Jmp 0 4 Add PC+4 [3 28] Instrction [3 26] Control RegDst Jmp Branch em emtoreg ALUOp emwrite ALUSrc RegWrite Shift left 2 Add ALU reslt 0 PCSrc 2 =Br Taken PC address Instrction [3 0] Instrction memory Instrction [25 2] Instrction [20 6] Instrction [5 ] 0 register data register 2 Registers Write data 2 register Write data 0 bcond Zero ALU ALU reslt Address Write data Data memory data 0 Instrction [5 0] 6 Sign 32 etend ALU control ALU operation Instrction [5 0] S8 L06 S3, James C. Hoe, CU/ECE/CALC, 208 [Based on original figre from P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]

4 Worst Case Critical Path Instrction [25 0] Shift Jmp address [3 0] left PCSrc =Jmp 0 4 Add PC+4 [3 28] Instrction [3 26] Control RegDst Jmp Branch em emtoreg ALUOp emwrite ALUSrc RegWrite Shift left 2 Add ALU reslt 0 PCSrc 2 =Br Taken PC address Instrction [3 0] Instrction memory Instrction [25 2] Instrction [20 6] Instrction [5 ] 0 register data register 2 Registers Write data 2 register Write data 0 bcond Zero ALU ALU reslt Address Write data Data memory data 0 Instrction [5 0] 6 Sign 32 etend ALU control ALU operation Instrction [5 0] S8 L06 S4, James C. Hoe, CU/ECE/CALC, 208 [Based on original figre from P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]

5 Single Cycle Datapath Analysis Assme (nmbers from P&H) memory nits (read or write): 200 ps ALU and adders: 00 ps register file (read or write): 50 ps other combinational logic: 0 ps steps IF ID EX E WB resorces mem RF ALU mem RF Delay R type I type LW SW B/JALR JAL S8 L06 S5, James C. Hoe, CU/ECE/CALC, 208

6 Single Cycle Implementations Good match for the seqential and atomic semantics of ISAs instantiate programmer visible state one for one map instrctions to combinational net state logic Bt, contrived and inefficient. all instrctions rn as slow as slowest instrction 2. mst provide worst case combinational resorce in parallel as reqired by any one instrction 3. what abot CISC ISAs? polyf? Not the fastest, cheapest or even the simplest way S8 L06 S6, James C. Hoe, CU/ECE/CALC, 208

7 lti cycle Implementation: Ver.0 Each instrction type take only as mch time as needed rn a 50 psec clock each instrction type take as many 50 psec clock cycles as needed Add asterenable signal so architectral state ignores clock edges ntil after enogh time an instrction s effect is still prely combinational from state to state all other control signal naffected S8 L06 S7, James C. Hoe, CU/ECE/CALC, 208

8 lti Cycle Datapath: Ver.0 Instrction [25 0] Shift Jmp address [3 0] left PCSrc =Jmp 0 4 Add PC+4 [3 28] Instrction [3 26] Control RegDst Jmp Branch em emtoreg ALUOp emwrite ALUSrc RegWrite Shift left 2 Add ALU reslt 0 PCSrc 2 =Br Taken PC address Instrction [3 0] Instrction memory Instrction [25 2] Instrction [20 6] Instrction [5 ] 0 register data register 2 Registers Write data 2 register Write data 0 bcond Zero ALU ALU reslt Address Write data Data memory data 0 Instrction [5 0] 6 Sign 32 etend ALU control asteren Instrction [5 0] S8 L06 S8, James C. Hoe, CU/ECE/CALC, 208 [Based on original figre from P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]

9 Seqential Control: Ver.0 IF IF 2 IF 3 IF 4 ID JAL EX WB B or JAL or JALR / asteren= I type or R type EX 2 LW or SW LW SW / asteren= E 4 E 3 E 2 E S8 L06 S9, James C. Hoe, CU/ECE/CALC, 208

10 icroseqencer: Ver.0 RO as a combinational logic lookp table literally holds the trth table 2 n rows Combinational control logic address n / inpt Inpts Otpts m asteren ** RO size grows as O(2 n ) as the nmber of inpts Datapath control otpts ** RO size grows as O(m) as the nmber of otpts Net state Inpts from instrction register opcode field State register S8 L06 S0, James C. Hoe, CU/ECE/CALC, 208 [Based on original figre from P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]

11 8 447 S8 L06 S, James C. Hoe, CU/ECE/CALC, 208 icrocoding: Ver.0 (note: this is only abot conting clock ticks) state label cntrl flow conditional targets R/I type LW SW B JALR JAL IF net IF 2 net IF 3 net IF 4 goto ID ID ID ID ID EX ID net EX net EX 2 goto WB E E IF IF IF E net E 2 net E 3 net E 4 goto WB IF WB goto IF IF CPI A systematic approach to FS seqencing/control

12 icrocontroller/icroseqencer A stripped down processor for seqencing and control control states are like PC PC indeed into a program RO to select an instrction well formed control flow spport (branch, jmp) fields in the instrction maps to control signals Adder icrocode storage Inpt Otpts icroprogram conter Seqencing control Datapath control otpts Very elaborate controllers have been bilt S8 L06 S2, James C. Hoe, CU/ECE/CALC, 208 Address select logic Inpts from instrction register opcode field [Based on original figre from P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]

13 Performance Analysis Iron Law: wall clock time = (inst/program) (cyc/inst) (time/cyc) For same ISA, inst/program is the same; okay to compare IPS = IPC f clk in Hz freqency in Hz million instrctions per second instrctions per cycle S8 L06 S3, James C. Hoe, CU/ECE/CALC, 208

14 Performance Analysis Single Cycle Implementation,667Hz = 667 IPS lti Cycle Implementation IPC avg 20,000 Hz = 278 IPS what is IPC average? Assme: 25% LW, 5% SW, 40% ALU, 3.3% Branch, 6.7% Jmps [Agerwala and Cocke, 987] weighted arithmetic mean of CPI 9.8 weighted harmonic mean of IPC 0.09 weighted arithmetic mean of IPC S8 L06 S4, James C. Hoe, CU/ECE/CALC, 208 IPS = IPC f clk

15 Redcing Datapath by Resorce Rese How to rese same adder for two additions in one instrction Add 4 PC address Instrction memory Instrction register register 2 Registers Write register Write data data data 2 3 ALU operatio Zero ALU ALU reslt RegWrite 6 Sign 32 etend ALUSrc isitype Single cycle resed same adder for different instrctions S8 L06 S5, James C. Hoe, CU/ECE/CALC, 208 [Based on original figre from P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]

16 Redcing Datapath by Seqential Rese Add PC address Instrction memory 4 Instrction IR register register 2 Registers Write register Write data data data 2 RegWrite 4 3 ALU control Zero ALU ALU reslt to IR or not to IR? S8 L06 S6, James C. Hoe, CU/ECE/CALC, 208 [Based on original figre from P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]

17 Removing Redndancies rd rs rs2 immed Latch Enables: PC, IR, DR, A, B, ALUOt, RegWr, emwr Steering: ALUSrc{RF,PC}, ALUSrc2{RF, immed}, AddrSrc{PC, ALUOt}, RFDataSrc{ALUOt, DR} Cold also redce down to a single register read write port! S8 L06 S7, James C. Hoe, CU/ECE/CALC, 208 [Based on original figre from P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]

18 Synchronos Register Transfers Synchronos state with latch enables PC, IR, RF, E, A, B, ALUOt, DR One can enmerate all possible register transfers For eample starting from PC IR E[ PC ] DR E[ PC ] PC PC 4 PC PC B PC PC immediate(ir) ALUOt PC 4 ALUOt PC immediate(ir) ALUOt PC B S8 L06 S8, James C. Hoe, CU/ECE/CALC, 208

19 Usefl Register Transfers (by dest) S8 L06 S9, James C. Hoe, CU/ECE/CALC, 208 PC PC + 4 PC PC + immediate SB type,u type (IR) PC A+ immediate SB type (IR) IR E[ PC ] A RF[ rs(ir) ] B RF[ rs2(ir) ] ALUOt A + B ALUOt A + immediate I type,s type (IR) ALUOt PC + 4 DR E[ ALUOt ] E[ ALUOt ] B RF[ rd(ir) ] ALUOt, RF[ rd(ir) ] DR

20 RT Seqencing: R Type ALU IF IR E[ PC ] ID A RF[ rs(ir) ] B RF[ rs2(ir) ] EX ALUOt A + B E if E[PC] == ADD rd rs rs2 GPR[rd] GPR[rs] + GPR[rs2] PC PC S8 L06 S20, James C. Hoe, CU/ECE/CALC, 208 WB RF[ rd(ir) ] ALUOt PC PC+4

21 RT Datapath Conflicts PC PC + 4 RF[ rd(ir) ] ALUOt, PC PC + imm(ir) RF[rd(IR) ] DR PC A + imm(ir) B RF[rs(IR) ] A RF[rs2(IR) ] IR E[ PC ] ALUOt A + imm(ir) ALUOt PC + 4 ALUOt A + B E[ ALUOt ] B DR E[ ALUOt ] S8 L06 S2, James C. Hoe, CU/ECE/CALC, 208 Can tilize each resorce only once per control step (cycle)

22 RT Seqencing: R Type ALU IF IR E[ PC ] ID A RF[ rs(ir) ] B RF[ rs2(ir) ] EX ALUOt A + B E WB RF[ rd(ir) ] ALUOt PC PC+4 step step 2 step 3 step S8 L06 S22, James C. Hoe, CU/ECE/CALC, 208

23 if E[PC]==LW rd offset(base) EA = sign etend(offset) + GPR[base] GPR[rd] E[ EA ] PC PC S8 L06 S23, James C. Hoe, CU/ECE/CALC, 208 RT Seqencing: LW IF IR E[ PC ] ID A RF[ rs(ir) ] B RF[ rs2(ir) ] EX ALUOt A + imm I type (IR) E DR E[ ALUOt ] WB RF[ rd(ir) ] DR PC PC+4

24 Combined RT Seqencing common steps opcode dependent steps R Type LW SW Branch Jmp start: IR E[ PC ] net A RF[ rs(ir) ] B RF[ rs2(ir) ] ALUOt PC+imm(IR) case opcode PC PC PC + 4 A+B A+imm(IR) A+imm(IR) PC+imm(IR) ALUOt ALUOt ALUOt start net net net net RF[rd(IR)] [ALUOt] DR ALUOt B cond?( A, B ) [ALUOt] PC PC+4 start PC PC+4 start start net if not cond RF[rd(IR)] DR PC ALUOt PC PC+4 start start RTs in each state corresponds to some setting of the control signals S8 L06 S24, James C. Hoe, CU/ECE/CALC, 208

25 Horizontal icrocode icrocode storage Inpt Otpts n bit PC inpt ALUSrcA IorD Datapath IRWrite control otpts PCWrite PCWriteCond. k bit control otpt Adder icroprogram conter Seqencing control Address select logic Inpts from instrction register opcode field [Based on original figre from P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.] S8 L06 S25, James C. Hoe, CU/ECE/CALC, 208 Control Store: 2 n k bit (not inclding seqencing)

26 Vertical icrocode icrocode storage Inpt Otpts n bit PC inpt bit signal means do this RT PC PC+4 PC ALUOt Datapath PC PC[ 3:28 ],IR[ 25:0 ],2 b00 control IR E[ PC ] otpts A RF[ IR[ 25:2 ] ] B RF[ IR[ 20:6 ] ].. m bit inpt Adder icroprogram conter Seqencing control RO Address select logic k bit otpt [Based on original figre from P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.] Inpts from instrction register opcode field S8 L06 S26, James C. Hoe, CU/ECE/CALC, 208 ALUSrcA IorD IRWrite PCWrite PCWriteCond.

27 icrocoding for CISC Can we etend controller and datapath? to spport a new instrction to spport a comple instrction, e.g. polyf Yes, ws very simple datapath do very complicated things easily bt with a slowdown if I can seqence an arbitrary RISC instrction then I can seqence an arbitrary RISC program as a program seqence will need some ISA state (e.g. loop conters) for more elaborate programs more elaborate ISA featres also make life easier S8 L06 S27, James C. Hoe, CU/ECE/CALC, 208

28 Single Bs icroarchitectre [8086 Family User s anal] S8 L06 S28, James C. Hoe, CU/ECE/CALC, 208

29 High Performance CISC Today High perf 86s translate CISC inst s to RISC OPs Pentim Pro decoding eample: 6 bytes of 86 instrctions op RO: play back a OP seqence for more complicated instrctions primary decoder decode st 86 into ~4 OPs byte offset decoder decoder decode p to 2 more simple 86 that each map to OP S8 L06 S29, James C. Hoe, CU/ECE/CALC, 208 OP stream eectes on a RISC internal machine