CSE 2021 Computer Organization. Hugh Chesser, CSEB 1012U W10-M

Transcription

1 CSE 22 Computer Organization Hugh Chesser, CSEB 2U

2 Agenda Topics:. ultiple cycle implementation - complete Patterson: Appendix C, D 2

3 Breaking the Execution into Clock Cycles Execution of each instruction is broken into a series of steps Each step is balanced to do almost equal amount of work Each step takes one clock cycle Each step contains at the most ALU operation, or register file access, or memory access Operations listed in step occurs in parallel in clock cycle Different steps occur in different clock cycles Different steps are:. IF: fetch step 2. ID: decode and register fetch step 3. EX: Execution, memory address computation, or branch completion step 4. E: emory access of R-type instruction completion step 5. WB: Write back completion step 3

4 ulticycle Implementation: Control Units added PC Address Write data emory emdata [3-26] [25 2] [2 6] [5 ] register [5 ] PCWriteCond PCWrite IorD emread emwrite emtoreg IRWrite [25 ] [5 ] Outputs Control Op [5 ] PCSource ALUOp ALUSrcB ALUSrcA RegWrite RegDst Read register Read register 2 Registers Write register Write data Read data Read data 2 A B Shift 28 left 2 PC [3-28] Zero ALU ALU result Jump address [3-] ALUOut 2 emory data register 6 Sign extend 32 Shift left 2 ALU control [5 ] 4

5 ulticycle Implementation 5 Steps ulticycle implementation unwound to show datapath in each step 5

6 Summary of Steps used in different s Action for Step Name R-type emory Reference Branch Jump IF - fetch ID - decode / Register fetch IR = emory[pc]; PC = PC + 4; A = Reg[IR[25-2]]; B = Reg[IR[2-6]]; ALUOut = PC + (sign-extend(ir[5-])<<2); EX R-type Execution / address comp. / Branch /Jump ALUOut=A op B ALUOut = A + signextend(ir[5-]) if(a == B) then PC = ALUOut; PC = PC[3-28] (IR[25-)<<2); E - emory Access / R-type Completion Reg[IR[5-]] = ALUOut; lw: DR = emory[aluout] or sw: emory[aluout] = B WB - emory Read Completion lw: Reg[IR[2-6]]=DR; 6

7 ultipath Datapath Implementation: Control Recall that design of single cycle datapath was based on a combinational circuit Design of multicycle datapath is more complicated. s are executed in a series of steps 2. Each step must occur in a sequence 3. Control of multicycle must specify both the control signals and the next step The control of a multicycle datapath is based on a sequential circuit referred to as a finite state machine State A finite state diagram for a 2-bit counter Each state specifies a set of outputs By default, unspecified outputs are assumed disabled The number of the arrows identify inputs State 3 State State 2 7

8 Finite State achine? See Appendix C A sequential logic function which has a state and inputs the logic function determines the next state and outputs oore machine outputs depend on just the current state ealy machine outputs depend on current state and inputs Book uses oore machine description 8

9 Finite State achine Control of ulticycle Datapath () Start fetch/decode and register fetch (Figure 4.36) emory access instructions (Figure 4.2) R-type instructions (Figure 4.9) Branch instruction (Figure 4.2) Jump instruction (Figure 4.24) High-Level View 9

10 Finite State achine Control of ulticycle Datapath (2) Start (Op = 'LW') or (Op = 'SW') fetch emread ALUSrcA = IorD = IRWrite ALUSrcB = ALUOp = PCWrite PCSource = (Op = R-type) decode/ Register fetch (Op = 'BEQ') ALUSrcA = ALUSrcB = ALUOp = (Op = 'JP') emory reference FS R-type FS Branch FS Jump FS Fig. D.3.: Steps and 2: Fetch and Decode s

11 Finite State achine Control of ulticycle Datapath (3) 2 From state ALUSrcA = ALUSrcB = ALUOp = (Op = 'LW') or (Op = 'SW') emory address computation 3 (Op = 'LW') emory access (Op = 'SW') 5 emory access Finite State achine for emory Reference s emread IorD = emwrite IorD = 4 Write-back step RegWrite emtoreg = RegDst = To state

12 Finite State achine Control of ulticycle Datapath (4) From state (Op = R-type) 6 Execution ALUSrcA = ALUSrcB = ALUOp = 7 R-type completion RegDst = RegWrite emtoreg = To state Finite State achines for R-type s 2

13 Finite State achine Control of ulticycle Datapath (5) 8 From state (Op = 'BEQ') ALUSrcA = ALUSrcB = ALUOp = PCWriteCond PCSource = Branch completion 9 From state (Op = 'J') PCWrite PCSource = Jump completion To state To state Finite State achine for Branch Finite State achine for Jump 3

14 2 emory address com puta tion ALU S rca = ALU SrcB = ALU O p = Start (Op = 'LW ') or (Op = 'SW ') 6 emread = ALU SrcA = IorD = IR W rite ALU S rcb = ALU O p = PC W rite = P C S ource = Exe cution ALU S rca = ALU S rcb = ALU O p = fe tch 8 (Op = R-type) Bra nch com pletion ALU S rca = ALU SrcB = ALU O p = P C W ritecond = P C S ource = (Op = 'BEQ') de code/ re gister fetch 9 ALU S rca = ALU S rcb = ALU O p = (Op='J') Jump comple tion PCWrite = PC Source = 3 (Op='LW') e mory a ccess (Op = 'SW') 5 emory access 7 R -type com ple tion emread = IorD = emwrite = IorD = R e gd st = RegWrite = emtor eg = 4 W rite -ba ck step R egd st = R egw rite = em tor eg = 4

15 Finite State achine Control of ulticycle Datapath (5) PCWrite PCWriteCond IorD emread emwrite Control logic Outputs IRWrite emtoreg PCSource ALUOp ALUSrcB ALUSrcA RegWrite RegDst Inputs NS3 NS2 NS NS Op5 Op4 Op3 Op2 Op Op S3 S2 S S register opcode field State register 5

16 Control Logic Truth Table Note that control outputs depend only on current state (Op column is blank for all output rows) Next state depends on current state and inputs (opcode from instruction) 6

17 ulticycle Implementation: Control Units added PC Address Write data emory emdata [3-26] [25 2] [2 6] [5 ] register [5 ] PCWriteCond PCWrite IorD emread emwrite emtoreg IRWrite [25 ] [5 ] Outputs Control Op [5 ] PCSource ALUOp ALUSrcB ALUSrcA RegWrite RegDst Read register Read register 2 Registers Write register Write data Read data Read data 2 A B Shift 28 left 2 PC [3-28] Zero ALU ALU result Jump address [3-] ALUOut 2 emory data register 6 Sign extend 32 Shift left 2 ALU control [5 ] 7