Computer Organization & Design The Hardware/Software Interface Chapter 5 The processor : Datapath and control

Transcription

1 Computer Organization & Design The Hardware/Software Interface Chapter 5 The processor : Datapath and control Qing-song Shi zjsqs@zju.edu.cn

2 Chapter 5 The processor : Datapath and control

3 Chapter Five The processor : Datapath and control 5. Introduction 5.2 Logic Design Conventions (skip) 5.3 Building a datapath 5.4 A Simple Implementation Scheme 5.5 A ulticycle Implementation 5.5 icroprogramming 5.6 Exception

4 What is the IPS? icroprocessor without Interlocked Pipeline Stages

5 5. Introduction We ll look at an implementation of the IPS Simplified to contain only: memory-reference instructions: lw, sw arithmetic-logical instructions: add, sub, and, or, slt What are steps? control flow instructions: beq, j How many FUN.? An Overview of the implementation For every insruction, the first two step are identical. Fetch the instruction from the memory 2. Decode and read the registers Next steps depend on the instruction class emory-refrernce Arithmetic-logical branches

6 Computer Organization Control unit CPU Path: multiplexors 计算机 emory Datapath ALU Registers I/O interface

7 An abstract view of the implementation of IPS 4 Add PC address memory register register 2 Write register Write data RegWrite Registers data data 2 ALUSrc u x 3 ALU operation Zero ALU ALU result Address Write data emwrite data Data memory emtoreg u x 6 Sign 32 extend em

8 Chapter Five The processor : Datapath and control 5. Introduction 5.2 Logic Design Conventions (skip) 5.3 Building a datapath 5.4 A Simple Implementation Scheme 5.5 A ulticycle Implementation 5.5 icroprogramming 5.6 Exception

9 State Elements Unclocked vs. Clocked Clocks used in synchronous logic when should an element that contains state be updated? falling edge cycle time rising edge

10 Our Implementation An edge triggered methodology Typical execution: read contents of some state elements, send values through some combinational logic write results to one or more state elements State element Com binational logic State element 2 Clock cycle

11 D-Latch for state D C D S R Q(t + ) X X X hold C Q=:reset Q=:reset S R Q Q C D Q(t + ) X hold Q=:reset Q=:set D-Latch FUN. table D Q C Q D-Latch symbol

12 Chapter Five The processor : Datapath and control 5. Introduction 5.2 Logic Design Conventions (skip) 5.3 Building a datapath 5.4 A Simple Implementation Scheme 5.5 A ulticycle Implementation 5.5 icroprogramming 5.6 Exception

13 The datapath there are Name Example Comments 32 register 3 Word Addresses signals line $s-$s7,$t-$t9, $zero,$a-$a3, $v-$v emory[], emory[4],, enory[ ] Fast locations for data. In IPS, data must be in registers to perform arithmetic. IPS register $zero always equals. $gp(28) is the global pointer, $sp(29) is the stack pointer, $fp(3) is the frame pointer, and $ra(3) is the return address. Accessed only by data transfer instructions. IPS uses byte addresses, so sequential word addresses differ by 4. emory holds data structures, arrays, and spilled registers, such as those saved on procedure calls. Name Register no. Usage Preserved on call $zero The constant value n,.a. $v-$v 2-3 Values for results and expression evaluation no $a-$a3 4-7 Arguments no $t-$t7 8-5 Temporaries no $s-$s Saved yes $t8-$t ore temporaries no $gp 28 Global pointer yes $sp 29 Stack pointer yes $fp 3 Framer pointer yes $ra 3 Return address yes

14 ALU OP for IPS machine language Name Format Example Comment add R add $s, $s2, $s3 sub R sub $s, $s2, $s3 lw I lw $s, ($s2) sw I sw $s, ($s2) and R and $s, $s2, $s3 or R or $s, $s2, $s3 nor R nor $s, $s2, $s3 addi I addi $s, $s2, ori I ori $s, $s2, beq I beq $s, $s2, bne I bne $s, $s2, slt R slt $s, $s2,$s3 j J 2 25 j (see section 2.9) jr R 3 8 j Sra jal J 3 25 jar (see section 2.9) Field size 6bits 5bits 5bits 5bits 5bits 6bits All IPS instruction 32 bits R-format R op rs rt rd shamt funct Arithmetic instruction format i-format I op rs rt address Data transfer,branch format

15 execution in IPS Fetch : Take instructions from the instruction memory odify PC to point the next instruction decoding & Operand: Will be translated into machine control command ing Register Operands, whether or not to use Executive Control: Control the implementation of the corresponding ALU operation emory access: Write or data from memory Only LW/SW Write results to register: If it is R-type instructions, ALU results are written to Rd If it is I-type instructions, Results are written to Rt

16 fetching three elements How to connect? Who? address memory PC Add Sum memory Program counter Adder

17 fetching unit Add 4 PC address memory CPU

18 ore Implementation Details Abstract / Simplified View: Data Register # PC Address Registers ALU memory Register # Register # Address Data memory Data

19 Register File--Built using D flip-flops Reg. address Data output Output from the register 5 bits 5 bits 5 bits 32 bits register number register number 2 Register file Write register Write data Write data data 2 32 bits 32 bits Reg. address register number register number 2 Register Register Register n Register n u x u x data data 2

20 Register File Write Written to the register Write Write signals rd or rt 5 bits Register number n-to- decoder n n C Register D C Register D Reg. address 32 bits Register data C Register n D C Register n D

21 Register files Foundation element of Computer(Part of Datapath ) Aggregation of many Registers Register address Control signals: /Write

22 Description: 32 32bits Register files odule regs(clk, rst,reg_rd_addr_a, reg_rt_addr_b, reg_wt_addr, wdata, we, rdata_a, rdata_b); input clk, rst, we; input [4:] reg_rd_addr_a, reg_rt_addr_b, reg_wt_addr; input [3:] wdata; output [3:] rdata_a, rdata_b; reg [3:] register [:3]; // r - r3 integer i; assign rdata_a = (reg_rd_addr_a == )? : register[reg_rd_addr_a]; // read assign rdata_b = (reg_rt_addr_b == )? : register[reg_rt_addr_b]; // read clk or posedge rst) begin if (rst==) begin // reset for (i=; i<32; i=i+) register[i] <= ; end else begin end endmodule if ((reg_wt_addr!= ) && (we == )) register[reg_wt_addr] <= wdata; end // write

23 Path Built using ultiplexer R-type instruction Datapath I-type instruction Datapath For ALU For memory For branch J-type instruction Datapath For Jump First, Look at the data flow within instruction execution

24 R type & Data stream op(6) rs(5) rt(5) rd(5) shamt func(6) bit 2-25 bit 6-2 bit -5 rs rt rd control reg. address data reg. address2 Registers RegWrite Write reg. address data2 Write data ALU operation 32bits data 3 ALU Zero ALU result Bnegate op function and Or Add Sub Slt

25 I type & Data stream op(6) rs(5) rt(5) Immediate data bit 2-25 bit 6-2 rs rt rt control reg. address data reg. address2 Registers RegWrite Write reg. address data2 Write data bit -5 6 lw $t, 2($s2) Sign extend 32 3 ALU Zero ALU result 32bits data Sw $t, 2($s2) ALU operation address data Data emory Write data enwrite en if $s2=,it will load word in element number 2 to $t

26 I type & Data stream of beq op(6) rs(5) rt(5) offset bit 2-25 bit 6-2 PC+4 from instructiondatapath rs rt reg. address data reg. address2 Registers RegWrite Write reg. address data2 Write data bit -5 6 Sign extend 32 Shift left 2 3 ALU ADD ALU operation Zero ALU result To PC

27 Combine the datapath R & I type op(6) rs(5) rt(5) Immediate data PC bit 2-25 bit -5 bit 6-2 bit -5 address emory UX rs rt rd 6 4 reg. address data reg. address2 Registers RegWrite Write reg. address data2 Write data Sign extend ADD 32 UX Shift left 2 3 ALU ADD Zero ALU result 32bits data ALU operation address data Data emory Write data en UX To PC enwrite UX

28 Combine the datapath R & I type address PC emory bit -5 bit 2-25 bit 6-2 UX bit RegWrite address data address2 Registers Write address data2 Write data Sign extend ADD 32 UX Shift left 2 ALU 3 ALU operation Zero ALU result ADD 32bits data address enwrite data Data emory Write data en UX UX

29 Combine the datapath R & I type address PC emory I-beq4 I-SW RI-LW bit -5 bit 2-25 bit 6-2 UX bit -5 6 RegWrite address data address2 Registers Write address data2 Write data Sign extend ADD 32 UX Shift left 2 ALU 3 ALU operation Zero ALU result ADD 32bits data address enwrite data Data emory Write data en UX UX

30 Chapter Five The processor : Datapath and control 5. Introduction 5.2 Logic Design Conventions (skip) 5.3 Building a datapath 5.4 A Simple Implementation Scheme 5.5 A ulticycle Implementation 5.5 icroprogramming 5.6 Exception

31 Building the Datapath Use multiplexors to stitch them together Note : control signals Page 36 F5.6

32 Building Control Analyse for cause and effect Information comes from the 32 bits of the instruction Selecting the operations to perform (ALU, read/write, etc.) Controlling the flow of data (multiplexor inputs) ALU's operation based on instruction type and function code R-format instruction (add, sub, and, or, slt) Op 6 bits 5bits 5bits 5bits 5bits 6bits I-format instruction (lw, sw, beq) Op Rs Rt Immediate 6 bits 5bits 5bits 6bits J-format instruction (add, sub, and, or, slt) Op Rs Rt Rd Shamt Funct address 6 bits 26bits

33 Code P3 Code add R rs rt rd sub R rs rt rd and R rs rt rd or R rs rt rd slt R rs rt rd lw I rs rt Immediate(displacement) sw I rs rt Immediate(displacement) beq I rs rt Immediate(offset) j J address

34 What should ALU do? e.g. what should the ALU do with these instructions Example: lw $, ($2) lw sw R OP rs rt 6 bit displacement ()35 2 ()43 2 () rs(5) rt(5) rd(5) shamt func(6) ALU op ALU control input 3 -types B negate op function and Or Add Sub Slt Why is the code for subtract and not?

35 Scheme of Controller 2-level decoder op(6) rs(5) rt(5) rd(5) shamt func(6) instruction op code (6) First ain decoder ALU op(2) Defined ALU Decoder Second Signals for Other Components (7) Defined at Chapter-3 ALU operation(3) Defined

36 The ALU control is where and other signals(7)

37 signals for datapath Defined 7+2 control (p. 35) Signal name Effect when deasserted(=) RegDst RegWrite Select register destination number from the rt(2:6) when WR None Effect when asserted(=) Select register destination number from the rd(5:) when WB Register destination input is written with the value on the Write data input ALUScr PCSrc em emwrite emtoreg The second ALU operand come from the second register file output ( data 2) The PC is replaced by the output of the adder that computers the value PC+4 None None The value fed to register Write data input comes from the Alu The second ALU operand is the signextended lower 6 bits of the instruction.. The PC is replaced by the output of the adder that computers the branch target. Data memory contents designated by the address input are put on the data output. Data memory contents designated by the address input are replaced by value on the Write data input. The value fed to the register Write data input comes from the data memory.

38 Designing the ain Control Unit (First level) ain Control Unit function ALU op (2) Divided 7 control signals into 2 groups 4 ux 3 R/W op code (6) ALU control ALU op (2) ux (4) R/W (3) em emwrite LW SW Beq R-type RegDst ALUScr PCSrc emtoreg RegWrite

39 Truth Table for ain decoder 4 Add [3 26] RegDst Branch em emtoreg Control ALUOp emwrite ALUSrc RegWrite Shift left 2 Add ALU result u x PC address memory [3 ] [25 2] [2 6] [5 ] u x register data register 2 Registers Write data 2 register Write data u x Zero ALU ALU result Address Write data Data memory data u x [5 ] 6 Sign 32 extend ALU control [5 ] RegDst ALUSrc emtoreg RegWrite em emwrite Branch ALU op ALU op emto- Reg em em R-format beq X RegDst ALUSrc X Reg Write Write Branch ALUOp ALUp LW R-format R-format lw SW LW sw X X beq SW beq X X X X

40 Circuitry of main Controller Simple combinational logic (truth tables) Inputs Op5 Op4 Op3 Op2 Op Op R-format Iw sw beq Outputs RegDst ALUSrc emtoreg RegWrite em emwrite Branch ALUOp ALUOpO opcode output R-format lw sw beq L/S beq R-type

41 Designing the ALU decoder (Second level) ust describe hardware to compute 3-bit ALU conrol input opcode ALUop operation Funct field Desired ALU action ALU control Input LW Load word xxxxxx Load word SW Store word xxxxxx Store word Beq branch equal xxxxxx branch equal R-type add add R-type subtract subtract R-type AND AND R-type OR OR R-type Set on less than Set on less than

42 Truth Table for ALU decoder Describe it using a truth table (can turn into gates): don t care ALUOp Funct field Operation ALUOp ALUOp F5 F4 F3 F2 F F 2 X X X X X X X X X X X X X X X X X X X X X X X X X X X X Operation 2 = ALU op + ALU op (F 3 F 2 F F + F 3 F 2 F F ) Operation = ALU op F 3 F 2 F F + ALU op F 3 F 2 F F Operation = ALU op F 3 F 2 F F + ALU op F 3 F 2 F F

43 The ALU control signals----logic circuit ALUOp ALU control block ALUOp ALUOp Operation2 F3 F2 Operation F (5 ) F Operation F Operation Operation Operation 2 = = = ALU ALU ALU op op op + + F 2 + (F ALU + F Operation op 3 F ) F F F F 3 F 2 x x x x x x x x x x x F F F 3 F 2 x x F 2 x X x x x X x x F F F F 3 F 2 x x F 3 x X x x x X x x x

44 Our Simple Control Structure All of the logic is combinational We wait for everything to settle down, and the right thing to be done ALU might not produce right answer? right away we use write signals along with clock to determine when to write Cycle time determined by length of the longest path State element Combinational logic State element 2 n n+ Clock cycle We are ignoring some details like setup and hold times

45 The simple Datapath with the control unit pc 4 [25-] Shift jump address[3-] left 2 Add ALU U U PC+4[3-28] result X X Shift Add left 2 address [3-26] Control RegDst Branch em emto ALUOp emwrite ALUSrc RegWrite jump R-type [3-] memory Op rs rt rd shamt Funct I-type Op rs rt Jump-type Op Immediate address [25-2] [2-6] U X [5-] [5-] register register 2 Write register Write data data data 2 Registers 6 Sign 32 extend [5-] U X ALU control Zero ALU ALU result Address data Data memory Write data U X

46 The Datapath in operation for R-type pc 4 [25-] address Add 26 Shift left 2 [3-26] jump address[3-] 28 PC+4[3-28] Control RegDst Branch em emto ALUOp emwrite ALUSrc RegWrite Shift left 2 Add ALU result U X U X jump I-type Op rs rt Jump-type Op [3-] memory add sub and or slt R-type Op rs rt rd shamt Funct Immediate address [25-2] [2-6] U X [5-] [5-] register register 2 Write register Write data data data 2 Registers 6 Sign 32 extend [5-] U X ALU control Zero ALU ALU result Address data Data memory Write data U X

47 The Datapath in operation for load pc 4 [25-] Shift 26 left 2 28 address Add [3-26] Control jump address[3-] PC+4[3-28] RegDst Branch em emto ALUOp emwrite ALUSrc RegWrite Shift left 2 Add ALU result U X U X jump R- Otype rsrt r I-type p d Op [3-] memory load instruction sha mt address Fu nct Op rs rt Immediate Jump-type [25-2] [2-6] U X [5-] [5-] register register 2 Write register Write data data data 2 Registers 6 Sign 32 extend [5-] U X ALU control Zero ALU ALU result Address data Data memory Write data U X

48 The Datapath in operation for store pc 4 [25-] Shift 26 left 2 28 address Add [3-26] Control jump address[3-] PC+4[3-28] RegDst Branch em emto ALUOp emwrite ALUSrc RegWrite Shift left 2 Add ALU result U X U X jump R- Otype rsrt r I-type p d Op rs rt sha mt Jump-type Op [3-] memory store instruction address Fu nct Immediate [25-2] [2-6] U X [5-] [5-] register register 2 Write register Write data data data 2 Registers 6 Sign 32 extend [5-] U X ALU control Zero ALU ALU result Address data Data memory Write data U X

49 The Datapath in operation for beq pc 4 [25-] Shift 26 left 2 28 address Add [3-26] Control jump address[3-] PC+4[3-28] RegDst Branch em emto ALUOp emwrite ALUSrc RegWrite Shift left 2 Add ALU result U X U X jump R- Otype rsrt r I-type p d Op rs rt Jump-type Op [3-] memory beq instruction sha mt address Fu nct Immediate [25-2] [2-6] U X [5-] [5-] register register 2 Write register Write data data data 2 Registers 6 Sign 32 extend [5-] U X ALU control Zero ALU ALU result Address data Data memory Write data U X

50 j instruction instruction format j Label ()2 26 bits address Implementation pc = pc 28~3 ## 26bits-address 4

51 The Datapath in operation for Jump pc 4 [25-] address Add 26 Shift left 2 [3-26] 28 Control jump address[3-] PC+4[3-28] RegDst Branch em emto ALUOp emwrite ALUSrc RegWrite Shift left 2 Add ALU result U X U X jump jump instruction R- Otype rsrt r sha Fu I-type p d mt nct O rs rt Immediat Jump-type p e Op [3-] memory address [25-2] [2-6] U X [5-] [5-] register register 2 Write register Write data data data 2 Registers 6 Sign 32 extend [5-] U X ALU control Zero ALU ALU result Address data Data memory Write data U X

52 Single Cycle Implementation performance for lw Calculate cycle time assuming negligible delays except: memory (2ns), ALU and adders (2ns), register file access (ns) 4 Add [3 26] Control RegDst Branch em emtoreg ALUOp emwrite ALUSrc RegWrite Shift left 2 Add ALU result u x PC address memory [3 ] [25 2] [2 6] [5 ] u x register data register 2 Registers Write data 2 register Write data u x Zero ALU ALU result Address Write data Data memory data u x [5 ] 6 Sign 32 extend ALU control [5 ] 2ns +=ns 2ns 2ns

53 Performance in Single Cycle Implementation Let s see the following table: class memory Register read ALU Data memory Register write Total R-format ns Load word ns Store word ns Branch ns Jump 2 2 ns The conclusion: Different instructions needs different time. The clock cycle must meet the need of the slowest instruction. So,some time will be wasted.

54 The CPU Performance Equation CPU time =I CPI τ

55

56 CPU performance is dependent upon three characteristics: clock cycle (or rate) clock cycles per instruction and instruction count. It is difficult to change one parameter in complete isolation from others because the basic technologies involved in changing each characteristic are interdependent: Clock cycle time Hardware technology and organization Clock cycle time Hardware technology and organization count set architecture and compiler technology

57 IPS (million instruction per second) The bigger the IPS, the faster the machine. Three problems with IPS: IPS is dependent on the instruction set, making it difficult to compare IPS of computers with different instruction sets. IPS varies between programs on the same computer. ost importantly, IPS can vary inversely to performance!

58 Single Cycle Problems : what if we had a more complicated instruction like floating point? If so,the waste of time will be more serious. wasteful of area. The reason is the following: Let s see the instruction mult.this instruction needs to use the ALU repeatedly. But,in the single cycle implementation,one ALU can be used only once in one clock cycle. So,the instruction mult will need many ALUs.The CPU will be very large.

59 One Solution for Single Cycle Problems One Solution: Use a smaller cycle time Let different instructions take different numbers of cycles a ulticycle datapath: PC Address emory Data or data register emory data register Data Register # Registers Register # Register # A B ALU ALUOut

60 Chapter Five The processor : Datapath and control 5. Introduction 5.2 Logic Design Conventions (skip) 5.3 Building a datapath 5.4 A Simple Implementation Scheme 5.5 A ulticycle Implementation 5.5 icroprogramming 5.6 Exception

61 ulticycle Approach Break up the instructions into steps, each step takes a cycle balance the amount of work to be done restrict each cycle to use only one major functional unit At the end of a cycle store values for use in later cycles introduce additional internal registers

62 Analyse events: Five Execution Steps IF: Fetch ID: Decode and Register Fetch EX(BC):Execution, emory Address Computation, or Branch Completion E(WB):emory Access or R-type instruction completion WB:Write-back step INSTRUCTIONS TAKE FRO 3-5 CYCLES!

63 Step : Fetch Use PC to get instruction and put it in the Register. IR = emory[pc]; Increment the PC by 4 and put the result back in the PC. PC = PC + 4; Can be described simply using RTL "Register-Transfer Language" IR = emory[pc]; PC = PC + 4; Can we figure out the values of the control signals? What is the advantage of updating the PC now?

64 Step 2: Decode and Register Fetch registers rs and rt in case we need them Compute the branch address in case the instruction is a branch RTL: A = Reg[IR[25-2]]; B = Reg[IR[2-6]]; ALUOut = PC + (sign-extend(ir[5-]) << 2); We aren't setting any control lines based on the instruction type (we are busy "decoding" it in our control logic)

65 Step 3 (instruction dependent) ALU is performing one of three functions, based on instruction type emory Reference ( lw / sw ): ALUOut = A + sign-extend(ir[5-]); R-type: ALUOut = A op B; Branch: if (A==B) PC = ALUOut; jump: pc = pc IR25- << 2

66 Step 4 (R-type or memory-access) Loads and stores access memory DR = emory[aluout]; # for lw or emory[aluout] = B; # for sw R-type instructions finish Reg[rd]=Reg[ IR[5-] ] = ALUOut; The write actually takes place at the end of the cycle on the edge

67 Write-back step (step 5) lw Reg[rt]=Reg[IR[2-6]]= DR; What about all the other instructions?

68 Summary: Step name fetch decode/register fetch Action for R-type instructions Action for memory-reference Action for instructions branches IR = emory[pc] PC = PC + 4 A = Reg [IR[25-2]] B = Reg [IR[2-6]] ALUOut = PC + (sign-extend (IR[5-]) << 2) Action for jumps Execution, address ALUOut = A op B ALUOut = A + sign-extend if (A ==B) then PC = PC [3-28] II computation, branch/ (IR[5-]) PC = ALUOut (IR[25-]<<2) jump completion emory access or R-type Reg [IR[5-]] = Load: DR = emory[aluout] completion ALUOut or Store: emory [ALUOut] = B emory read completion Load: Reg[IR[2-6]] = DR

69 Simple Questions How many cycles will it take to execute this code? lw $t2, ($t3) lw $t3, 4($t3) beq $t2, $t3, Label #assume not add $t5, $t2, $t3 sw $t5, 8($t3) Label:... What is going on during the 8th cycle of execution? Answer: In what cycle does the actual addition of $t2 and $t3 takes place? No. 6 Calculating memory address (2)

70 Reusing Resource We will be reusing functional units ALU used to compute address and to increment PC emory used for instruction and data We will use a finite state machine for control PC Address emory or data Data register emory data register Data Register # Registers Register # Register # A B ALU ALUOut shared unit

71 Scheme of Controller of ulticycle PC u x Address Write data emory emdata [25 2] [2 6] [5 ] register [5 ] emory data register [5 ] u x u x 6 register register 2 Registers Write register Write data Sign extend data data 2 32 Shift left 2 A B 4 u x u 2 x 3 Zero ALU ALU result ALUOut

72 How does it control in ulticycle Approach IorD em emwrite IRWrite RegDst RegWrite ALUSrcA PC u x Address Write data emory emdata [25 2] [2 6] [5 ] register [5 ] emory data register [5 ] u x u x 6 register register 2 Registers Write register Write data Sign extend data data 2 32 Shift left 2 A B 4 u x u 2 x 3 ALU control Zero ALU ALU result ALUOut [5 ] emtoreg ALUSrcB ALUOp

73 signals for datapath of ulticycle Defined +6 control (p. 324) Signal name Effect when deasserted(=) Effect when asserted(=) RegDst Select register destination number from the rt(2:6) when WR. Select register destination number from the rd(5:) when WB. RegWrite None Register destination input is written with the value on the Write data input ALUScrA The first ALU operand is the PC The first ALU operand come from the A register. em None emory contents at the location specified by the address input is put on the emory data out. emwrite None emory contents at the location specified by the address input are replaced by value on the Write data input. emtoreg IorD The value fed to register Write data input comes from the ALUOut The PC is used to supply the address to the memory unit. The value fed to the register Write data input comes from the DA. ALUOut is used to supply the address to the memory unit. IRWrite None The output of memory is written into the IR. PCWrite None The is written;the source is controlled by PCSource. PCWriteCond None The PC is written if the zero output from the ALU is also active.

74 Control signals Signal name Value Effect ALUOp ALUScrB The ALU performs an add operation. The ALU performs an subtract operation. The funct field of the instruction determines the ALUoperation The second input to the ALU comes from the B register. PCSource The second input to the ALU is the constant 4. The second input to the ALU is the sign-extended, lower 6 bits of the IR. The second input to the ALU is the sign-extended, lower 6 bits of the IR shift 2 bits. Output of the ALU(PC+4) is sent to the PC for writing. The contents of ALUOut (the branch target address) are sent to the PC writing. The jump target address (IR[25:]shifted left 2 bits and concatenated with PC+4[3:28]) is sent to the PC for writing.

75 seq: pc = pc + 4 beq:pc = pc + offset * 4 j :pc = pc IR 25- << 2 PC u x Address Write data emory emdata [3-26] [25 2] [2 6] [5 ] register [5 ] emory data register PCWriteCond PCWrite IorD Outputs em emwrite emtoreg IRWrite [25 ] [5 ] Control Op [5 ] u x u x PCSource ALUOp ALUSrcB ALUSrcA RegDst 6 RegWrite register register 2 Registers Write register Write data Sign extend data data 2 32 Shift left 2 A B 4 u x u 2 x 3 26 Shift 28 left 2 ALU control PC [3-28] Zero ALU ALU result Jump address [3-] ALUOut 2 u x [5 ]

76 Implementing the Control Value of control signals is dependent upon: what instruction is being executed which step is being performed Let s go over the main control unit in the single-cycle implementation.

77 Review for singlecycle ain control unit in the single-cycle implementation R-type lw 35 sw 43 beq 4 Inputs Op5 Op4 Op3 Op2 Op Op Outputs R-format Iw sw beq RegDst ALUSrc emtoreg RegWrite em emwrite Branch ALUOp ALUOpO

78 Review Now,let s look at the AlU control unit.it does not need to changed. ALUOp ALUOp ALUOp ALU control block F3 Operation2 F (5 ) F2 F F Operation Operation Operation

79 As same as the single-cycle So,the following truth table remains the same. ALUOp Funct field Operation ALUOp ALUOp F5 F4 F3 F2 F F X X X X X X X X X X X X X X X X X X X X X X X X X X X X

80 Review: Finite state machines Finite state machines: a set of states next state function (determined by current state and the input) output function (determined by current state and possibly input) Current state Next-state function Next state Inputs Clock Output function Outputs

81 Difference in controller Do something different in each cycle Tow main ways to implement the control. Finite state machine 2. use microprogramming Next,we will discuss the first way.

82 PC u x Address Write data emory emdata [3-26] [25 2] [2 6] [5 ] register [5 ] emory data register PCWriteCond PCWrite IorD Outputs em emwrite emtoreg IRWrite [25 ] [5 ] Control Op [5 ] u x u x PCSource ALUOp ALUSrcB ALUSrcA RegDst 6 RegWrite register register 2 Registers Write register Write data Sign extend data data 2 32 Shift left 2 A B 4 u x u 2 x 3 26 Shift 28 left 2 ALU control PC [3-28] Zero ALU ALU result Jump address [3-] ALUOut 2 u x [5 ]

83 State diagram for execute flow Ref Fig5.3 (p.332) Start fetch/decode and registerfetch Figure(5.32) enory access instructions Figure(5.33) R-type instructions Figure(5.34) Branch instructions Figure(5.35) Jump instructions Figure(5.36)

84 fetch / decode and Reg fetch Start (Op = 'LW') or (Op = 'SW') fetch em ALUSrcA = IorD = IRWrite ALUSrcB = ALUOp = PCWrite PCSource = (Op = R-type) (Op = 'BEQ') decode/ Register fetch ALUSrcA = ALUSrcB = ALUOp = (Op = 'JP') emory reference FS (Figure 5.33) R-type FS (Figure 5.34) Branch FS (Figure 5.35) Jump FS (Figure 5.36)

85 lw and sw 2 From state ALUSrcA = ALUSrcB = ALUOp = (Op = 'LW') or (Op = 'SW') emory address computation 3 (Op = 'LW') emory access (Op = 'SW') 5 emory access em IorD = emwrite IorD = 4 Write-back step RegWrite emtoreg = RegDst = To state (Figure 5.32)

86 R-type From stste 6 Op=R-type ALUSrcA= ALUSrcB= ALUOp= Execution 7 RegDst= RegWrite emtoreg= R-type completion To stste (Figure 5.32)

87 Branch From stste 8 Op= BEQ ALUSrcA= ALUSrcB= ALUOp= PCWriteCond PCSource= Branch completion To stste (Figure 5.32)

88 J-type From stste 9 Op= J PCSource= Jump completion To stste (Figure 5.32)

89 Graphical Specification of FS lw 2 3 emory address computation ALUSrcA = ALUSrcB = ALUOp = (Op = 'LW') em IorD = emory access (Op = 'SW') 5 Start (Op = 'LW') or (Op = 'SW') sw emwrite IorD = emory access fetch em ALUSrcA = IorD = IRWrite ALUSrcB = ALUOp = PCWrite PCSource = 6 7 Execution ALUSrcA = ALUSrcB = ALUOp= RegDst = RegWrite emtoreg = 8 R-type completion (Op = R-type) Branch completion ALUSrcA = ALUSrcB = ALUOp = PCWriteCond PCSource = beq (Op = 'BEQ') decode/ register fetch 9 ALUSrcA = ALUSrcB = ALUOp = (Op = 'J') Jump completion PCWrite PCSource = jump 4 Write-back step R-type RegDst= RegWrite emtoreg =

90 The truth table for the 6 datapath control outputs, which depend only on the state inputs.

91 The logic equations for the control unit shown in a shorthand form

92 Implemented using a block of combinational logic and a register to hold the the current state Combinational Control logic Datapath control output Outputs Inputs State register Next state Input from instruction Register opcode field

93 Chapter Five The processor : Datapath and control 5. Introduction 5.2 Logic Design Conventions (skip) 5.3 Building a datapath 5.4 A Simple Implementation Scheme 5.5 A ulticycle Implementation 5.5 icroprogramming 5.6 Exception

94 icroinstruction format icroinstruction control signal position of next icroinstruction Representation split into some fields next position sequential dispatch table (jump)

95 icroinstruction format (Reg fetch) A=Reg[IR 25-2 ], B=Reg[IR 2-6 ]

96 icroinstruction format em address is from

97 Steps of s Step name fetch decode/register fetch Action for R-type instructions Action for memory-reference Action for instructions branches IR = emory[pc] PC = PC + 4 A = Reg [IR[25-2]] B = Reg [IR[2-6]] ALUOut = PC + (sign-extend (IR[5-]) << 2) Action for jumps Execution, address ALUOut = A op B ALUOut = A + sign-extend if (A ==B) then PC = PC [3-28] II computation, branch/ (IR[5-]) PC = ALUOut (IR[25-]<<2) jump completion emory access or R-type Reg [IR[5-]] = Load: DR = emory[aluout] completion ALUOut or Store: emory [ALUOut] = B emory read completion Load: Reg[IR[2-6]] = DR

98 icrooperation 2 emory address computation ALUSrcA = ALUSrcB = ALUOp = Start fetch em ALUSrcA = IorD = IRWrite ALUSrcB = ALUOp = PCWrite PCSource = 6 (Op = 'LW') or (Op = 'SW') Execution ALUSrcA = ALUSrcB = ALUOp= 8 (Op = R-type) Branch completion ALUSrcA = ALUSrcB = ALUOp = PCWriteCond PCSource = decode/ register fetch (Op = 'BEQ') 9 ALUSrcA = ALUSrcB = ALUOp = (Op = 'J') Jump completion PCWrite PCSource = 3 (Op = 'LW') emory access (Op = 'SW') 5 emory access 7 R-type completion em IorD = emwrite IorD = RegDst = RegWrite emtoreg = 4 Write-back step RegDst= RegWrite emtoreg=

99 icroprogramming A specification methodology address appropriate if hundreds of opcodes, modes, cycles, etc. signals specified symbolically using microinstructions Label ALU control SRC SRC2 Register control emory PCWrite control Sequencing Fetch Add PC 4 PC ALU Seq Add PC Extshft Dispatch em Add A Extend Dispatch 2 LW2 ALU Seq Write DR Fetch SW2 Write ALU Fetch Rformat Func code A B Seq Write ALU Fetch BEQ Subt A B ALUOut-cond Fetch JUP Jump address Fetch

100 微指令编码 ALUOp ALUOp ALU ALUSrcA ALUSrcB ALUSrcB IRWrite RegWrite RegDst SRC SRC2 emtoreg em em IorD PCSource PCSource PCWrite PCWriteCond Addrctl Addrctl Register emory control control PCWite Seq ALU Register PCWrite Label control SRC SRC2 control emory control Sequencing Fetch Add PC 4 PC ALU Seq Add PC Extshft Dispatch em Add A Extend Dispatch 2 LW2 ALU Seq Write DR Fetch SW2 Write ALU Fetch RformatFunc codea B Seq Write ALU Fetch BEQ Subt A B ALUOut-cond Fetch JUP Jump addressfetch

101 icroprogramming What are the icroinstructions? Control unit icrocode memory Outputs Input PCWrite PCWriteCond IorD em emwrite IRWrite BWrite emtoreg PCSource ALUOp ALUSrcB ALUSrcA RegWrite RegDst AddrCtl Datapath Adder icroprogram counter Address select logic Op[5 ] register opcode field

102 Details PLA or RO Dispatch RO Dispatch State RO 2 Op Opcode name Value Adder Op Opcode name Value R-format lw ux jmp 3 2 sw beq lw sw Dispatch RO 2 Dispatch RO AddrCtl Address select logic Op register opcode field State number Address-control action Value of AddrCtl Use incremented state 3 Use dispatch RO 2 Use dispatch RO Use incremented state 3 4 Replace state number by 5 Replace state number by 6 Use incremented state 3 7 Replace state number by 8 Replace state number by 9 Replace state number by Seeing to CD

103 ALU ALUOp ALUOp Lw sw SRC SRC2 ALUSrcA ALUSrcB ALUSrcB IRWrite Opcode 3 2 State (C) Register control emory control PCWite RegWrite RegDst emtoreg em em IorD PCSource PCSource PCWrite R J Beq Lw Sw Seq PCWriteCond Addrctl Addrctl

104 Chapter Five The processor : Datapath and control 5. Introduction 5.2 Logic Design Conventions (skip) 5.3 Building a datapath 5.4 A Simple Implementation Scheme 5.5 A ulticycle Implementation 5.5 icroprogramming 5.6 Exception

105 5.6 Exception The cause of changing CPU s work flow : Control instructions in program (bne/beq, j, jal, etc) It is foreseeable in programming flow Something happen suddenly (Exception and Interruption) It is unpredictable Unexpected events Exception: from within processor ( overflow, undefined instruction, etc) Interruption : from outside processor ( input /output )

106 5.6 Exception Exception An Exception is a unexpected event from within processor. We follow the IPS convention, using the term exception to refer to any unexpected change in control flow. Here we will discuss two types exceptions : arithmetic overflow undefined instruction

107 How Exceptions Are Handled When exception happens, the processor must do something. The predefined process routines are saved in memory when computer starts. Problem: how can CPU goto relative routine when an exception occurs. CPU should know the cause of exception which instruction generate the exception

108 How Exceptions Are Handled Design add a register: exception program counter(epc) save the address of the offending instruction add a status register: cause register( CauseReg) hold a field that indicates the reason for the exception. undefined instruction bit = overflow Another method is to use vector interrupts Exception type vector address undefine instr c H overflow c 2 H

109 How Control Checks for Exceptions add control signal CauseWrite for CauseReg EPCWrite for EPC EPC = PC - 4 (completed by ALU) process of control CauseReg = or EPC = PC - 4 PC <--- address of process routine ( ex. c )

110 How Control Checks for Exceptions PC u x Address Write data emory emdata [25 2] [2 6] [5 ] register [5 ] emory data register PCWriteCond PCWrite IorD em emwrite emtoreg IRWrite [5 ] Outputs Control Op [5 ] [25 ] 26 Shift 28 left 2 [3-26] PC [3-28] u x u x 6 CauseWrite IntCause EPCWrite PCSource ALUOp ALUSrcB ALUSrcA RegWrite RegDst register register 2 Registers Write register Write data 32 Sign extend data data 2 Shift left 2 A B 4 u x u 2 x 3 ALU control Zero ALU ALU result Jump address [3-] CO 3 ALUOut u x u x 2 EPC Cause [5 ]

111 How Control Checks for Exceptions detect exceptions Undefined instruction when no next state is defined from state for op value. New state is introduced. Overflow Overflow is occured only in R-type instruction. Overflow is provided as an output from the ALU. This signal is used in the modified FS to specify an additional state for state 7.

112 IntCause = CauseWrite ALUSrcA = ALUSrcB = ALUOp = EPCWrite PCWrite PC++Source = IntCause = CauseWrite ALUSrcA = ALUSrcB = ALUOp = EPCWrite PCWrite PCSource = PCSource = To state to begin next instruction

113 emory address computation 2 ALUSrcA = ALUSrcB = ALUOp = Start fetch em ALUSrcA = IorD = IRWrite ALUSrcB = ALUOp = PCWrite PCSource = 6 (Op = 'LW') or (Op = 'SW') Execution ALUSrcA = ALUSrcB = ALUOp = (Op = R-type) Branch completion 8 ALUSrcA = ALUSrcB = ALUOp = PCWriteCond PCSource = decode/ Register fetch (Op = 'BEQ') 9 ALUSrcA = ALUSrcB = ALUOp = (Op = 'J') Jump completion PCWrite PCSource = (Op = other) 3 (Op = 'LW') em IorD = emory access 5 (Op = 'SW') emwrite IorD = emory access 7 R-type completion IntCause = CauseWrite RegDst = RegWrite emtoreg = Overflow ALUSrcA = ALUSrcB = ALUOp = EPCWrite PCWrite PCSource = IntCause = CauseWrite ALUSrcA = ALUSrcB = ALUOp = EPCWrite PCWrite PCSource = 4 Write-back step Overflow RegWrite emtoreg = RegDst =