Liquid Architecture. Microarchitecture Optimization for Embedded Systems

Transcription

1 Liquid Architecture Microarchitecture Optimization for Embedded Systems D. Schuehler, B. Brodie, R. Chamberlain, R. Cytron, S. Friedman, J. Fritts, P. Jones, P. Krishnamurthy, J. Lockwood, S. Padmanabhan, and H. Zhang Dept. of Computer Science and Engineering Washington University in St. Louis Supported by NSF ITR

2 Liquid Architecture Configurable architecture that can adapt to needs of particular application E.g., within an FPGA Soft-core processors E.g., as an embedded processor Tensilica supports configuration at fab time Stretch support configuration at run time Today s discussion is on performance analysis and configuration choice

3 Block Diagram Event Bus FPGA FPX Statistics Module Control Packet Processor I-Cache D-Cache AHB APB LEON SPARCcompatible processor LED UART `` Adapter `` Memory Controller Boot Rom External Memory Network Interface Layered Internet Protocol Wrappers

4 Microarchitecture Configurability Instruction set Memory subsystem Cache size (I and D) Associativity Cache line size Co-processor(s) Instruction pipeline Full HDL source is available

5 Design Flow Internet Write and compile embedded SPARC application with GCC Identify configuration for candidate architecture Reconfigure FPX hardware via Internet and upload system software. Execute program on FPX Platform and measure runtime performance

6 .text Method Time / Cycles Cycle-accurate profiling main addquery findmatch Choose methods to profile from the user interface computekey computebase computestep fillquery Rnd

7 Method Address Range.text main addquery findmatch Lo 0x C 0x400003EF Hi computekey computebase computestep fillquery Rnd

8 .text Method Statistics Module Event Bus PC CLK main addquery findmatch Lo 0x C 0x400003EF Hi 0x A computekey computebase computestep fillquery Rnd

9 Function Event Bus PC CLK.text Statistics Module main Lo 0x C 0x A 0x400003EF Hi addquery findmatch INCR Counter computekey computebase computestep fillquery Rnd

10 Function Event Bus PC CLK.text Statistics Module main Lo 0x C 0x A 0x400003EF Hi addquery findmatch INCR Counter computekey computebase Lo 0x400005D8 0x A 0x F Hi computestep fillquery INCR Counter Rnd

11 Event Bus Statistics Module PC CLK Lo 0x C 0x A 0x400003EF Hi To User INCR Counter Lo 0x400005D8 0x A 0x F Hi INCR Counter

12 Where is time spent? 100% 90% % of total runtime 80% 70% 60% 50% 40% 30% Rest coreloop findmatch BLASTN biosequence search application 20% 10% 0% 128K 32K Size of hash table (Bytes)

13 Function.text Time / Cycles Cache Hits / Misses Read Write main addquery findmatch computekey Expand to measure cache hits/misses computebase computestep fillquery Rnd

14 Measure Several Configurations

15 Impact of D-cache Configuration Total findmatch coreloop hit rate (%) BLASTN biosequence search application K, 1Kx1 128K, 32Kx1 128K, 16Kx2 32K, 1Kx1 32K, 32Kx1 32K, 16Kx2 Size of hash table, D-cache configuration

16 Impact of I-cache Configuration 35 Run time (secs) KB I-Cache 4KB I-Cache BLASTN biosequence search application K 32K BLASTN hash table sizes (Bytes)

17 Function Time / Cycles Cache Hits / Misses Read Write Pipeline Stalls Branch Predict.text main addquery findmatch computekey computebase computestep fillquery Rnd

18 Time for Single Run Time (sec) Almost 2 orders of magnitude faster than simulation 10 1 SimpleScalar 3.0 LEON

19 Implications of Slow Simulation Focus has historically been on measuring the performance of a single thread of a single application Real apps are often executed in a multitasking environment Impacts cache behavior Ignores OS (system call) performance Liquid architecture system enables direct measurement, including OS

20 OS Boot Sequence

21 Summary Run-time reconfigurable processors will be available sooner rather than later Determining desired configuration is a difficult design task Large search space Depends on accurate performance data Liquid architecture system enables direct measurement of performance properties

22 Current and Future Work Evaluation of several arch. design ideas Automated search of the design space Characterizing performance analysis methods Analytic models Simulation models Direct execution models Usable as is for evaluating soft-core procs Like to extend to higher-speed procs