8051 Interfacing: Address Map Generation

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1 85 Interfacing: Address Map Generation EE438 Fall2 Class 6 Pari vallal Kannan Center for Integrated Circuits and Systems University of Texas at Dallas

2 85 Interfacing Address Mapping Use address bus and data bus Interfaced device show up as memory locations from the processor They use up some of the address space Memories, displays etc I/O Mapping Connect the devices to the I/O Ports of the processor Don t use up address space Sensors, pushbuttons, LCDs, motors, LEDs etc 2-Sep-2 2

3 85 Address Generator Address Generator is a piece of hardware that produces unique addresses to each interfaced device Each Interfaced Device can use up or more locations from the address space of the processor Memories typically use up in Kilobytes (2K, 4K, 8K etc) Other devices typically use a few (<6) addresses Addresses of devices should not overlap 85 A[5:] D[7:] Addr. Gen f f3 f2 Device CE Device 2 CE Device 3 CE A[5:] D[7:] A[5:] D[7:] A[5:] D[7:] 2-Sep-2 3

4 What is needed? Need to know the following for all the devices before address generator can be designed Base address of each device Where it starts in the address map Size of the device How much of the address space it uses up Code RAM 4K Code ROM 4K Code Memory LEd 2b LCD 8b x5 x4 RAM 32K x x Data Memory xf x8 x 2-Sep-2 4

5 Example : 2K Memory at x Pins : address - A to A, Data D7 to D, _RD, _WR, _CE Base address = x Size = 2k (2 *24 = 248 bytes = x8) Address Map occupancy x to x7ff that is, binary to binary lowest address bits A to A have to be connected to the address pins on the memory 2-Sep-2 5

6 Example : (contd.) Unused address bits are A5 to A Base address is x CE has to be generated if all the unused address bits are logic- CE is active low _CE = A5 + A4 + A3 + A2 + A Then connect _RD and _WR A5 Truth-Table for CE A4 A3 A2 A _CE 2-Sep-2 6

7 Ex-2: Same Memory at x4 Base address is x4 A5 A4 A3 A2 A _CE Size is 2K Unused address bits A5 to A CE has to be generated as per the truth-table and so on Expression is _ CE = A5 A4 A3 A2 A 2-Sep-2 7

8 (In)Complete Addressing Complete addressing: Use all unused address bits to generate CE Incomplete addressing Use a sub-set of the unused address bits Used to reduce the address generator complexity Produces address aliases (same device at multiple addresses) Example 2K memory at x, we used A5 to A Instead just connect A to _CE Same 2K memory device will then be aliased for all values of A5 to A2 x, x, x2, x3,., xf Address generator became very simple, but we lost a lot of address space 2-Sep-2 8

9 7438 Decoder for Address Gen. 3 to 8 decoder, available in a single DIP package. Takes 3 address lines and generates complete addressing among those Example Connect A5, A4, A3 to the decoder inputs Decoder outputs give base addresses for x, x2, x4, x6, x8, xa, xc, xe For more complicated address decoding use programmable devices like PALs, PLDs or FPGAs A5 A4 A3 GND Vcc C B A G2 G 74LS38 Y Y Y2 Y7 2-Sep-2 9

10 External (pure) Code Memory Could be RAM or ROM Address generation as per standard procedure Connect _PSEN to the _OE of the memory device _RD and _WR are ignored Don t connect these 85 pins to the memory device Connect Data bits D7-D of the memory and the 85 2-Sep-2

11 External (pure) Data Memory Could be RAM or ROM Address generation as per standard procedure Connect _RD from the 85 to OE of the memory Connect _WR from the 85 to WR of the memory Ignore _PSEN Connect Data bits D7-D of the memory and the 85 2-Sep-2

12 External Code + Data Memory Could be RAM or ROM Address generation as per standard procedure Logically AND _PSEN and _RD and then connect to the OE of the memory Connect _WR from the 85 to WR of the memory Connect Data bits D7-D of the memory and the 85 2-Sep-2 2

13 External Non-Memory Devices Same procedure as for interfacing memory Only difference is that these devices have smaller sizes and use lesser portions of the address space Example: 8 LEDS connected to a 8bit latch. The latch is address mapped to xf. Size is byte 8255 I/O device memory mapped at xd. Size is 4 bytes 2-Sep-2 3

14 Case Study - Sample 85 System 2-Sep-2 4

15 Case study Sample 85 System 83 based No on-chip ROM, 28 bytes on-chip RAM, 8.432MHz oscillator, 74HC373 based ADBUS demuxer 8Kx8 external code memory in 28C64 EEPROM Code memory at x 32Kx8 external code+data overlapped in SRAM. SRAM mapped at x8 SRAM and EEPROM share code memory space. So decoding needed. A5 line is used for the purpose A5 = EEPROM is selected (hence x) A5 = SRAM is selected (hence x8) RS232 serial interface available for PC communication Monitor programs available 2-Sep-2 5

16 Reverse Engineering Given a system with little or no docs, determine the function, schematic, etc Vendors provide poor support. Reverse Engineering is fun! Usually No schematics are available Software is also undocumented! On-chip code could be copy protected!! 2-Sep-2 6

17 Next Class 85 I/O Mapped interfacing 85 and the 8255 I/O device Example Interfacing a character LCD 2-Sep-2 7

EE4380 Microprocessor Design Project

EE4380 Microprocessor Design Project Fall 2002 Class 1 Pari vallal Kannan Center for Integrated Circuits and Systems University of Texas at Dallas Introduction What is a Microcontroller? Microcontroller