Smallest RISC-V Device for Next-Generation Edge Computing

Transcription

1 Smallest RISC-V Device for Next-Generation Edge Computing 1 Seiji Munetoh 1, Chitra K Subramanian 2, Arun Paidimarri 2, Yasuteru Kohda 1 IBM Research Tokyo 1 & T.J. Watson Research Center 2

2 Processor chip size, Transistor count and Technology node Server Desktop Mobile Our target Next-gen edge? Embedded RFID 2 A simple microprocessor core uses 100K-1M transistors, and can fit in an area as small as 100X100 um2 using advanced technology nodes. Running at 10 MHz, such a microprocessor will consume 1-10 mw (and much less, if it runs slower). The creation of compute elements that are ultra-compact and low cost will enable a dramatic expansion of applications in areas from security to IoT to health care and beyond

3 Our 1 st target application Authentication Hash based authentication HMAC-SHA256 and variants Host/device communication Optical With micro-led and micro-pv/pd cells Protocol, UART, HDLC frame, custom payloads Bootloader ROM (synthesized, embedded in the proc. chip) Basic device authentication Upload new application to the device Storage Memory (as external chip) Use to emulate NV memory chip 3

4 Our 1 st gen. processor and 2.5D integrated device Processor (DD2) ASIC: 300um x 250um, GF14LPP SoC: Based on PULPino (RV32IMC) Memory: 2KB data + Authentication engine + Analog custom circuits(ldo, Clock...) 2.5D integration device 32KB RISC-V processor (DD1) Micro LED Si interposer < 1mm 2, 20μm bump + Processor + Memory (32KB ) + Optical I/O: PD, MicroLED + Power: PV cells (1V,3V)

5 MUX MUX Original PULPino Architecture (32KB x2) 32KB Inst 32KB Data Boot ROM (xkb) SPI-Flash (xkb) 32KB inst boot ROM RV32IMC core bridge bridge bridge MUX 32KB data 0x x x inst 32KB data 32KB boot ROM 8KB I2C bridge APB SPI master UART APB AXI 0x IO space SPI-Flash Copy to inst. & execution Application 5

6 Add-on PCB Comm, I2C.SPI ZedBpard (Original PULPino) ZYBO (Modified PULPino) ARTY (ASIC emulation) Architecture evaluation using COTS FPGA boards Reduce Memory (/Flash) size Reduce # of I/O pins Confirm Performance Develop BootROM w/ Uploader Emulate & Test ASIC design Custom analog circuits (LDO, Clock OSC, PD,LED) 6 ASIC

7 Modifications to PULPino to Reduce Size Original 32KB data Candidates 2KB data 2KB data 2KB data 2KB data 7 4-bit 8-bit 16-bit 32-bit Reduce Memory footprint: Original PULPino: 32KB(I)+32KB(D)+Ext Flash Reduced memory: 2KB(D) + 32KB Ext PULPino constraint: size > App size Remove Inst. from processor die, and use external memory to store and exec the code (XIP) area (in 14nm): 60Kmm 2 /64KB => 4Kmm 2 /2KB, (1/14) Support XIP Expand bus widths from 4 to 8,16,32 Evaluate the performance of 4,8,16,32 bit data bus widths between Proc. and ext.

8 Original Reduced memory footprint: Application Execution Performance Trade Off Candidates x 35.6 slow Candidates 8 32KB data 2KB data 2KB data 2KB data 2KB data 4-bit x 18.9 slow 8-bit x 11.7 slow 16-bit x 8.1 slow 32-bit Clock/Instruction 1(original), 76(4), 40(8), 24(16), 16(32) Application execution time from ext. 8 ~ 36 times slow Choose the 8-bit bus configuration, IO footprint fits within memory chip size Adequate for most applications But, a hash calculation by SW (XIP on ext. ) is too slow since it requires greater computational power

9 With or without of Authentication Engine HW Original 32KB data Candidates (w/o engine) x 31.3 slow 2KB data 8-bit (w/ engine) x 1.6 slow 2KB data Auth. Engine 8-bit Authentication engine SHA256, HMAC, Benes-network SHA256 performance Original: 7760 clk/blk 8-bit bus: clk/blk 8-bit bus + HW assist: clk/blk Original + HW assist: 350 clk/blk Area (FPGA) LUT 18K-> 21K, + 33% FF 15K->17K, + 21% 9 Hash Algorithm performance is adequately restored with addition of the authentication engine HW. And the BootROM can support Hash calc. w/ Auth. engine

10 MUX MUX 2KB Data Our Modified Processor Architecture (2KB + external 32KB MPI-) Boot ROM (xkb) 32KB MPI- (XIP) boot ROM XIP MUX RV32IMC core MUX 2KB data Analog bridge bridge bridge bridge 0x AXI 0x x x data 2KB boot ROM 8KB IO space AXI MPI master 8-bit width bridge Authentication Engine UART SoC ctrl APB Analog Clock gen Reset gen PD in LED out 0x MPI- XIP 32 KB MPI- Application Micro LED PV, PD IBM Confidential

11 ASIC Implementation: Processor, MPI-, Debug Chip Processor die 32KB MPI die Debug die (Proc + + PADRING) X=?um Y=?um 2.5D integration X=295um Y=256um (0.076mm 2 ) Global foundries 14LPP X=164um Y=256um 11

12 Processors Testing the Debug Chip Singulation Packaging Testing the operation Dicing QFP64, wire bonding On testbed PCB Processors Boot OK Application upload & run - OK Power ON RSTn CL K Processor send out 0x00 to host 12

13 Testing the 2.5D integrated Device Singulation Packaging Testing the operation Etching On Si interposer On probe station Boot OK 13

14 Summary of processor specs PULPino ASIC node 65nm 14nm Our processor ASIC size 1mm mm 2 Memory I- 32KB D- 32KB I- N/A D- 2KB Ext. Memory 128MB Flash MPI- 32KB Clock XXMhz 1-100MHz I/O UART, I2C.SPI UART Debug SPI slave (SPI slave) Analog - LDO, Clock/Reset, LED driver, PD input 14

15 Conclusions and future plans Our 1 st generation device is under full evaluation Preliminary tests showed functionality Target application: authentication Our 2 nd generation device was taped out Feb New SoC design with I-cache, radio interface, sensors Target applications: Blockchain and IoT application Our 3 rd generation device is under consideration It's all RISC-V 15

16 Thank you RISC-V processor MicroLED 32KB 100μm 16