Lecture 18: DRAM Technologies

Transcription

1 Lecture 18: DRAM Technologies Last Time: Cache and Virtual Memory Review Today DRAM organization or, why is DRAM so slow??? Lecture 18 1

2 Main Memory = DRAM Lecture 18 2

3 Basic DRAM Architecture Lecture 18 3

4 DRAM Access Time RAS CAS Address Row Column D out Data Valid Lecture 18 4

5 Technology Trends Year Chip Size Speeed Cycle Time Mbit 100ns 190ns Mbit 80ns 165ns Mbit 60ns 120ns Mbit 50ns 110ns Mbit 50ns 100ns Mbit 45ns 90ns Mbit 40ns 80ns Lecture 18 5

6 Processor/Memory Gap Processor Memory nanoseconds Lecture 18 6

7 Improving External Memory System Performance Bandwidth vs. Latency Bandwidth = #bits transferred per cycle Latency = time to access DRAM Bandwidth Memory bus width (16, 32, 64) Multiple memory banks Address interleaving Multiple memory controllers (independent) Latency Synchronous DRAM access modes Faster interface (Rambus) Lecture 18 7

8 Memory Bus Width Depends on microprocessor implementation 386 = 32 bit external data bus 386SX = 16 bit external data bus Today = 64 bit data busses common, 128 bit soon Also interacts with external DRAM organization Lecture 18 8

9 Interleaved Memory Organization Bank Select Latch or Queue CPU & Cache Memory Bank Lecture 18 9

10 Multiple Memory Banks (interleaving) Distribute memory address space across memory banks Route requests to banks based on low block address bits Allows memory accesses to go in parallel Two key issues how are replies matched up with requesters? how do we avoid bank conflicts? Offset Bank Word or Offset Bank A 0 A 1 A 2 A 3 D 0 D 1 D 2 D 3 A0 A1 A2 A3 Lecture 18 10

11 Bank Conflicts Accesses may not reference banks evenly Consider 0,1,2,3 vs 0,8,16,24 often caused by column access to a matrix causes problems for large block size too Solutions don t do that number of columns in matrix not a power of 2 prime number of banks number of active banks with stride s is lcd(s,b) hash the banks These techniques now embedded inside a single DRAM chip Lecture 18 11

12 Improving per DRAM chip Performance: Synchronous DRAM Interface signals are clocked Clock provided by microprocessor Why? Easier to designed timed protocols Data available 8 cycles after CAS Add intelligence to EMI (external memory interface) on CPU Lecture 18 12

13 Micron GDDR3 SDRAM Lecture 18 13

14 Burst Mode Provide one address and sequence of data comes out Perfect for cache line reads and writes Burst size programmable RAS CAS Address Row Column D out D0 D1 D2 D3 Lecture 18 14

15 Synchronous DDR approx 600 MHz clk Lecture 18 15

16 Page Mode Access One RAS (get whole row) Multiple CAS (different parts of the row) Exploits spatial locality (kind of like DRAM cache) RAS CAS Address Row ColB ColC D out B0 B1 B2 B3 C0 C1 Lecture 18 16

17 Pipelined Mode Access Interleave access to multiple internal banks Lower latency for back-to-back access to different banks RAS CAS Address RowB RowC ColB ColC D out B0 B1 B2 B3 C0 C1 Can combine page/pipelined mode access Even better schedule accesses to better use page/pipeline Starting to be done in HW Can even put prefetching hardware at memory interface Lecture 18 17

18 Changing the open page in a bank is slow Lecture 18 18

19 Reads after writes are slow! Lecture 18 19

20 Newer DRAM Interfaces Double Data Rate (DDR) DRAM Transfer data at rising and falling edge Regular DRAM 150MHz at 8byte width = 1.2GBytes/sec Double data rate = 2.4GBytes/sec Rambus RDRAM split transaction bus, byte wide More complicated electrical interface on DRAM and CPU Restrictions on board level design DRDRAM Direct Rambus DRAM 800 MHz interface at 18 bits = 1.6GB/sec per chip Lecture 18 20

21 Other Memory Technologies Embedded DRAM DRAM built into processor chip (PIM-type architectures) ROM read-only memory Programmed at manufacture time Arrays with programmable transistor sites Flash/EPROMs Programmed by tunnelling current to gate Floating gate store charge Fast read, writes x slower than DRAM Capacity 8x worse MRAM magnetic RAM Emerging technology non-volatile storage Slow reads, with higher power Lecture 18 21

22 Summary Two important characteristics of main memory Latency memory latency increasing we re stuck with it Bandwidth typically limited by pin count on processor chip Also a problem, but can at least throw money at it Variety of techniques to increase and make better use of BW Increase transmission rates (DDR, Rambus) Overlap multiple accesses Prefetch data when memory bus is idle Lecture 18 22