Advanced 1 Transistor DRAM Cells

Transcription

1 Trench DRAM Cell Bitline Wordline n+ - Si SiO 2 Polysilicon p-si Depletion Zone Inversion at SiO 2 /Si Interface [IC1] Address Transistor Memory Capacitor SoC - Memory - 18 Advanced 1 Transistor DRAM Cells Word line Insulating Layer Cell plate Capacitor dielectric layer Cell Plate Si Capacitor Insulator Storage Node Poly 2nd Field Oxide Refilling Poly Si Substrate Transfer gate Storage electrode Isolation [Rabaey] Trench Cell SoC - Memory - 19 Stacked-capacitor Cell

2 Sense Amplifier Bitlines WL i-4 WL i-3 WL i-2 Memory cells WL i-1 SA 1 SA 2 SA 3 SA 4 SA 5 SA 6 SA 7 SA: Sense Amplifier WL i WL i+1 WL i+2 Memory Speicherzellen cells WL i+3 [IC1] WL i : Wordlines 2 n/2 Bitlines SoC - Memory - 20 Sense Amplifier Read 1 pull up T 1 T 2 C s Equalize BL T E K 1 K 2 BL T 3 T 4 WL Sense [IC1] Memory Cell SoC - Memory - 21

3 Sense Amplifier Read 0 pull up T 1 T 2 C s Equalize BL T E K 1 K 2 BL T 3 T 4 WL Sense [IC1] Memory Cell SoC - Memory Transistor CMOS SRAM Cell size / density WL speed robustness M5 Q M2 M4 Q M6 M1 M3 BL BL [Rabaey] SoC - Memory - 23

4 ROM Read Only Memory WL i m 0 WL k 1 Programming Programing 0 1 size / density BL 1 BL 2 speed [IC1] robustness SoC - Memory - 24 Floating Gate Transistor Cell Floating gate Gate Source Drain D t ox G t ox n + Substrate p n + S (a) Device cross-section (b) Schematic symbol [Rabaey] SoC - Memory - 25

5 Floating-Gate Transistor Programming 20 V 0 V 5 V 20 V 10 V 5 V 5 V 0 V 2.5 V 5 V S D S D S D Avalanche injection. Removing programming voltage leaves charge trapped. I D Programming results in higher V T. [Rabaey] V wl SoC - Memory - 26 V gs EPROM Memory Flavors [Infineon] SoC - Memory - 27

6 SoC - Memory - 28 Flash Array Organization NOR structure: Individual cell/word select Higher wiring overhead Faster access NAND structure: Multiple cell/word select Higher transistor density Slower access SoC - Memory - 29

7 NAND Operation Read 0 1 Gnd Write 0 1 Gnd Erase 10V 10V 10V 20V 10V Gnd Float Gnd Gnd Gnd Float substrate: 20V SoC - Memory - 30 Flash Array Organization [Infineon] SoC - Memory - 31

8 NROM - Nitride Read Only Memory Basic Principle: Charge stored in ONO Layer (Oxide-Nitride-Oxide) Programming with hot electrons Erase with hot holes [Infineon] Key Features: Non-volatile Very small cell size 2 bits per 1 transistor cell High density products (64M-256M) Fast random access (60 nsec) Slow write/erase SoC - Memory - 32 MRAM Magnetoresistive RAM Basic Principle: Information stored in MTJ Layer (Magnetic Tunnel Junction) Writing thru current direction Sensing resistance of MTJ stack [Univ Texas, TR-02-47] Key Features: Non-volatile 4 Mbit MRAM samples High potential for density and fast access time SoC - Memory - 33

9 On-chip Peripheral Bus (OPB) MHz Access speed Capacity How to Use Memory in System Design CPU Cache Local Bus Fast & Small SRAM Slower & larger (S)DSRAM I/O Subsystem (SCSI, PCI, etc) Disk Tape FAST SLOW LOW HIGH [IC1] SoC - Memory - 34 Memory in System Design: Example PCI-X Bridge MHz 64-bit PCI-X, 33-66MHz 32/64bit PCI 128-bit master, 128-bit slave 266MHz 32/64-bit with ECC DDR266 SDRAM Controller 128 bit PLB Monitor OPB Bridge 128 bit Arb RAM/ROM/ Peripheral controller External bus master cntlr. UART (2) I2C (2) Up to 66MHz 32-bit address / 32-bit data up to 133MHz 128-bit Processor Local Bus (PLB) 128-bit SRAM Ctlr. 128-bit 128KB SRAM 128-bit 128-bit 128-bit DMA Controller GPIO GPIO GPT 32K I-Cache JTAG MMU CPU 32K D-Cache Trace Timers MAL Interrupt Controller 13 external interrupts 1 MII or 2 RMII interfaces 10/100 Ethernet MAC CPU Cache Local Bus Fast & Small SRAM Slower & larger (S)DSRAM I/O Subsystem (SCSI, PCI, etc) Disk Tape SoC - Memory - 35

10 A Minimal Memory System [Gries] SoC - Memory - 36 SDRAM Read Operation Timing [Gries] SoC - Memory - 37

11 SDRAM Read Operation Timing (t CAS ) [Micron] t RCD : row to column delay t RAS : row-access strobe t CAS : column-access strobe t RP : row precharge Timing: t CAS t RCD t RP t RAS SDRAM SoC - Memory - 38 SDRAM Read Operation Timing (t CAS ) [Micron] Access latency: t mem_acc = t RCD + t CAS BW peak = f w Min. row cycle time: t RC = t RAS + t RP BW(burst = n) = SoC - Memory - 39 f w n, n t RC t t mem_acc RC f w n t mem_acc + (n-1), else

12 SoC - Memory - 40 SDRAM Write Operation Timing [Gries] SoC - Memory - 41

13 Product Overview Type Characteristics Remarks Fast page mode DRAM SDRAM DDR SDRAM One row address, many column addresses Burst reads in sync to system clock Double data rate, rising/falling edge Rarely used today Basis of today s DRAM memories Widely used today RAMBUS 400 MHz 16 bit channels Up to 3.2 GBytes/s Embedded DRAM Customized data access Building block for SOC QDR SRAM Double data rate, dual rd/wr port 400 Mbytes/s rd + wr with 4 Bytes granularity SoC - Memory - 42 Enhanced Synchronous DRAM [Gries] SoC - Memory - 43

14 Synchronous DRAM multiple mem banks in/out registers SoC - Memory - 44 Double Data Rate (DDR) SDRAM multiple mem banks in/out registers up/down clock SoC - Memory - 45

15 Synchronous DRAM vs DDR [Gries] SoC - Memory - 46 Multiport DRAM Row Address Column Address Block Address Control Circuitry Block Selector Global Amplifier/Driver I/O Global Data Bus Separate rd/wr addresses, decoders and I/O SoC - Memory - 47

16 Synchronous DRAM vs RAMBUS [RAMBUS] SoC - Memory - 48 Embedded DRAM Pro s: customized size wide data bus multi port high speed Con s: complex technology expensive less density [IBM] SoC - Memory - 49

17 Reliability Soft Errors -particle WL BL n + SiO 2 1 α-particle 1 bit on 50 ff C 3.5 V 1 particle ~ 1 million carriers ~ 2x 10 6 carriers ~ 1.1x 10 6 electrons [Rabaey] SoC - Memory - 50 Memory Yield Yield reduction with growing area due to: Material defects Process variation Yield improvement at const. area due to process maturization [Rabaey] SoC - Memory - 51

18 Redundancy Redundant columns Redundant rows Memory Array Row Address Row Decoder Fuse : Bank [Rabaey] Column Decoder SoC - Memory - 52 Column Address Redundancy and Error Correction Superpositioning of redundancy and error correction substantially improves yield [Rabaey] SoC - Memory - 53

19 Memory Summary Memories are key elements in integrated system design Come in different types with different optimization criteria (size/density, access speed/cycle time, robustness) Dynamic / static / non-volatile memory Memory cell / bank / array structure Single data / burst access Reliability SoC - Memory - 54 References [1] Jan Rabaey: Digital Integrated Circuits: A Design Perspective, Prentice Hall, 2nd Edition, 2003 [2] Stechele/Herkersdorf: Integrierte Schaltungen, Lecture notes, TUM, 2003 [3] IBM photos 3.ibm.com/chips/photolibrary/photo10.nsf/home?ReadForm [4] white papers [5] M. Gries: A Survey of Synchronous RAM Architectures, Swiss Federal Institute of Technology, ETHZ, Technical Report TIK No. 71, 1999 [6] J. Alsmeier, Infineon: Speicherkonzepte, 4. Dresdner Sommerschule Mikroelektronik, September 2003 [7] R. Desikan, University of Texas, Tech Report TR-02-47, Sept SoC - Memory - 55