Chapter 3: ARM Instruction Set [Architecture Version: ARMv4T]

Size: px

Start display at page:

Download "Chapter 3: ARM Instruction Set [Architecture Version: ARMv4T]"

Josephine Green
5 years ago
Views:

1 Chapter 3: ARM Instruction Set [Architecture Version: ARMv4T]

2 A program is the information that you want to convey to CPU / Computing Engine Words ex : Sit, Stand Instruction ex : INC, ADD Sentence Function Paragraph Program High Level English and similar languages. Ex : A= A+B Compiler / Interpreter Medium Level Mnemonics or Assembly language. Ex : ADD A,B Assembler Machine language Ex : 72 ( ) Low Level OPCODE Ex : 72 ( )

3 An instruction is the basic entity of program, using which we convey the information to processor. Different architecture versions support different instruction set. Famous ARM7TDMI family of processors belongs to ARMv4T architecture. ARM7 family of processors normally operates in two states ARM State (32 bit) - 58 instructions Thumb State (16 bit) - 30 instructions Each state has its own set of instructions. Developer has to use them in that state only. In this presentation we will discuss only on instructions of ARM state belonging to ARMv4T ARM7 family of processors is a 32 bit processor with 32 bit registers and 32 bit instructions. i.e., every instruction in ARM processors is 32 bit in ARM state.

$ARM Instruction Syntax {Label} <Instruction>{CC}{S} <Op_Dest>,{Op_Src1},{Op_Src2},{Barrel shifter operation} *CC => Condition *Op_Dest => Operand_Destination *Op_Src => Operand_Source *{} => Optional$

4 ARM Instruction Syntax {Label} <Instruction>{CC}{S} <Op_Dest>,{Op_Src1},{Op_Src2},{Barrel shifter operation} *CC => Condition *Op_Dest => Operand_Destination *Op_Src => Operand_Source *{} => Optional content - Suffix S to any instruction updates the flags in CPSR Ex : ADDEQS Rd, Rn, Rm, LSL #2 i.e., Rd = Rn + Rm * 4 If Z=1 Else Rd = Rd Conditional Execution Suffix Tested Status Flags Description EQ Z set Equal NE Z clear Not equal CS/HS C set Unsigned higher or same CC/LO C clear Unsigned lower MI N set Negative PL N clear Positive or zero

HI C set and Z clear Unsigned higher LS C clear or Z set Unsigned lower or same GE N equals V Signed greater or equal LT N not equal to V Signed less than GT Z clear AND (N equals V) Signed greater

5 HI C set and Z clear Unsigned higher LS C clear or Z set Unsigned lower or same GE N equals V Signed greater or equal LT N not equal to V Signed less than GT Z clear AND (N equals V) Signed greater than LE Z set OR (N not equal to V) Signed less than or equal Barrel Shifter Operation Shift Operation Logical Shift Left by immediate Logical Shift Left by register Logical Shift Right by immediate Logical Shift Right by register Arithmetic Shift Right by immediate Arithmetic Shift Right by register Rotate Right by immediate Rotate Right by register Rotate Right with Extend Syntax Rm, LSL #shift_imm Rm, LSL Rs Rm, LSR #shift_imm Rm, LSR Rs Rm, ASR #shift_imm Rm, ASR Rs Rm, ROR #shift_imm Rm, ROR Rs Rm, RRX

6 Classification of instructions 1. Data Processing Instruction - Data movement, Arithmetic, Logical, Comparison, Multiply 2. Branch instructions 3. Load Store instructions 4. Single register, Multiple register, Stack operations, Swap 5. Software interrupt instructions 6. Program Status Register instructions 7. Coprocessor Instructions 8. Loading Constants 1. Data movement instructions Syntax : <Instruction> {<cond>}{s} Rd, N Instruction : MOV Rd = N MVN Rd = ~N - S suffix with MOVE operations can update the C, Z - N can be register or immediate data - MOV/MVN instruction without barrel shifter operations Example1 : R1 = 0x R0 = 0x MOV R1, R0 R1 = 0X R0 = 0X Example2 : R1 = 0x MOV R1, #0x04 R1 = 0X Example3 : R1 = 0x R0 = 0x MVN R1, R0 R1 = 0XFFFFFFFB R0 = 0X Example4 : R1 = 0x R0 = 0x MOV R1, R0, LSR #1 R1 = R0 = 0x Example5 : R1 = 0x R0 = 0x MVN R1, R0, LSR #1 R1 = R0 = 0x

7 2. Arithmetic Instructions Syntax : <Instruction>{<cond>}{S} Rd, Rn, N Instruction : ADD Rd = Rn + N ADC SUB Rd = Rn + N + C Rd = Rn N SBC Rd = Rn N -!C RSB Rd = N Rn RSC Rd = N Rn -!C ADD, SUB, RSB instruction(without carry) Example1 : ADD R2, R1, R0 R2 = 0x R1 = 0x R0 = 0x Example2 : SUB R2, R1, R0 R2 = 0x R1 = 0x R0 = 0x Example3 : RSB R2, R1, R0 R2 = R1 = 0x R0 = 0x ADC, SBC, RSC instruction (with carry) Example4 : C = 1 ADC R2, R1, R0 R2 = 0x R1 = 0x R0 = 0x Example5 : C = 0 SBC R2, R1, R0 R1 = 0x R0 = 0x Example6 : R1 = 0x R0 = 0x C=0 RSC R2, R1, R0 R2 = R1 = 0x R0 = 0x

8 ADD, SUB instruction(with barrel shifter operation) Example6 : ADD R2, R1, R0, LSL #1 R2 = R1 = 0x R0 = 0x Example7 : R0 = 0x SUB R2, R1, R0, LSR #1 R2 = R1 = 0x R0 = 0x ADD with condition execution and suffix S Example7 : ADDEQS R2, R1, R0, LSL #1 R2 = 0x A if Z=1 else 0x and CPSR is updated Example8 : ADDS R2, R1, R0, LSL #1 R2 = 0x A and CPSR is updated

9 3. Logical instructions Syntax Instruction : <Instruction> {<cond>}{s} Rd, Rn, N : Bitwise logical operations Sno Instruction Syntax Description Operation 1 AND AND Rd, Rn, N Logical AND Rd = Rn & N 2 ORR ORR Rd, Rn, N Logical OR Rd = Rn N 3 EOR EOR Rd, Rn, N Logical XOR Rd = Rn ^ N 4 BIC BIC Rd, Rn, N Logical Bit clear Rd = Rn &~N AND, ORR, XOR instruction Example1 : R1 = 0x R0 = 0x F AND R2, R1, R0 R2 = 0x R1 = 0x R0 = 0x F Example2 : R1 = 0x R0 = 0x F ORR R2, R1, R0 R2 = 0x F R1 = 0x R0 = 0x F Example3 : R1 = 0x R0 = 0x F EOR R2, R1, R0 R2 = 0x E R1 = 0x R0 = 0x F BIC instruction Example4 : R1 = 0x R0 = 0x F BIC R2, R1, R0 R1 = 0x R0 = 0x F Example5 : R1 = 0x R0 = 0x F BICS R2, R1, R0 and Z = 1 R1 = 0x R0 = 0x F

10 ORR, EOR instruction with barrel shifter operation Example6 : R1 = 0x R0 = 0x F ORR R2, R1, R0, LSL #1 R2 = 0x F R1 = 0x R0 = 0x F Example7 : R1 = 0x R0 = 0x F EOR R2, R1, R0, LSL #1 R2 = 0x F R1 = 0x R0 = 0x F

11 4. Comparison instructions Syntax Instruction : <Instruction>{cond} Rn, N :TST is logical AND and TEQ is a logical XOR operation Sno Instruction Syntax Description Operation 1 CMP CMP Rn, N Compare Rn N 2 CMN CMN Rn, N Compare negate Rn + N 3 TST TST Rn, N Test bits Rn & N 4 TEQ TEQ Rn, N Test for equality Rn ^ N - Updates CPSR only without affecting the register content and these can be used in conditional execution CMP, CMN, TST instruction Example1 : CPSR_nzcv CMP R1, R0 CPSR_nzCv Example2 : CPSR_nzcv CMN R1, R0 CPSR_nzcv Example3 : CPSR_nzcv TST R1, R0 CPSR_nZcv TEQ instruction without & with barrel shifter operations Example4 : CPSR_nzcv TEQ R1, R0 CPSR_nzcv Example5 : R0 = 0x CPSR_nzcv TEQ R1, R0, LSL #1 CPSR_nZcv R0 = 0x

12 5. Multiply instructions Multiply instructions uses MAC unit hence they are not associated with the Barrel shifter operations Operands has to be in the register. i.e., immediate operands are not supported Syntax : MUL{cond} Rd, Rm, Rn MLA{cond} Rd, Rm, Rn, Rs Instruction : For 32 bit resultant operations Sno Instrn Syntax Description Operation 1 MUL MUL Rd, Rm, Rn Multiply Rd=Rm*Rn 2 MLA MLA Rd, Rm, Rn, Rs Multiply and accumulate Rd=Rm*Rn + Rs MUL, MLA instruction Example1 : MUL R2, R1, R0 R2 = 0x C Example2 : R3 = 0x R2 = 0x R0 = 0x MLA R3, R2, R1, R0 R3 = 0x E R2 = 0x R0 = 0x

13 Syntax : UMULL {cond} RdLo, RdHi, Rm, Rn UMLAL {cond} RdLo, RdHi, Rm, Rn Instruction : For 64 bit resultant operations Sno Instruction Syntax Description Operation 1 UMULL UMULL RdLo, RdHi, Rm, Rn 2 UMLAL UMLAL RdLo, RdHi, Rm, Rn Unsigned Multiply Long Unsigned Multiply and accumulate Long [RdHi, RdLo]=Rm*Rn [RdHi, RdLo]=[RdHi, RdLo]+(Rm*Rn) UMULL, UMLAL calculations R3 = 0x R2 = 0x R1 = 0xF R0 = 0x UMULL R3,R2,R1,R0 = 0x1E => R1*R0 R1*R0 = 0x1E [R3,R2] = 0x UMLAL R3,R2,R1,R0 = 0x1E => [R3,R2]+R1*R0 UMULL, UMLAL instruction Example3 : R3 = 0x R1 = 0xF R0 = 0x UMULL R3, R2, R1, R0 R3 = 0xE R2 = 0x R1 = 0xF R0 = 0x Example4 : R3 = 0x R1 = 0xF R0 = 0x UMLAL R3, R2, R1, R0 R3 = 0xE R2 = 0x R1 = 0xF R0 = 0x

14 Syntax : SMULL {cond} RdLo, RdHi, Rm, Rn SMLAL {cond} RdLo, RdHi, Rm, Rn Instruction : For 64 bit resultant signed operations Sno Instruction Syntax Description Operation 1 SMULL SMULL RdLo, RdHi, Rm, Rn Signed Multiply Long [RdHi, RdLo]=Rm*Rn 2 SMLAL SMLAL RdLo, RdHi, Rm, Rn, Rs Signed Multiply and accumulate Long [RdHi, RdLo]=[RdHi, RdLo]+(Rm*Rn)

15 6. Branch instructions Syntax : <instruction>{cond} label Instruction : Branch instructions alter the execution flow Sno Instruction Syntax Description Operation 1 B B label Branch PC = Label 2 BL BL label Branch with link LR = PC PC = Label 3 BX BX Rm Branch Exchange PC = Rm & 0xfffffffe, T = Rm & 1 4 BLX BLX Rm Branch Exchange with link LR = PC PC = Rm & 0xfffffffe, T = Rm & 1 B / BX instruction are similar to JUMP instructions and the maximum possible jump is 32MB BL / BLX instruction are similar to CALL instructions and hence they support subroutine. Return from subroutine is done using instruction MOV PC, LR BX / BLX instructions are widely used to change the state of the processor from ARM to THUMB and vice versa BLX instruction also supports label Ex : BLX Label Example1 : R0 = 0x CPSR_nzcvt BX R0 CPSR_nzcvT

16 7. Program Status Register instructions Syntax : <instruction>{cond} Rd, <CPSR / SPSR> Instruction : Read / write operation on CPSR / SPSR Sno Instruction Syntax Description Operation 1 MRS MRS Rd, CPSR Copy CPSR to GPR Rd = CPSR 2 MSR MSR CPSR_F, Rd Copy GPR to CPSR_Field CPSR_F = Rd CPSR_F => CPSR_Flags [24:31] CPSR_S => CPSR_Status [16:23] CPSR_E => CPSR_Extention [8:15] CPSR_C => CPSR_Control [0:7] On reset, Processor Mode = Supervisor(10011) Processor State = ARM state(t=0) Interrupts = Disabled(I=F=1) Hence, CPSR_C = 0xD3 ( ) Default value of CPSR = 0x000000D3 MRS, MSR instruction Example1: R3 = 0x CPSR=0x000000D3 MRS R0, CPSR R0 = 0x000000D3 CPSR=0x000000D3 Example2: R3 = 0xF CPSR=0x000000D3 MSR CPSR_F, R0 CPSR=0xF00000D3 R0 = 0xF MSR instruction also supports immediate value and writing to CPSR is possible only in privileged modes

17 8. Load and Store instructions [ Single Register Transfer ] STORE LOAD RAM memory address RAM memory content 0x x x x x x x x x

18 Syntax Instruction : <instruction> {<cond>} Rd, addressing : These are the only instructions that works on the memory. - LDR instruction copies memory content to the register - STR instruction copies register content to the memory and it is the only instruction having source operand before the destination operand. - Point to remember, Memory is byte aligned and registers are word(32bit) size - There are 8 possible load and store instructions, - 6 instructions for loading and storing of a unsigned word, half-word and byte values - 2 instruction for loading signed byte and half-word values - No load / Store instructions affects CPSR - No need of signed extension in the store instruction as memory is byte aligned - LDRSB / LDRSH are the only two sign extension instruction all other instruction append zero to the left of the number hence they are un-singed Sno Instn Description Syntax Operation 1 LDR Load a word from memory into register 2 STR Store a word from register into the memory LDR R0,[R1] R0 = memory32[r1] STR R0,[R1] memory32[r1] = R0 3 LDRB Load a byte from memory into register 4 STRB Store a byte from register content into the memory LDRB R0,[R1] STRB R0,[R1] R0 = memory8[r1] memory8[r1]=r0 5 LDRH Load a half-word from memory into register 6 STRH Store a half-word from register content into the memory 7 LDRSB Load a signed byte from memory into register 8 LDRSH Load a signed half-word from memory into register LDRH R0,[R1] R0 = memory16[r1] STRH R0,[R1] memory16[r1] = R0 LDRSB R0,[R1] R0 = Sign extended memory8[r1] LDRSH R0,[R1] R0 = Sign extended memory16[r1]

- Load a word to register R0 from RAM memory location 0x40000000 31 01 R0 Mem32[0x40000000] =0x33221100 LDR and STR instruction Example1:

19 - Load a word to register R0 from RAM memory location 0x R0 Mem32[0x ] =0x LDR and STR instruction Example1: memory32[r1] = 0x LDR R0, [R1] R0 = 0x memory32[r1] = 0x Example2: memory32[r1] = 0x STR R0, [R1] memory32[r1] = 0x

20 LDRH and STRH instruction Example3 : R1 = 0x memory16[r1] = 0x2211 LDRH R0, [R1] R0 = 0x R1 = 0x memory16[r1] = 0x2211 Example4 : R1 = 0x memory16[r1] = 0x2211 STRH R0, [R1] R1 = 0x memory16[r1] = 0x7766 LDRB and STRB instruction Example5 : R1 = 0x memory8[r1] = 0x11 LDRB R0, [R1] R0 = 0x R1 = 0x memory8[r1] = 0x11 Example6 : R1 = 0x memory8[r1] = 0x11 STRB R0, [R1] R1 = 0x memory8[r1] = 0x66 LDRSH, LDRSB instruction (MSB/Sign bit gets extended to 32 bit) Example7 : memory32[r1] = 0x LDRSH R0, [R1] R0 = 0xFFFF8877 memory32[r1] = 0x Example8 : memory32[r1] = 0x LDRSB R0, [R1] R0 = 0x memory32[r1] = 0x

21 Index methods Index Method Data Base address register Example Post-index Mem[base] Base + offset LDR R0,[R1],#4 Pre-index Mem[base+offset] Not updated LDR R0,[R1,#4] Pre-index with write-back Mem[base+offset] Base + offset LDR R0,[R1,#4]! Addressing modes for Post-indexing methods: Addressing Modes Data Base address register Example Immediate Mem[base] Base + offset LDR R0,[R1],#+4 Register Mem[base] Base + offset LDR R0,[R1],+R2 Register scaled Mem[base] Base + offset LDR R0,[R1],+R2,LSL #2 Same addressing modes are also applicable for Pre-indexing methods - Barrel shifter operations / Register scaled addressing mode is not supported by singed byte load instructions (LDRSB/LDRSH) and half-word load / store instructions (LDRH/STRH) - Offset can be + (positive) / - (Negative) - Pre-index method is used in accessing elements in the data structure. Post and Preindexing with write back is used in traversing the array LDR and STR instruction with post index Example9 : memory32[r1] = 0x LDR R0,[R1],#4 R0 = 0x R1 = 0x memory32[r1] = 0x Example10 : memory32[r1] = 0x STR R0,[R1],#4 R1 = 0x memory32[0x ] = 0x

22 LDR with pre-index and pre-index with write back Example11 : memory32[r1] = 0x memory32[r1+4]=0x LDR R0,[R1,#4] R0 = 0x memory32[r1] = 0x Example12 : memory32[r1] = 0x memory32[r1+4]=0x LDR R0, [R1,#4]! R0 = 0x R1 = 0x memory32[r1] = 0x STR with pre-index and pre-index with write back Example13 : memory32[r1] = 0x memory32[r1+4]=0x STR R0,[R1,#4] memory32[0x ] = 0x Example14 : memory32[r1] = 0x memory32[r1+4]=0x STR R0, [R1,#4]! R1 = 0x memory32[r1] = 0x LDR instruction pre-index with write-back using Register and Register scaled addressing modes Example15 : R2 = 0x memory32[r1] = 0x memory32[r1+4]=0x LDR R0,[R1,+R2]! R0 = 0x R1 = 0x memory32[r1] = 0x Example16 : R2 = 0x memory32[r1] = 0x memory32[r1+4]=0x LDR R0, [R1,+R2,LSL #1]! R0 = 0x R1 = 0x memory32[r1] = 0x

23 9. Load and Store instructions - [ Multiple Register Transfer ] Advantage : Load / Store multiple values in a single instruction Dis-advantage : Increased Interrupt latency Syntax : <instruction>{cc}<addressing_mode> Rn{!},<Register/s>! => Write back / update Rn address Registers Addressing modes => {Rn Rm} OR {Rn, Ro, Rp, Rm} => Help to trace through the memory locations / registers Sno Instruction Description 1 LDM Load multiple words from memory into registers 2 STM Store multiple words from registers into the memory Addressing methods: Addressing Modes Data Start Address End address Rn! IA Increment Rn Rn+4*N-4 Rn+4*N IB Increment Rn+4 Rn+4*N Rn+4*N DA Decrement Rn-4*N+4 Rn Rn-4*N DB Decrement Rn-4*N Rn-4 Rn-4*N N => Number of Registers Rn => Base Register Store Multiple STMIA Load Multiple LDMDB STMIB LDMDA STMDA LDMIB STMDB LDMIA

24 R1=0x C mem[0x ]=0x mem[0x ]=0x mem[0x ]=0xbbaa9988 mem[0x c]=0xffeeddcc R0=0x R0=0x R1=0x C R2=0x R3=0x R4=0x mem[0x ]=0x mem[0x ]=0x mem[0x ]=0xbbaa9988 mem[0x c]= 0Xffeeddcc Example18 : LDMIA R0!,{R2-R4} R0=0x C R2=0x R3=0x R4=0xBBAA9988 Example19 : LDMIB R0!,{R2-R4} R0=0x C R2=0x R3=0xBBAA9988 R4=0xFFEEDDCC Example20 : LDMDA R1!,{R2-R4} R1=0x R2=0x R3=0xBBAA9988 R4=0xFFEEDDCC Example21 : LDMDB R1!,{R2-R4} R1=0x R2=0x R3=0x R4=0xBBAA9988

25 R0=0x R1=0x C R2=0x R3=0x R4=0x mem[0x ]=0x mem[0x ]=0x mem[0x ]=0xbbaa9988 mem[0x c]= 0xFFEEDDCC Example22 : STMIA R0!,{R2-R4} R0=0x C mem[0x ]=0x mem[0x ]=0x mem[0x ]=0x Example23 : STMIB R0!,{R2-R4} R0=0x C mem[0x ]=0x mem[0x ]=0x mem[0x c]=0x Example24 : STMDA R1!,{R2-R4} R1=0x mem[0x ]=0x mem[0x ]=0x mem[0x c]=0x Example25 : STMDB R1!,{R2-R4} R1=0x mem[0x ]=0x mem[0x ]=0x mem[0x ]=0x

26 10. Stack operations - There are no specific stack instructions like PUSH and POP in ARM. LDM and STM instructions with proper addressing modes are used to do stack operations. - Stack can grown up / down in memory i.e., it can Ascending(A) / Descending(D) - Stack pointer can point to last Filed(F) / Empty(E) memory location - Monitoring the stack over flow / under flow is the programmers responsibility Addressing Modes Descriptions POP =LDM PUSH =STM FA Full Ascending LDMFA LDMDA STMFA STMIB FD Full Descending LDMFD LDMIA STMFD STMDB EA Empty Ascending LDMEA LDMDB STMEA STMIA EB Empty Descending LDMEB LDMIB STMEB STMDA FA => F => Full i.e., Stack pointer is pointing to the last filled/used memory location A => Ascending i.e., Stack memory grows up in memory Examples are similar to LDM / STM instructions. A change is addressing mode with base address register i.e., SP in this case

27 11. Swap Instructions This instruction exchanges a word between a register and memory. Example: : R0=0x R1=0x R2=0x Mem32[0x ]=0x SWP R0,R1,[R2] ;R0=[R2], [R2]=R1, R1=unchanged : R0=0x R1=0x Mem32[0x ]=0x These instructions exchanges a word between a register and memory. - These are an atomic operation i.e., it can not be interrupted by any other instruction. Syntax : SWP{B}{<cond>} Rd, Rm, [Rn] Sno Instrn Description Example Operations 1 SWP swap a word between memory and a register SWP R0,R1,[R2] R0 = mem32[r2] mem32[rn] =R1 R1 = R1 2 SWPB swap a byte between memory and a register SWPB R0,R1,[R2] R0 = mem8[r2] mem8[r2] =R1 R1 = R1

28 Example26: : R0=0x R1=0x R2=0x Mem32[0x ]=0x SWP R0,R1,[R2] : R0=0x Software R1=0x Interrupt Instruction Mem32[0x ]=0x Example27: : R0=0x R1=0x R2=0x Mem32[0x ]=0x SWPB R0,R1,[R2] : R0=0x R1=0x Mem32[0x ]=0x

$forces to change the system mode to supervisory mode - It sets the PC to 0x08 in the vector table Syntax : SWI{<cond>} SWI_number Sno Instrn Description Example Operations 1 SWI Softer Interrupt SWI$

29 12. Software Interrupt Instruction - It is a software exceptions that provides a mechanism for calling operating system routine - Every SWI instruction is associated with user defined SWI_number - It forces to change the system mode to supervisory mode - It sets the PC to 0x08 in the vector table Syntax : SWI{<cond>} SWI_number Sno Instrn Description Example Operations 1 SWI Softer Interrupt SWI 0x LR = 0x {i.e., present PC vlue} CPSR = nzcvqift_svc SPSR = nzcvqift_user PC = 0x R0 = 0x12 SWI_handler STMFD sp!, {r0-r12, lr} LDR r10, [lr, #-4] ; Store registers r0-r12 and the link register ; Read the SWI instruction BIC r10, r10, #0xff ; Mask off top 8 bits BL service_routine ; r10 contains the SWI number & Branch to service routine with link LDMFD sp!, {r0-r12, pc} ; Return from SWI handler

30 13. Co-processor Instructions Co-processors are used with ARM processor core for, Expanding the computation ability(floating point) Expanding the controlling ability (Memory Management) Most of the instructions are co-processor specific but, some instructions works between ARM processor core and co-processor. Few of them are mentioned below, Instruction CDP MRC / MCR LDC / STC Description Coprocessor data processing perform an operation in a coprocessor Coprocessor register transfer move data to/from coprocessor registers Coprocessor memory transfer load and store blocks of memory to/from a coprocessor Syntax: CDP{<cond>} cp, opcode1, Cd, Cn {, opcode2} <MRC MCR>{<cond>} cp, opcode1, Rd, Cn, Cm {, opcode2} <LDC STC>{<cond>} cp, Cd, addressing *cp => Co-processor number p0 to p15 *Opcode1 => Operations to take place on co-processor *Cd => Co-processor destination register *Cn => Co-processor primary register *Cm => Co-processor secondary register/extended register *Opcode2 => Secondary register modifier Example : Co-processor 15(P15) is called as system control coprocessor, such as memory management, write buffer control, cache control, and identification registers. It has a register-c0 which contains coprocessor identification number. Copy the content of register-c0 from co-processor P15 to r10 of ARM processor. MRC p15, 0, r10, c0, c0, 0

31 14. Loading constants There is no ARM instruction that moves 32bit constant value to the register. This is because, ARM instructions are 32 bit in size and hence they can not encode 32bit value in an instruction. In general maximum immediate value that we can move to register using MOV instruction is 8 bit value i,e, 0xFF Ex : 1. MOV R0,#0x000000FF works 2. MOV R0,#0xFFFFFFFF does not works One method of making ex:2 possible is by using MVN instruction i.e., MVN R0,#0x Other method is to use pseudo instructions like LDR Pseudo-instruction Actual instruction LDR r0, =0xff MOV r0, #0xff LDR r0, =0x LDR r0, [pc, #offset_12] ADR r7, lable ADD r7, pc, #offset * We can observe this in dis-assembler Syntax: LDR Rd, =constant ADR Rd, label Sno Instruction Description Operation 1 LDR Load constants Rd=32 bit value 2 ADR Load address Rd=32-bit relative address Ex : 1 ADR r7,stop MOV R7,#0x MOV R2,#0x000000ff STOP B STOP Ex : 2 LDR r0, [pc, #constant_number-8-{pc}] MOV R7,#0x MOV R2,#0x000000ff constant_number DCD 0x

LDR, LDRH, LDRB, LDM STR, STRH, STRB, STM SWP, SWPB LDRSB, LDRSH, MOV, MVN, LDR, ADR, MRS, MSR AND, ORR, EOR, BIC, ADD, ADC, SUB, SUB BRS B,RS C CMP, CMN, TST, TEQ, B,BL,BX,BLX MUL, MLA UMULL, UMLAL

32 LDR, LDRH, LDRB, LDM STR, STRH, STRB, STM SWP, SWPB LDRSB, LDRSH, MOV, MVN, LDR, ADR, MRS, MSR AND, ORR, EOR, BIC, ADD, ADC, SUB, SUB BRS B,RS C CMP, CMN, TST, TEQ, B,BL,BX,BLX MUL, MLA UMULL, UMLAL SMULL, SMLAL SWI CDP, MRC, MCR, LDC, STC 1. Data Processing instructions(22) ARM instruction classification Data Movement(2) Logical(4) Arithmetic(6) Compare(4) Multiply(6) : MOV, MVN : AND, ORR, EOR, BIC : ADD, ADC, SUB, SUBB, RSB, RSC : CMP, CMN, TST, TEQ : MUL, MLA, UMULL, UMLAL, SMULL, SMLAL 2. Branch(4) : B, BL, BX, BLX 3. Load-Store(12) : LDR, STR, LDRH, STRH, LDRB, STRB, LDRSB, LDRSH, LDM, STM, SWP, SWPB 4. Software interrupt(1) : SWI 5. Program Status(2) : MSR, MRS 6. Co-processor (5) : CDP, MCR, MRC, LDC, STC 7. Loading constants(2) : LDR, ADR Total number of instructions: 48

The ARM Instruction Set

The ARM Instruction Set Minsoo Ryu Department of Computer Science and Engineering Hanyang University msryu@hanyang.ac.kr Topics Covered Data Processing Instructions Branch Instructions Load-Store Instructions