Introduction to C. Write a main() function that swaps the contents of two integer variables x and y.

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1 Introduction to C Write a main() function that swaps the contents of two integer variables x and y. void main(void){ int a = 10; int b = 20; a = b; b = a; } 1

2 Introduction to C Write a main() function that swaps the contents of two integer variables x and y. void main(void){ int a = 10; int b = 20; int temp; temp = a a = b; b = temp; } 2

3 Introduction to C Can it be done without a third variable? void main(void){ int a = 10; int b = 20; int temp; temp = a a = b; b = temp; } 3

4 Introduction to C Can it be done without a third variable? void main(void){ int a = 10; int b = 20; int temp; temp = a } a = b; b = temp; Arithmetic solution (+ -) Logical solution (xor) 4

5 Introduction to C Can we package the swapping code in a function? void main(void){ } int a = 10; int b = 20; int temp; temp = a a = b; b = temp; 5

6 Ch.3 The ARM Cortex-M MCU(s) 6

7 Text sections 3.1 ARM Cortex-M Architecture 7

8 What is ARM? The ARM architectures are reduced instruction set computer (RISC) instruction set architectures (ISA), developed by British company ARM Holdings, who have designed and licensed a family of computer processors that use these instruction set architectures; The 32-bit architecture was first developed in the 1980s by Acorn Computers Ltd to power their desktop machines and subsequently spun off as a separate company, now ARM Holdings. The name was originally an acronym for Acorn RISC Machine and subsequently, after the name Acorn was dropped, Advanced RISC Machine. Globally, as of 2013, it is the most widely used 32-bit ISA in terms of quantity produced. In 2010 alone, producers of chips based on ARM architectures reported shipments of 6.1 billion ARM-based processors, representing 95% of smartphones, 35% of digital televisions and set-top boxes and 10% of mobile computers. 8

9 CISC v. RISC Complex instruction set computers (CISC) Early computers offered CPUs that were much faster than available memories. Fetching instructions limited performance A single complex instruction could perform many operations Example: Find the zeros of a polynomial Complex instructions require many processor clock cycles to complete A program running on a CISC computer employed a relatively small number of complex instructions High code density 9

10 CISC v. RISC Reduced Instruction Set Computers (RISC) Memories match CPU speed No large penalty for instruction fetch Instructions simplified Load, store, operations only on data already in registers Single processor clock cycle per instruction A program running on a RISC computer employs a relatively larger number of simplified instructions Reduced code density 10

11 What is ARM? The ARM architecture is a Reduced Instruction Set Computer (RISC) architecture, as it incorporates these typical RISC features: A uniform register file load/store architecture, where data processing operates only on register contents, not directly on memory contents. Simple addressing modes, with all load/store addresses determined from register contents and instruction fields only. Pipelining effectively provides single cycle operation for many instructions. Overview of 11

12 M3 vs. M4 240 system interrupts with individual priorities (from only 32 in M0, M0+, M1), and one NMI M4F Overview of 12

13 M3/M4 NVIC = Nested Vectored Interrupt Previous ARM cores all used external interrupt controllers! Controller 13

14 Cortex-M3/M4 have a Harvard Microcontroller Architecture PPB Arm Cortex TM -M3 processor System bus Input ports Internal NVIC peripherals Output ports ICode bus Instructions Flash ROM DCode bus Data RAM Table source: 14

15 Cortex-M registers Either data or addresses General purpose registers Stack pointer Link register Program counter Register file R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 (MSP) R14 (LR) R15 (PC) Special registers PSR PRIMASK FAULTMASK BASEPRI CONTROL R13 (PSP) Program status register Exception mask registers CONTROL register MSP MAIN STACK POINTER PSP PROCESS STACK POINTER 15

16 Program Status Registers: Application, Interrupt, Execution APSR IPSR EPSR N Z C V Q 31 0 Reserved Reserved ICI/IT T Reserved Reserved ICI/IT 8 ISR_NUMBER Reserved PSR N Z C V Q ICI/IT T Reserved ICI/IT ISR_NUMBER ICI = Interruptible-Continuable Instruction info. (Load/Store Multiple) IT = If-Then block info. Can be accessed either individually (xpsr), or collectively (PSR)

17 Condition Codes Bit Name Meaning (after +, -, *, / ) N negative result is negative Z zero result is zero V overflow signed overflow C carry unsigned overflow Q saturation saturation has occurred in one of the saturation instructions (e.g. SSAT, USAT see Sec.5 of the Cortex-M3/M4F Instruction Set) 17

18 QUIZ: How are the flags N, Z, C, V set after this addition?

19 QUIZ: How are the flags N, Z, C, V set after this addition?

MEMORY MAPS LM3S1968 LM4F120 256k Flash ROM 64k RAM I/O ports Internal I/O PPB 0x0000.

20 MEMORY MAPS LM3S1968 LM4F k Flash ROM 64k RAM I/O ports Internal I/O PPB 0x x0003.FFFF 0x x2000.FFFF 0x x41FF.FFFF 0xE xE004.0FFF 20

21 Endianness Address 0x x The 16-bit number 1000 Data 0x03 0xE8 Big Endian Address 0x x Data 0xE8 0x03 Little Endian The 32-bit number 305,419,896 Address Data Address Data 0x x12 0x x78 0x x34 0x x56 0x x56 0x x34 0x x78 0x x12 Big Endian Little Endian ENDIANESS: BIG ENDIAN MSB STORED IN SMALLEST ADDRESS LITTLE ENDIAN LSB STORED IN SMALLEST ADDRESS CORTEX-M3/M4 USE LITTLE ENDIAN EOL1 21

22 QUIZ: C What is the rule for generating this sequence: ? Write a main() function that calculates the sum of the first twenty members of the sequence. 22

23 Doubly-tricky QUIZ We re visualizing the memory contents of a microcontroller. What number is stored in the 4-Byte word that starts at 0x0000D4? 23

24 QUIZ 1. How many registers are in the Cortex-M register file? 2. How may of those are general-purpose registers? 3. What is the meaning of general-purpose? 4. Explain the function of the LR and PC. 5. What is the function of the APSR? Explain briefly each of its 5 bits (flags). 6. The value stored in the 4 MSB of APSR is 0xD. Explain what this means. 24

Cortex-M registers Either data or addresses General purpose registers Stack pointer Link register Program counter Register file R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11

25 Cortex-M registers Either data or addresses General purpose registers Stack pointer Link register Program counter Register file R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 (MSP) R14 (LR) R15 (PC) Special registers PSR PRIMASK FAULTMASK BASEPRI CONTROL R13 (PSP) Program status register Exception mask registers CONTROL register 25

26 Not in text What is THUMB? APSR IPSR EPSR N Z C V Q 31 0 Reserved Reserved ICI/IT T Reserved Reserved ICI/IT 8 ISR_NUMBER Reserved PSR N Z C V Q ICI/IT T Reserved ICI/IT ISR_NUMBER Can be accessed either individually, or collectively under the name PSR 26

Thumb-2 gives approximately 26% improvement in code density over ARM Thumb-2 gives approximately 25%

27 The Thumb-2 instruction set Variable-length instructions ARM instructions are a fixed length of 32 bits Thumb instructions are a fixed length of 16 bits Thumb-2 instructions can be either 16-bit or 32-bit Thumb-2 gives approximately 26% improvement in code density over ARM Thumb-2 gives approximately 25% improvement in performance over Thumb Cortex M3/M4 have only the Thumb-2 mode! (T bit in EPSR must always be 1) 27

28 ARM 32-BIT INSTRUCTION FORMAT 28

29 THUMB INSTRUCTION SET FORMAT 29

30 THUMB ARM TRANSLATION (performed in the hardware) 30

31 Thumb, Thumb-2, and Thumbnail The Cortex-M3/M4 use only the Thumb-2 instruction set (no 32-bit pure ARM) The Thumb-2 instruction set is a composite of both 32- bit ARM instructions and the restrictive 16-bit Thumb instructions Thumb-2 improves code density in comparison with the ARM instruction set, but it is virtually as fast as ARM In our class, we use only a subset of 30 Thumb-2 instructions, listed in Appendix 4. The author calls this subset Thumbnail. 31

32 Cortex-M3/M4 Operating Modes Thread mode is the foreground operating context This is the context in which the main program and associated subroutines operate ISR_NUMBER in IPSR is 0 Handler mode is the background operating context This is the context in which the ISRs operate Both operating modes employ the MSP EE 319K - Bard, Valvano, and Yerraballi 32

Typo in Sec. 3.1.2 Reset: Thread (a.k.a. foreground) mode is unprivileged!

33 Typo in Sec Reset: Thread (a.k.a. foreground) mode is unprivileged! Source: ARM Cortex-M3 Introduction by ARM University Relations (linked on course webpage) 33

34 Text sections 3.2 Software Development 3.3 Cortex-M3/M4 Assembly Language 34

35 SW Development Environment Editor Keil TM uvision Source code Start ; direction register LDR R1,=GPIO_PORTD_DIR_R LDR R0,[R1] ORR R0,R0,#0x0F ; make PD3-0 output STR R0, [R1] Start Debug Session Simulated Microcontroller Processor Memory I/O Build Target (F7) Object code 0x x x F040000F 0x A 6008 Address Data Download Real Microcontroller Start Debug Session Processor Memory I/O 35

36 SW Development Environment Re-read Sections 2.3, 2.4,

37 Conventions used in representing Thumbnail instructions Ra Rd Rm Rn Rt represent 32-bit registers value any 32-bit value: signed, unsigned, or address {S} if present, instr. sets condition codes (NZCV) #im12 any value from 0 to 4095 #im16 any value from 0 to {Rd,} if present Rd is destination, otherwise Rn {cond} optional logical condition (see Table 3.2) label any address within the ROM op2 the value generated by <op2> {, shift} optional shift of a register {, off} optional offset applied to a register 37

38 Examples Is this imm12 or imm16? ADD R0, #42 ADD R0, R1, #42 ADD R2, R1, R12 ADDS R5, R5, #25 ADDEQ R10,R11,R12 ADC R5, R1, R3 ;add w/carry Can we apply both {S} and {cond} in the same instruction? No! 38

39 Multi-word addition ADDS R4, R0, R2 ;Add the least significant words. ADC R5, R1, R3 ;Add most significant words w/ carry. To be continued in the lab EOL2 39

40 Cortex-M3/M4 assembly language Label Opcode Operands Comment INIT MOV R0, #100 ;set table size Comments should explain why or how should not explain the opcode and its operands are a major component of self-documenting code 40

41 Conditional execution ADD R0, #42 ADD R0, R1, #42 ADD R2, R1, R12 ADDS R5, R5, #25 ADDEQ R10,R11,R12 ADC R5, R1, R3 ;add w/carry 41

42 Conditions for conditional execution Suffix Flags Meaning Condition Code Suffixes Unsigned 1) Put first value in register 2) CMPS second value 3) EQ NE HI HS LO BLS Signed 1) Put first value in register 2) CMPS second value 3) EQ NE GT GE LT LE Logical 1) Put first value in register 2) ANDS ORRS EORS, ORNS 3) EQ NE EQ Z = 1 Equal NE Z = 0 Not equal CS / HS C = 1 Higher or same, unsigned CC / LO C = 0 Lower, unsigned < MI N = 1 Negative PL N = 0 Positive or zero VS V = 1 Overflow VC V = 0 No overflow HI C = 1 and Z = 0 Higher, unsigned > LS C = 0 or Z = 1 Lower or same, unsigned GE N = V Greater than or equal, signed LT N V Less than, signed < GT Z= 0 and N = V Greater than, signed > LE Z=1 and N V Less than or equal, signed AL Can have any value Always. This is the default when no suffix is specified. OR NOT second operand is inverted 42

43 Understanding the conditions Consider the signed (i.e. two s complement) numbers X and Y 1) Put first value in a register, say R1: MOV R1, #X 2) CMPS (compare and set) with the second value: CMPS R1, #Y 3) Apply any instruction with the suffix EQ NE GT GE LT LE: ADDLE R3, R4, R5 Is X less than Y equivalent to N V? 43

44 Addressing modes Immediate Indexed PC-relative 44

45 Addressing Modes Immediate addressing the data is contained in the instruction MOV R0,# k Flash ROM 32k 64k RAM I/O ports 0x x0003.FFFF 0x x2000.FFFF 7FFF 0x x41FF.FFFF R0 PC 0x EEPROM Internal I/O PPB 0x x F04F 0064 MOV R0,#100 0x x C 0xE xE004.0FFF 45

46 Addressing Modes Indexed addressing the address of the data in memory is in a register LDR R0,[R1] ; R0= value pointed to by R1 PC R0 R1 0x x EEPROM 0x x LDR R0,[R1] 0x x x RAM 0x x x x C 46

47 Addressing Modes Indexed addressing with offset LDR R0,[R1,#4] 47

48 Addressing Modes PC Relative Addressing the address of data in EEPROM is indexed based upon the PC B location BL subroutine ;branch ;branch and link 48

49 What does this code do? PC-relative LDR R1, =Count ;Count stores 0x LDR R0, [R1] First, LDR R1,=Count 0x ROM space R1 0x Count Second, LDR R0,[R1] RAM space R0 Why can t we just store 0x in the LDR instruction itself? 49

50 Addressing philosophy Cortex-M3/M4 has a 32-bit address space Instructions are at most 32 bits long => not enough space in an instruction for an address EEPROM accesses can be indexed using the program counter The PC always points to EEPROM and it can be used to calculate an address relative to the value in the PC RAM accesses involve storing the address in EEPROM and then accessing it using indexed addressing relative to the PC Two instructions will typically be required to access RAM or I/O 50

51 Flexible second operand <op2> Constant ADD Rd, Rn, #const ;Rd=Rn+const ADD Rd, Rn, Rm Register w/optional shift ADD R0, R1, LSL #4 ;R0=R0+(R1*16) ADD R0, R1, R2, LSL #4 51

52 Data storage philosophy Memory object Register Example operand type Constants in ROM PC =Constant [PC,#28] Local variables SP [SP,#0x04] on the stack Global variables R0 R12 [R0] in RAM I/O ports R0 R12 [R0] 52

53 53

54 Thumbnail Instructions Memory Access Instructions LDR Rd, [Rn] ;load 32-bit number at [Rn] to Rd LDR Rd, [Rn,#off] ;load 32-bit number at [Rn+off] to Rd LDR Rd, =value ;set Rd equal to 32-bit value (PC rel) LDRH Rd, [Rn] ;load unsigned 16-bit at [Rn] to Rd LDRH Rd, [Rn,#off] ;load unsign. 16-bit at [Rn+off] to Rd LDRSH Rd, [Rn] ;load signed 16-bit at [Rn] to Rd LDRSH Rd, [Rn,#off] ;load signed 16-bit at [Rn+off] to Rd LDRB Rd, [Rn] ;load unsigned 8-bit at [Rn] to Rd LDRB Rd, [Rn,#off] ;load unsigned 8-bit at [Rn+off] to Rd LDRSB Rd, [Rn] ;load signed 8-bit at [Rn] to Rd LDRSB Rd, [Rn,#off] ;load signed 8-bit at [Rn+off] to Rd Why do we need separate instructions for signed and unsigned for 8 and 16 bits? (Why not for 32 bits?) 54

55 Why do we need separate instructions for signed and unsigned 8 and 16 bits? (Why not for 32 bits?) Find the representations of -21 on: 8 bits: 16 bits: 32 bits: EOL3 55

56 QUIZ: Conditionals What number is in R1 after this code has executed? MOV R1, #10 MOV R2, #20 MOV R6, #42 MOV R7, #41 CMPS R6, R7 ADDGT R1, R2 ADD R1, R2 56

57 QUIZ: Conditionals Would the result be different if the unsigned comparison were used instead? MOV R1, #10 MOV R2, #20 MOV R6, #42 MOV R7, #43 CMPS R6, R7 ADDHI R1, R2 ADD R1, R2 57

58 QUIZ: Conditionals 58

59 QUIZ: Addressing 59

60 QUIZ: Addressing 60

61 QUIZ: Addressing ADDS R12, R11, R10 ;! 61

62 QUIZ: Addressing Why are memory accesses done in two instructions, rather than just one? Give an example, assuming that variable num1 is located in the RAM at address 0x FC (!) 62

63 X-tra credit QUIZ: Addressing In the text explanation of PC-relative addressing (p.92), the number 28 appears. What does it mean? 63

64 Thumbnail Instructions Memory Access Instructions STR Rt, [Rn] ;store 32-bit Rt to [Rn] STR Rt, [Rn,#off] ;store 32-bit Rt to [Rn+off] STRH Rt, [Rn] ;store least sig. 16-bit Rt to [Rn] STRH Rt, [Rn,#off] ;store least sig. 16-bit Rt to [Rn+off] STRB Rt, [Rn] ;store least sig. 8-bit Rt to [Rn] STRB Rt, [Rn,#off] ;store least sig. 8-bit Rt to [Rn+off] PUSH {Rt} ;push 32-bit Rt onto stack POP {Rd} ;pop 32-bit number from stack into Rd ADR Rd, label ;set Rd equal to the address at label MOV{S} Rd, <op2> ;set Rd equal to op2 MOV Rd, #im16 ;set Rd equal to im16 (0 to 65535) MVN{S} Rd, <op2> ;set Rd equal to -op2 How come there are no signed/unsigned stores (by similarity with the loads)? 64

65 Thumbnail Instructions Memory Access Instructions STR Rt, [Rn] ;store 32-bit Rt to [Rn] STR Rt, [Rn,#off] ;store 32-bit Rt to [Rn+off] STRH Rt, [Rn] ;store least sig. 16-bit Rt to [Rn] STRH Rt, [Rn,#off] ;store least sig. 16-bit Rt to [Rn+off] STRB Rt, [Rn] ;store least sig. 8-bit Rt to [Rn] STRB Rt, [Rn,#off] ;store least sig. 8-bit Rt to [Rn+off] PUSH {Rt} ;push 32-bit Rt onto stack POP {Rd} ;pop 32-bit number from stack into Rd ADR Rd, label ;set Rd equal to the address at label MOV{S} Rd, <op2> ;set Rd equal to op2 MOV Rd, #im16 ;set Rd equal to im16 (0 to 65535) MVN{S} Rd, <op2> ;set Rd equal to -op2 65

66 Wasn t there an LDR that did the same thing? 66

67 PC-relative LDR vs. ADR ADR has only PC-relative addressing mode! DCD = Define Constant Data = assembler directive Count is an address in data memory (RAM) Pi is an address in code memory (FlashROM) 67

68 PC-relative LDR vs. ADR Is it possible to translate any PC-relative LDR into an ADR? 68

69 Can you figure out how many bits are used in the ADR instruction for the offset? 69

70 Are 13 bits sufficient to represent a jump from Flash ROM to RAM? 70

71 ADR vs. LDR/STR Loading a register with a pointer to an address in FlashROM ADR Rd, label Loading a register with a constant, address, or data LDR RD, =number LDR RD, =label LDR and STR are used to load/store RAM data or constants 71

72 Thumbnail Instructions Memory Access Instructions STR Rt, [Rn] ;store 32-bit Rt to [Rn] STR Rt, [Rn,#off] ;store 32-bit Rt to [Rn+off] STRH Rt, [Rn] ;store least sig. 16-bit Rt to [Rn] STRH Rt, [Rn,#off] ;store least sig. 16-bit Rt to [Rn+off] STRB Rt, [Rn] ;store least sig. 8-bit Rt to [Rn] STRB Rt, [Rn,#off] ;store least sig. 8-bit Rt to [Rn+off] PUSH {Rt} ;push 32-bit Rt onto stack POP {Rd} ;pop 32-bit number from stack into Rd ADR Rd, label ;set Rd equal to the address at label MOV{S} Rd, <op2> ;set Rd equal to op2 MOV Rd, #im16 ;set Rd equal to im16 (0 to 65535) MVN{S} Rd, <op2> ;set Rd equal to -op2 72

73 3.3.7 The Stack Last-in-first-out (LIFO) storage In Cortex M3/M4, it works only with 32-bit data! Stack pointer (SP = R13) points to the top element already on the stack SP is decremented before more data is placed on stack Incremented after data is removed PUSH and POP instructions used to load and retrieve data 73

74 Instruction sequence PUSH {R0} PUSH {R1} PUSH {R2} POP {R3} POP {R4} POP {R5} Operation SP PUSH {R0} PUSH {R1} PUSH {R2} SP SP 2 SP 1 1 POP {R5} POP {R4} POP {R3} 0x x2000.FFFC 74

75 Instruction sequence PUSH {R0} PUSH {R1} PUSH {R2} POP {R3} POP {R4} POP {R5} If R0 R5 initially contain the numbers 0 5 (respectively), what are the contents of R0 R5 after this sequence of instructions? Operation SP PUSH {R0} PUSH {R1} PUSH {R2} SP SP 2 SP 1 1 POP {R5} POP {R4} POP {R3} 0x x2000.FFFC 75

76 Use the stack to swap the contents of two registers e.g. R11 and R12 Operation SP PUSH {R0} PUSH {R1} PUSH {R2} SP SP 2 SP 1 1 POP {R5} POP {R4} POP {R3} 0x x2000.FFFC EOL4 76

77 Use the stack to swap the contents of two registers e.g. R11 and R12 Operation SP PUSH {R0} PUSH {R1} PUSH {R2} SP SP 2 SP 1 1 POP {R5} POP {R4} POP {R3} 0x x2000.FFFC 77

78 Use the stack to reverse the contents of four registers: R9 R10 R11 R12. Draw stack after each operation. 78

79 Instruction sequence PUSH {R0} PUSH {R1} PUSH {R2} POP {R3} POP {R4} POP {R5} Operation What is the addressing mode of PUSH and POP? SP PUSH {R0} PUSH {R1} PUSH {R2} SP SP 2 SP 1 1 POP {R5} POP {R4} POP {R3} 0x x2000.FFFC 79

80 3.3.8 Branch Instructions B label ;branch to label Always BEQ label ;branch if Z == 1 Equal BNE label ;branch if Z == 0 Not equal BCS label ;branch if C == 1 Higher or same, unsign. BHS label ;branch if C == 1 Higher or same, unsign. BCC label ;branch if C == 0 Lower, unsign. < BLO label ;branch if C == 0 Lower, unsign. < BMI label ;branch if N == 1 Negative BPL label ;branch if N == 0 Positive or zero BVS label ;branch if V == 1 Overflow 80

81 Branch Instructions BVC label ;branch if V == 0 No overflow BHI label ;branch if C==1 and Z==0 unsigned > BLS label ;branch if C==0 or Z==1 unsigned BGE label ;branch if N == V signed BLT label ;branch if N!= V signed < BGT label ;branch if Z==0 and N==V signed > BLE label ;branch if Z==1 and N!=V signed BX Rm ;branch indirect to location specified by Rm BL label ;branch to subroutine at label BLX Rm ;branch to subroutine indexed by Rm 81

82 Branch instr. in a nutshell BVC label ;branch to label BX Rm ;branch indirect to location specified by Rm BL label ;branch to subroutine at label BLX Rm ;branch to subroutine indexed by Rm They can all accept conditional suffixes 82

83 What does this program do? 83

84 What does this program do? Sequence Conditional While-loop Block 1 Block 2 Block 1 Block 2 Block 84

85 What does this program do? 85

86 What does this program do? 86

87 Functions a.k.a. subroutines Do you recognize this sequence? main Num = 0 Change() Change Num = Num+25 Return Last instruction in a function is always this 87

88 One convention used in ARM-Cortex programming is that function parameters are passed in the registers R0-R3. Re-write the code below with the value of Num passed in R3. 88

89 Another convention used in ARM-Cortex programming is that the function return value is passed in R0. Re-write the code below with the value of Num passed back to the main program in R0. 89

90 Extra-credit: What is the problem with the C code? 90

91 Function management Problem: What if a function makes use of some of the registers used by the main program? Upon return, the main program should be able to continue its operation uninterrupted! Solution: Function pushes on the stack the registers it s going to use Before returning, it pops the same registers (in reverse order!) 91

92 Function management Rules for stack use Functions should have an equal number of pushes and pops Stack accesses (push or pop) should not be performed outside the allocated area Stack reads and writes should not be performed within the free area Stack push should first decrement SP, then store the data Stack pop should first read the data, and then increment SP 92

93 QUIZ: Subroutines 93

94 3.3.5 Logical Instructions AND{S} {Rd,} Rn, <op2> ; Rd=Rn&op2 (op2 is 32 bits) ORR{S} {Rd,} Rn, <op2> ; Rd=Rn op2 (op2 is 32 bits) EOR{S} {Rd,} Rn, <op2> ; Rd=Rn^op2 (op2 is 32 bits) BIC{S} {Rd,} Rn, <op2> ; Rd=Rn&(~op2) (op2 is 32 bits) ORN{S} {Rd,} Rn, <op2> ; Rd=Rn (~op2) (op2 is 32 bits) LSR{S} Rd, Rm, Rs ; logical shift right Rd=Rm>>Rs (unsigned) LSR{S} Rd, Rm, #n ; logical shift right Rd=Rm>>n (unsigned) ASR{S} Rd, Rm, Rs ; arithmetic shift right Rd=Rm>>Rs (signed) ASR{S} Rd, Rm, #n ; arithmetic shift right Rd=Rm>>n (signed) LSL{S} Rd, Rm, Rs ; shift left Rd=Rm<<Rs (signed, unsigned) LSL{S} Rd, Rm, #n ; shift left Rd=Rm<<n (signed, unsigned) 94

95 QUIZ: Logical Instructions AND{S} {Rd,} Rn, <op2> ; Rd=Rn&op2 (op2 is 32 bits) ORR{S} {Rd,} Rn, <op2> ; Rd=Rn op2 (op2 is 32 bits) EOR{S} {Rd,} Rn, <op2> ; Rd=Rn^op2 (op2 is 32 bits) BIC{S} {Rd,} Rn, <op2> ; Rd=Rn&(~op2) (op2 is 32 bits) ORN{S} {Rd,} Rn, <op2> ; Rd=Rn (~op2) (op2 is 32 bits) LSR{S} Rd, Rm, Rs ; logical shift right Rd=Rm>>Rs (unsigned) LSR{S} Rd, Rm, #n ; logical shift right Rd=Rm>>n (unsigned) ASR{S} Rd, Rm, Rs ; arithmetic shift right Rd=Rm>>Rs (signed) ASR{S} Rd, Rm, #n ; arithmetic shift right Rd=Rm>>n (signed) LSL{S} Rd, Rm, Rs ; shift left Rd=Rm<<Rs (signed, unsigned) LSL{S} Rd, Rm, #n ; shift left Rd=Rm<<n (signed, unsigned) Write a program to flip all bits in R0 95

96 QUIZ: Logical Instructions AND{S} {Rd,} Rn, <op2> ; Rd=Rn&op2 (op2 is 32 bits) ORR{S} {Rd,} Rn, <op2> ; Rd=Rn op2 (op2 is 32 bits) EOR{S} {Rd,} Rn, <op2> ; Rd=Rn^op2 (op2 is 32 bits) BIC{S} {Rd,} Rn, <op2> ; Rd=Rn&(~op2) (op2 is 32 bits) ORN{S} {Rd,} Rn, <op2> ; Rd=Rn (~op2) (op2 is 32 bits) LSR{S} Rd, Rm, Rs ; logical shift right Rd=Rm>>Rs (unsigned) LSR{S} Rd, Rm, #n ; logical shift right Rd=Rm>>n (unsigned) ASR{S} Rd, Rm, Rs ; arithmetic shift right Rd=Rm>>Rs (signed) ASR{S} Rd, Rm, #n ; arithmetic shift right Rd=Rm>>n (signed) LSL{S} Rd, Rm, Rs ; shift left Rd=Rm<<Rs (signed, unsigned) LSL{S} Rd, Rm, #n ; shift left Rd=Rm<<n (signed, unsigned) Write a program to flip all odd bits in R0 96

97 QUIZ: Logical Instructions AND{S} {Rd,} Rn, <op2> ; Rd=Rn&op2 (op2 is 32 bits) ORR{S} {Rd,} Rn, <op2> ; Rd=Rn op2 (op2 is 32 bits) EOR{S} {Rd,} Rn, <op2> ; Rd=Rn^op2 (op2 is 32 bits) BIC{S} {Rd,} Rn, <op2> ; Rd=Rn&(~op2) (op2 is 32 bits) ORN{S} {Rd,} Rn, <op2> ; Rd=Rn (~op2) (op2 is 32 bits) LSR{S} Rd, Rm, Rs ; logical shift right Rd=Rm>>Rs (unsigned) LSR{S} Rd, Rm, #n ; logical shift right Rd=Rm>>n (unsigned) ASR{S} Rd, Rm, Rs ; arithmetic shift right Rd=Rm>>Rs (signed) ASR{S} Rd, Rm, #n ; arithmetic shift right Rd=Rm>>n (signed) LSL{S} Rd, Rm, Rs ; shift left Rd=Rm<<Rs (signed, unsigned) LSL{S} Rd, Rm, #n ; shift left Rd=Rm<<n (signed, unsigned) Write a program to set (=1) the 8 upper bits in R0, and leave all the rest unchanged. 97

98 Homework for Ch.3 End of chapter: 6, 9, 10, 22, 23, 25 Not from text: Write a function in assembly Main program passes values of two integers in R1 and R2 Function returns their sum in R0 98

Exam 1 Fun Times. EE319K Fall 2012 Exam 1A Modified Page 1. Date: October 5, Printed Name:

Exam 1 Fun Times. EE319K Fall 2012 Exam 1A Modified Page 1. Date: October 5, Printed Name: EE319K Fall 2012 Exam 1A Modified Page 1 Exam 1 Fun Times Date: October 5, 2012 Printed Name: Last, First Your signature is your promise that you have not cheated and will not cheat on this exam, nor will