ARM Cortex-M4 Architecture and Instruction Set 3: Branching; Data definition and memory access instructions

Transcription

1 ARM Cortex-M4 Architecture and Instruction Set 3: Branching; Data definition and memory access instructions M J Brockway February 17, 2016

2 Branching To do anything other than run a fixed sequence of instructions, the CPU needs to be able decide on the result of some test what instruction to execute next. In normal operaton, an instruction is fetched from the address pointed at by the Program Counter (PC = R15), and the PC immediately incremented by the size of that instruction: 2 or 4 bytes. Then the next instruction is the next in the RAM. A branch instruction overrides this by setting the PC to some other value - some other valid instruction address, we hope. This may be a conditonal branch: it only happens if some condition is met. In these cases, the next instruction to be fetched is the one whose address was loaded into the PC by the branch instruction.

3 Branching Syntax B{cond} label BL{cond} label BX{cond} Rm BLX{cond} Rm where: cond is an optional condition code, EQ, NE, LT, LE, GE, GT,... as seen before - reminder on next slide. Rm is a register containing the address to branch to. Curiously, the contents must have bit[0] == 1 (an odd number) although the address actually branched to has this bit set to 0 (The register contents are ANDed with 0xFFFFFFFE).

4 Condition Code Suffixes - reminder EQ equal: Z==1 NE not equal: Z==0 HS higher or same, unsigned: C==1 HI higher, unsigned: C==1 and Z==0 LO lower, unsigned: C==0 LS lower or same, unsigned: C==0 or Z==1 MI negative: N==1, PL positive or zero: N==0, VS overflow: V==1 VC no overflow: V==0 GE greater than or equal, signed: N==V GT greater than, signed: N==V and Z==0 LE less than or equal, signed: N!=V or Z==1 LT less than, signed: N!=V

5 Branching B and BL branch to the address indicated by the label - the PC-address of the instruction immediately after the label. The actual branch instruction operates using a PC-relative address: the address to branch to is specified as an offset relative to the current value of the PC of the branch instruction itself. PC-addresses can be stored in registers; hence BX and BLX options: these copy the value (an address) of the operand register to the PC, actually R15, and this causes the branch. BL and BLX branch to the label provided, or the address in the register, but first they copy the PC value to the link register, LR = R14. Typically BL is used to branch to a subroutine; returning from the subroutine then consists in using BX to branch to the address in LR. More of this later.

6 Branching - Example This code, which you have seein in the first lecture and lab in this series, has two examples of B, one with a condition suffix E0 main FUNCTION E0 ; initialize registers E0 F04F 000A MOV r0, # E4 F04F 0100 MOV r1, # E8 ; Calculating E8 loop E ADD r1, r EA 3801 SUBS r0, # EC D1FC BNE loop EE ; Result is now in R EE deadloop EE E7FE B deadloop F0 ENDFUNC F0 END

7 Branching - Example Having explored this example with the Microvision debugger, you may have noticed that at line 9, PC = 0x000000E4. This is because when an instruction is fetched, the PC is updated to the address of the next instruction. For this reason, a detailed look with the debugger shows the PC values (second column) changing as follows as execution progresses: 7 main FUNCTION 8 ; initialize registers E4 F04F 000A MOV r0, # E8 F04F 0100 MOV r1, #0 11 ; Calculating loop EC 4401 ADD r1, r EE 3801 SUBS r0, # F0 D1FC BNE loop 16 ; Result is now in R1 17 deadloop F2 E7FE B deadloop 19 ENDFUNC

8 Branching - Example... The PC values are all larger than the original assembly address by the size of the instruction. Line 12 declares loop to be a label; Line 15 indicates a BNE, a conditional (on NE: Z flag is clear) branch to the label loop; The binary version of this BNE instruction is D1FC. The second byte, FC, is numerically -4 (think: two s complement!). The BNE instruction has PC-address F0 (in hex); 4 back from here is EC: the ADD instruction following label loop! F0 + FC = EC in byte-sized 2 s-complement arithmetic Exercise for you: see if you can understand the branch at address F2 in similar fashion. This code runs on the spot for ever, by branching to PC-2 repeatedly.

9 Memory Access Instructions with immediate offset Syntax 1. op{type}{cond} Rt, [Rn] - no offset or write-back 2. op{type}{cond} Rt, [Rn, #offset] - immediate offset, no write-back 3. op{type}{cond} Rt, [Rn, #offset]! - pre-indexed 4. op{type}{cond} Rt, [Rn], #offset - post-indexed where: op is one of LDR - load register Rt from [...] STR - store register Rt to [...] type is one of B - unsigned byte (0-extended to 32 bits) SB - signed byte (on load, sign-extended to 32 bits) H - unsigned halfword (0-extended to 32 bits) SB - signed halfword (on load, sign-extended to 32 bits) omitted if whole word is to be loaded or stored Optional cond condition is EQ, NE,... as we defined above. Rt is register to load to or store from.

10 Memory Access Instructions with immediate offset The operand in [... ] specifies a memory address to load from or store to. Think of [addr] as the data at memory address addr. Register Rn contains a base memory address; offset is a value in range -255 to 1020, used to offset from the address in Rn. Thus the target memory address for load or store is (Rn) in the first form of the instruction, or (Rn + offset). Form number 1. simply loads/stores Rt from/to the memory location pointed at by Rn; 2. loads/stores Rt from/to the memory location pointed at by (Rn + offset); 3. increments Rn by offset, then loads/stores Rt from/to the memory location pointed at by Rn; 4. loads/stores Rt from/to the memory location pointed at by Rn then increments Rn by offset; The N,Z,C,V flags are not affected.

11 Examples LDR R8, [R10] load R8 from memory address R10 STR R2, [R5, #4] store R2 to memory address R5+4 Value in R5 is unchanged LDR R2, [R5, #4]! Add 4 onto contents of R5, then load R2 from memory address R5 STR R2, [R5], #-4 load R2 from memory address R5 then decrement contents of R5 by 4

12 Data Definitions These instructions assume we have a register containing an address pointing at an item of data, or perhaps an array of data. One way this comes about is via the assembler directives which define and reserve memory for data. {label} DCD expr{, expr}... {label} DCDU expr{, expr}... defines a 32-bit word or a sequence of words with optional label giving address. expr is a numeric expression The version without U adds padding so that the data is aligned on a word boundary, an address that is a multiple of 4. Usually the unaligned version is the simpler one to use. Example numarray DCDU , , , LDR R0, =numarray ;loads address of data into R0 LDR R1, [R0, #4] ;loads into R1 Why #4?

13 Data Definitions - example Adding up some numbers... numarray DCDU , , , , 0 We can use a post-incrementing to iterate through the array: MOV R2, #0 LDR R1, =numarray loop LDR R0, [R1], #4 ADD R2, R0 CMP R0, #0 BNE loop

14 Data Definitions ctd The ALIGN assembler directive can be used to make DCD work predictably: ALIGN 4 numarray DCD , , , , 0... The lab sheet accompanying this lecture explores this further.

15 Data Definitions - half-words {label} DCW expr{, expr}... {label} DCWU expr{, expr}... defines a 16-bit halfword or a sequence of words with optional label giving address. expr is a numeric expression The version without U adds padding so that the data is aligned on a halfword boundary, an address that is a multiple of 2. Usually the unaligned version is the simpler one to use. Example numarray DCWU 1000, 999, 998, 997 LDR R0, =numarray ; loads address of data into R0 LDR R1, [R0] ; loads 0x03E703E8 into R1 Why this?

16 Data Definitions - half-words On the other hand, LDRH R1, [R0] ; loads 0x03E8 into R1 The adding-up example can be adapted to work with half-words: numarray DCWU 1000, 999, 998, 997, 0 Iterate over data as before, but load haflwords and post-increment by their size, 2 rather than 4: MOV R2, #0 LDR R1, =numarray loop LDRH R0, [R1], #2 ADD R2, R0 CMP R0, #0 BNE loop

17 Data Definitions - bytes {label} DCB expr{, expr}... defines a byte or a sequence of bytes. Optional label gives address where byte(s) stored. expr must evaluate to a value between -128 and 255 Examples littlenum DCB 42 littlebytearray DCB 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 hellostg DCB "hello world", 0 LDR R0, =littlenum ;loads address of data into R0 LDR R1, [R0] ;loads data into R1 Careful! R1 ends up containing 0x A. Why?

18 Data Definitions - bytes The adding-up example can be adapted to work with bytes: numarray DCDU 10,9,8,7,6,5,4,3,2,1,0 Iterate over data as before, but load bytes and post-increment by their size, 1: MOV R2, #0 LDR R1, =numarray loop LDRB R0, [R1], #1 ADD R2, R0 CMP R0, #0 BNE loop

19 References DUI0553A cortex m4 dgug.pdf: The Cortex M4 Generic User Guide The second item is the on-line manual for the Microvision assembler, and is easy to find with Google. In connection with this lecture see especially the GUG sections 3.10, 3.4 and sections 12.15, of the assembler manual.