MNEMONIC OPERATION ADDRESS / OPERAND MODES FLAGS SET WITH S suffix ADC

Transcription

1 ECE425 MNEMONIC TABLE MNEMONIC OPERATION ADDRESS / OPERAND MODES FLAGS SET WITH S suffix ADC Adds operands and Carry flag and places value in destination register ADD Adds operands and places value in destination register ADR Pseudocode to load an None address into a Example: ADR R0, 0x AND Logic AND of operands is placed in destination register C B Branches to new location None. label address -> PC indicated by label: B XYZ BL Branches to new location indicated by label: BL XYZ Saves address of instruction after Branch Link instruction in Link Register (R14) None. PC-04 -> LR Label address -> PC BIC BX CMN CMP EOR LDM LDMEA empty ascending LDMFA Full ascending Performs bitwise AND of source register with COMPLIMENT of operand Stores result in destination. Branch and exchange. Used for returning from subroutines: BX LR Adds value or register or shifter operand with Rs. Flags set by result. Register values NOT affected Subtracts value or register or shifter operand from Rs. Flags set by result. Register values NOT affected Exclusive OR of operands is placed in destination register Loads list of registers FROM memory. Registers ALWAYS loaded in ASCENDING order from lowest memory location to highest. Two letter code indicates C = shifter carry out 1 NOTE: No destination register, Rd 1 NOTE: No destination register, Rd NZCV NOTE: no S required NZCV NOTE: no S required C

2 LDMED Empty descending LDMFD Full descending LDR CODE}B CODE}H CODE}SB CODE}SH LDR MLA MOV MRS Rd,CPSR MRS Rd,SPSR type of stack being used. Use! to indicate memory base address (usually stack pointer) is updated. ^ at end of instruction also moves SPSR back to CPSR when returning from exceptions. Example: LDMEA SP!,{R0-R4} Loads from memory effective operands nto destination Loads unsigned byte (8 bits) from memory effective Loads unsigned half word (16 bits) from memory effective Loads signed byte (8 bits) from memory effective Loads signed half word (16 bits) from memory effective Pseudo-code for loading values into registers Multiply Accumulate. Values in two registers are multiplied to form 32 bit result which is added to a third register and placed in destination Moves values from registers or immediate into destination Moves value of CPSR or SPSR into general purpose register LDR Rd, =val C unpredictable C

3 MSR CPSR_<fields>, <source> MSR SPSR_<fields>, <source> Moves value from source to CPSR or SPSR. Fields mask bits in status register: _c = control mask _x = extension mask _s = status mask _f = flags (legal in User Mode) Register or immediate MNEMONIC OPERATION ADDRESS / OPERAND MODES FLAGS SET WITH S suffix MUL Multiply values in two registers to produce 32 bit result which is stored in destination register NZ C unpredictable MVN ORR RSB RSC SBC SMLAL SMULL Moves 1 s complement of source registers or immediate into destination Logic OR of operands placed in destination Reverse subtract. Subtracts source register FROM second operand and stores result in destination. Used for immediate: Example RSB R1,R5,#0x1 means R1 = 0x1 R5 Reverse subtract with carry. Subtracts source register plus NOT carry from second source and stores result in destination Subtract with carry. Subtracts second source plus NOT carry from source register and stores result in destination Signed multiply accumulate long. Values from two registers are multiplied to produce 64 bit result which is added to value in two register and stored back in the two registers. Signed multiply long. Values from two registers are C shifter carry out C shifter carry out NZ CV unpredictable NZ

4 multiplied to produce 64 bit result which is stored in the two destination registers. CV unpredictable MNEMONIC OPERATION ADDRESS / OPERAND MODES FLAGS SET WITH S suffix STM STMEA empty Stores list of registers TO memory. Registers ALWAYS loaded in ASCENDING order ascending from lowest memory location STMFA to highest. Full ascending Two letter code indicates STMED type of stack being used. Empty descending Use! to indicate memory STMFD base address (usually stack Full descending pointer) is updated. Example: STMEA SP!,{R0-R4} STR STR{COND. CODE}B STR{COND. CODE}H SUB{COND. CODE} SWI TST{COND. CODE} Stores value in Rd into effective address calculated from operands. Stores least significant byte (8 bits) in Rd into effective operands. Stores least significant half word (16 bits) in Rd into effective address calculated from operands. Subtracts second operand from the first and stores the result in the destination Causes software interrupt. 24 bit immediate value can be read by service by tracing back to instruction through LR to determine number of SWI or what service is required. e.g. SWI #0x12 Performs logical AND of source and operand and sets the NZC flags accordingly. No register values are affected. Immediate 1 No destination register NZC V flag is Note: No S suffix required.

5 ADDRESS /OPERAND MODE 1 MODE FORMAT MEANING Immediate XXX Rd,Rs,#val Rd = Rs <operation> #val Register XXX Rd,Rs,Rx Rd = Rs <operation> Rx Shift immediate XXX Rd,Rs,Rx,LSL#n Rd = Rs<operation>(Rx shifted by n) Shift Register XXX Rd,Rs,Rx,LSL Rn Rd = Rs<operation>(Rx shifted by value in Rn) ADDRESS/OPERAND MODE 2 PRE-INDEX MODE FORMAT MEANING Immediate offset XXX Rd,[Rs,#val]{!} Rd [Rs + #val] With!, Rs = Rs+val Register offset XXX Rd,[Rs,Rx]{!} Rd [Rs + Rx] With!, Rs = Rs+Rx, Rx is unchanged Scaled register offset XXX Rd,[Rs,Rx,LSL#n]{!} Rd [Rs+(Rx shifted by n)] With!, Rs = Rs +(Rx shifted by n)], Rx is unchanged ADDRESS/OPERAND MODE 2 POST-INDEX MODE FORMAT MEANING Immediate offset XXX Rd,[Rs],#val Rd [Rs] Rs = Rs+val Register offset XXX Rd,[Rs],Rx Rd [Rs] Rs = Rs+Rx, Rx is unchanged Scaled register offset XXX Rd,[Rs],Rx,LSL#n Rd [Rs] Rs = Rs +(Rx shifted by n)], Rx is unchanged SHIFTS LSL LSR ASR carry. Shifts left by n bits, inserting 0 at least significant bit. Most significant bit is shifted into carry. Shifts right by n bits, inserting 0 at most significant bit. Least significant bit is shifted into carry. Shifts right by n bits. Most significant bit remains unchanged. Least significant bit is shifted into

6 ROR RRX bit. Rotates right by n bits. Least significant bit moves to carry and to most significant bit. Rotates right by n bits. Least significant bit moves to carry and carry moves to most significant

7 CONDITIONAL EXECUTION Mnemonics come after operation code and before S or byte size codes, if any. Examples: ADDEQS LDRNE LDRGTB R0,R1,R2 R0,[R1] R0,[R1] MNEMONIC FLAG CONDITION MEANING EQ Z set Equal NE Z clear Not equal CS or HS C set Unsigned >= CC or LO C clear Unsigned < MI N set Negative PL N clear Positive or zero VS V set Overflow VC V clear No overflow HI C set and Z clear Unsigned > LS C clear and Z set Unsigned <= GE N>= V Signed >= LT N not = V Signed < GT Z clear and N=V Signed > LE Z set and N not =V Signed <= AL Always Default